Abstract: An ion beam generation apparatus comprising an ion source (20) for generating ions, and a tetrode extraction assembly (11) comprising four electrodes for extracting and accelerating ions from the ion source. The extraction assembly comprises a source electrode (22) at the potential of the ion source, an extraction electrode (23) adjacent to the source electrode to extract ions from the ion source (20), a ground electrode (25), and a suppression electrode (24) between the extraction electrode and the ground electrode. Each electrode has an aperture to allow the ion beam to pass therethrough. The gap between the extraction (23) and suppression (24) electrodes is variable in the direction of ion beam travel.

Abstract: The present invention is an article of manufacture for use in alerting a person of exposure to an excessive amount of ultraviolet radiation. In one embodiment, the article of manufacture comprises a first strip comprising a backing member and first and second patches. Each of the first and second patches comprise an ultraviolet sensitive material releasably disposed upon the backing member. Each of the first and second patches comprise first and second outside edges and an inside edge. The first and second patches are nested and adjoined along said inside edges of the first and second patches, respectively. The ultraviolet sensitive material is adapted to change from a first color to a second color when exposed to an excessive amount of ultraviolet radiation. In operation, a person may remove the first and second patches from the backing member as desired and apply the patch to an area of exposed skin.

Abstract: A calibration pattern is drawn on a substrate using a charged particle beam. The substrate is developed, and the position of the developed calibration pattern is detected to check the relationship between the position of the stage and the reference position of the charged particle beam. On the basis of the check result, the reference position of the charged particle beam is corrected, and a pattern is drawn on the substrate on which the pattern is to be drawn.

Abstract: The present invention relates to detecting defects on a wafer. A wafer stage includes markings which are used to form a reference coordinate system. The wafer is positioned on the wafer stage and the wafer is scanned to detect a defect on the wafer. The position of the detected defect is mapped relative to the reference coordinate system of the stage. The location of a reference point on the wafer also is determined in the reference coordinate system. The position of the defect is determined relative to the reference point on the wafer so as to facilitate repeatedly locating the defect on the wafer as the wafer is loaded and reloaded into inspection and processing tools.

Abstract: A measuring instrument (100) and a method for measuring features (19) on a substrate (9) are described. The measuring instrument (100) has a support element (15) that is provided opposite the substrate (9). Mounted on the support element (15) is a nonoptical measurement device (23) with which a measurement of the features (19) of the substrate (9) is performed under ambient air pressure. The nonoptical measurement device (23) can be configured, for example, as an AFM (24) or an electron beam lens (40). Furthermore, in addition to the nonoptical measurement device (23), an optical lens (10) can be provided that is used for rapid location and determination of the coarse position of features (19) on the substrate (9).

Abstract: A convergent charged particle beam apparatus and method includes an electron beam image observation arrangement which observes an electron beam image of a surface of a specimen mounted on a movable stage inside of a vacuum chamber when an electron beam converged by an electron optical system is irradiated and scanned over the surface of the specimen and detecting secondary charged particles produced from the specimen so as to provide electron image data of the surface. A height detector optically detects a surface height of the specimen by irradiating light from outside of the vacuum chamber onto the specimen and detecting reflected light from the specimen with a detector disposed outside of the vacuum chamber. A controller controls a focal point of the converged and focused electron beam in accordance with the output from the height detector, and a display displays the electron image of the surface of the specimen.

Abstract: An ultraviolet radiation generating system and methods is disclosed for treating a coating on a substrate, such as a coating on a fiber optic cable. The system comprises a microwave chamber having one or more ports capable of permitting the substrate to travel within or through a processing space of the microwave chamber. A microwave generator is coupled to the microwave chamber for exciting a longitudinally-extending plasma lamp mounted within the processing space of the microwave chamber. The plasma lamp emits ultraviolet radiation for irradiating the substrate in the processing space. A reflector is mounted within the processing space of the microwave chamber and is capable of reflecting ultraviolet radiation to uniformly irradiate the substrate in a surrounding fashion. When the system is operating, the microwave chamber is substantially closed to emission of microwave energy and ultraviolet radiation.

Abstract: A wafer scanning support unit of an ion implantation apparatus includes a vacuum chamber having an opening in one side thereof for admitting an ion beam, and a wafer scanning support disposed within the vacuum chamber for supporting a wafer at an inclination and moving the wafer up and down in front of the ion beam so that the wafer is scanned. The wafer scanning support includes a scan shaft pivotally mounted about a horizontal axis so that it can be inclined relative to the vertical, an elevating member slidingly coupled to the scan shaft so as to be movable therealong, a driving motor for moving the elevating member up and down along the scan shaft, and a wafer holder connected to the elevating member so as to be movable therewith. The inclined wafer holder is moved along an inclined path corresponding to the inclination of the scan shaft, so that the ion beam travels substantially the same distance to impinge all portions of the wafer including the uppermost and bottommost parts.

Abstract: The operating lifetime of a hot cathode discharge ion source is extended by introducing nitrogen into an ion implantation apparatus after introduction of an ion implantation gas, such as GeF4, is stopped. The nitrogen is preferably introduced along with the GeF4 during implantation as well.

Abstract: A mask stage speed |Vm|, a wafer stage speed |Vw|, and an absolute value |&Dgr;S| of a beam deflection value are determined (step 101). Then, it is judged whether a stripe number is even or odd (step 108) and deflective directions of a mask stage, a wafer stage, and a wafer deflector are set in accordance with the above judgment result (steps 109 and 110). Then, the wafer stage and mask stage respectively start continuous movement (step 113) and divided patterns are exposed (step 115-119). It is judged whether all divided patterns are exposed (step 120). When all divided patterns are not exposed, the next divided pattern is exposed by adding a deflection value on a wafer corresponding to a beam width on a mask (step 121).

Abstract: Mounting and alignment structures for optical components allow optical components to be connected to an optical bench and then subsequently aligned, i.e., either passively or actively, in a manufacturing or subsequent calibration or recalibration, alignment or realignment processes. The structures comprise quasi-extrusion portions. This portion is “quasi-extrusion” in the sense that it has a substantially constant cross section in a z-axis direction as would be yielded in an extrusion manufacturing process. The structures further comprise at least one base, having a laterally-extending base surface, and an optical component interface. At least one armature connects the optical component interface with the base. In the preferred embodiment, the base surface is securable to an optical bench.

Abstract: A surface position detecting method wherein an object having a region with a pattern structure formed thereon is relatively scanned relative to a surface position detecting device and surface positions of the object at plural detection points in the region are detected by use of the surface position detecting device.

Abstract: A device and a method for automatically adapting a light sensor to the light transmission properties of a windshield include determining the light transmission properties of the windshield for light having at least two different wavelengths. Light intensities of each of at least two different wavelengths of a light beam transmitted by a transmitter along a path through the windshield are measured by a light receiver. The measured light intensities are compared with reference light intensity values associated with clear glass. Transmission properties of the windshield are then calculated based on the comparison between the measured light intensities and the reference light intensity values. The light sensor is then adapted as a function of the calculated transmission properties of the windshield.

Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of AlxByInzGa1-x-y-zN, InGaN1-a-bPaAsb, or AlxByInzGa1-x-y-zN1-a-bPaAsb.

Abstract: Bipolar and field effect molecular wire transistors are provided. The molecular wire transistor comprises a pair of crossed wires, with at least one of the wires comprising a doped semiconductor material. The pair of crossed wires forms a junction where one wire crosses another, one wire being provided with Lewis acid functional groups and the other wire being provided with Lewis base functional groups. If both wires are doped semiconductor, such as silicon, one is P-doped and the other is N-doped. One wire of a given doping comprises the emitter and collector portions and the other wire comprises the base portion, which is formed by modulation doping on the wire containing the emitter and collector at the junction where the wires cross and between the emitter and collector portions, thereby forming a bipolar transistor. Both NPN and PNP bipolar transistors may be formed.

Abstract: An integrated circuit includes a layered superlattice material having the formula A1w1+a1A2w2+a2 . . . Ajwj+ajS1x1+s1S2x2+s2 . . . Skxk+skB1y1+b1B2y2+b2 . . . Blyl+blQz−q, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . B1 represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.

Abstract: An improved negative differential resistance field effect transistor (NDR-FET) is disclosed. The NDR FET includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. In this fashion, charge traps can be optimized for extremely rapid trapping and de-trapping of charge because they are extremely close to a channel of hot carriers. The NDR-FET is also useable as a replacement for conventional NDR diode and similar devices in memory cells, and enables an entire family of logic circuits that only require a single channel technology (i.e., instead of CMOS) and yet which provide low power.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (204) on a silicon wafer (202). The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (206) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: A method of depositing a thin film on a substrate in a semiconductor device using Atomic Layer Deposition (ALD) process parameters exposes the substrate to at least one adherent material in a quantity sufficient for the material to adsorb onto the substrate and thereby form an initiation layer. The initiation layer presents at least one first reactive moiety which is then chemically reacted with at least one first reaction material using atomic layer deposition conditions to form a second reactive moiety. The second reactive moiety is then chemically reacted with at least one second reaction material under process conditions sufficient to form a reaction layer over the initiation layer. The process may be repeated to form successive reaction layers over the initiation layer. The adherent material constituting the initiation layer is preferably one which is not substantially degraded by the atomic layer deposition parameters.

Abstract: An organic light-emitting diode with high luminance and high efficiency comprising an anode, an organic pn-junction and a cathode layered sequentially in this order, wherein the organic pn-junction emits light by an electric current passing through the diode in an electric field applied between the anode and the cathode, characterized in that the organic pn-junction is composed of an organic p-type luminescent-semiconductor thin film and an organic n-type luminescent-semiconductor thin film, wherein one surface of the organic p-type luminescent-semiconductor thin film is in contact with the anode and another surface of the organic p-type luminescent-semiconductor thin film is in contact with the organic n-type luminescent-semiconductor thin film, and one surface of the organic n-type luminescent-semiconductor thin film is in contact with the cathode and another surface of the organic n-type luminescent-semiconductor thin film is in contact with the organic p-type luminescent-semiconductor thin film and wherei

Abstract: A method of patterning a preselected material on a substrate is provided, comprising coating a substrate surface with a releasable polymer coating, creating one or more openings through the polymer coating to expose a portion of the substrate surface in a predefined pattern, coating at least a portion of the substrate surface that is exposed through the polymer coating with at least one preselected material, and optionally, removing said polymer coating so that the material is retained on said substrate surface in said predefined pattern.

Abstract: The present invention relates to a semiconductor device, and more particularly, to a test pattern for evaluating a process of silicide film formation. The test pattern in accordance with the present invention includes: a silicon substrate having an active region and a field region; a first pattern composed of a cross resistor pattern of a polycide layer formed on the field region; and a second pattern composed of polycide layer and a silicide layer formed on the active region. The second pattern includes: a pair of polycide patterns composed of a first polycide strip and a second polycide strip extended in parallel, being spaced from each other a predetermined interval on an insulating film formed on the active region; and an active silicide strip formed between the first polycide strip and the second polycide strip.

Abstract: A method for measuring bridge induced by mask layout amendment. Provide a mask with a layout that comprises a conductor line pattern, numerous gate patterns which are connected with conductor line pattern, and numerous contact pattern groups, each contact pattern group has numerous contact patterns and at least surrounds one terminal, which does not contact with conductor line, of one corresponding gate pattern. Then, amend this layout and transfer amended layout into a substrate to form a conductor line, numerous gates and numerous contact groups in and on this substrate. Finally, electrically couple these contact groups with a terminal, then, apply an electrical signal into this conductor line and measure whether the electrical signal appears at this terminal.

Abstract: A flat panel display device comprising a thin film semiconductor switching element formed on a surface of a substrate, a display electrode connected with the switching element, a semiconductor layer for auxiliary capacity which is electrically connected with the display electrode, a dielectric layer formed on a surface of the semiconductor layer for auxiliary capacity, and a metal layer formed on a surface of the dielectric layer, wherein the auxiliary capacity is constituted by the semiconductor layer for auxiliary capacity, the dielectric layer, and the metal layer, and the semiconductor layer for auxiliary capacity is implanted all over the surface thereof with a high concentration of impurity ion.

Abstract: A semiconductor integrated circuit comprising thin-film transistors in each of which the second wiring is prevented from breaking at steps. A silicon nitride film is formed on gate electrodes and on gate wiring extending from the gate electrodes. Substantially triangular regions are formed out of an insulator over side surfaces of the gate electrodes and of the gate wiring. The presence of these substantially triangular side walls make milder the steps at which the second wiring goes over the gate wiring. This suppresses breakage of the second wiring.

Abstract: Disclosed is a thin-layer solar cell array system and a method for producing the same, having placed over a carrier substrate of plane design, a solar cell layer which is provided with at least one n-type conducting semiconductor zone (emitter) and at least one p-type conducting semiconductor zone (base) as well as a first and a second contact electrode, each of different electric polarity, which are each electrically connected to the emitter respectively to the base.

Abstract: A semiconductor device possessing a semiconductor substrate consisting of a single element semiconductor; directly formed on the semiconductor substrate, a buffer layer consisting of a compound semiconductor possessing a lattice constant differing from the lattice constant of the single element semiconductor; laminated on the buffer layer, an active layer consisting of the same compound semiconductor as the buffer layer, which functions as a semiconductor element; and, disposed between the buffer layer and the active layer, a barrier layer forming a voltage barrier against the active layer so as to control the flow of current from the active layer to the semiconductor substrate: and in the case where this is utilized as a Hall element, a semiconductor device is obtained which maintains good carrier mobility as a Hall element, and also, the leakage current to the substrate can be controlled, and therefore sufficient Hall electromotive force can be obtained.

Abstract: A semiconductor device such as an IGBT, for realizing measurement precision for forward voltage effect characteristics using a relatively small current. It includes a second conductivity type of first anode region formed to partially constitute the upper surface of a first conductivity type of semiconductor substrate and having an anode electrode formed on its upper surface, a second anode region formed within said first anode region, and an anode electrode formed on said second anode region. The second anode region is electrically isolated from the first anode region, and the anode electrode formed on the upper surface of the second anode region is independent of the anode electrode formed on the upper surface of the first anode region. In such semiconductor device having said second anode region, even though a small force current, measurement can be performed at a current density which is equal to or close to a rated current.

Abstract: A III-N compound semiconductor bipolar transistor structure and method of manufacture. An epitaxial layer structure is formed over a substrate. The epitaxial layer structure includes a nucleation layer, a buffer layer, an emitter layer containing first type dopants (conductive type) and a base layer containing second type dopants (conductive type). Ion implantation is conducted to form a first conductive region within the base layer for forming a collector terminal. A portion of the emitter layer is etched for forming an emitter terminal. In addition, two ion-implantation regions may form inside the base layer. The ion-implantation regions serve separately as the collector terminal and the emitter terminal of the bipolar transistor, respectively, so that a more planar transistor structure is formed.

Abstract: The invention relates to a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element (1), formed on a semiconductor surface (2), for storing a data bit; the non-volatile memory element (1) including a fuse wire (3) and a heating wire (4); the fuse wire (3) being arranged as a planar line, and further being arranged as a memory element to be programmable by blowing the fuse wire (3) through joule heating induced by a current flow; the heating wire (4) being arranged as a heater spatially surrounding the fuse wire (3), and the heating wire (4) being arranged to generate additional heat by current flow induced joule heating and to provide said additional heat to the fuse wire (3) during programming of the fuse wire (3).

Abstract: In one embodiment of the invention, an embedded enclosure includes a power plane and first and second ground planes. The power plane has a power surface and a power periphery, and couples power to signals of an integrated circuit operating at a fundamental frequency. The first and second ground planes have first and second ground surfaces and first and second ground peripheries, respectively. The first and second ground planes couple ground to the signals. The first and second ground planes are separated from the power plane by first and second distances, respectively. The first and second ground surfaces are larger than the power surface. The first and second ground peripheries extend at least third and fourth distances from the power periphery, respectively. The third and fourth distances are N and M times larger than the first and second distances, respectively.

Abstract: A transistor 28a including a first gate electrode 26 is formed on a substrate 10 through a gate insulation film 24. An insulation film 30 is formed on the transistor 28a and the substrate 10. A plurality of first wirings 40a, 40b are formed on the insulation film 30, spaced from each other by a first gap d1. A second wiring 42 is formed, spaced from either of the first wiring 40a, 40b by a second gap d2 which is substantially equal to the first gap d1. Either of the first wirings 40a, 40b is electrically connected to the first gate electrode 26, and the second wiring 42 is electrically connected to the substrate 10.

Abstract: An etching mask having high etching selectivity for an inorganic interlayer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.

Abstract: A high-vacuum packaged microgyroscope for detecting the inertial angular velocity of an object and a method for manufacturing the same. In the high-vacuum packaged microgyroscope, a substrate with an ASIC circuit for signal processing is mounted onto another substrate including a suspension structure of a microgyroscope in the form of a flip chip. Also, the electrodes of the suspension structure and the ASIC circuit can be exposed to the outside through polysilicon interconnection interposed between double passivation layers. The short interconnection between the suspension structure and the ASIC circuit can reduce the device in size and prevents generation of noise, thereby increasing signal detection sensitivity. In addition, by sealing the two substrates at low temperatures, for example, at 363 to 400° C. using co-melting reaction between metal, for example, Au, and Si in a vacuum, the degree of vacuum in the device increases.

Abstract: A photodetector is integrated on a single semiconductor chip with bipolar transistors including a high speed poly-emitter vertical NPN transistor. The photodetector includes a silicon nitride layer serving as an anti-reflective film. The silicon nitride layer and oxide layers on opposite sides thereof insulate edges of a polysilicon emitter from the underlying transistor regions, minimizing the parasitic capacitance between the NPN transistor's emitter and achieving a high frequency response.

Abstract: A semiconductor device capable of a high-speed operation is provided. The semiconductor device is provided with low concentration impurity regions, a gate electrode formed with gate oxide film interposed between the gate electrode and a silicon substrate, an etching stopper, an interlayer insulating film having a contact hole and having an etching rate greater than that of the etching stopper, a high concentration impurity region formed by implanting an impurity into the silicon substrate through the contact hole, a plug layer filling the contact hole, and an interconnection layer.

Abstract: A method of processing dielectric layers in FeRAM and the structure of the like are provided. A FeRAM having a barrier layer, a first electrode, a second electrode, and a ferroelectric material is sandwiched between two layers of gradient dielectric layers. These gradient dielectric layers have changing refraction index from one side to the other side. As a result, these gradient dielectric layers prevent hydrogen from damaging the FeRAM structure. The change in refraction index is achieved by adjusting the ratio and deposition power of the SiH4 and N2O during plasma enhanced chemical vapor deposition of the gradient dielectric layers.

Abstract: A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. A single crystalline vertical transistor is formed along alternating sides of the pillar within a row of pillars. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions.

Abstract: A DC-to-DC switching power converter includes switching elements having capacitive gate control inputs, an energy storage element and driver circuitry. Improved efficiency is achieved using adiabatic buffers to drive MOSFET switching elements with stepped switching signals. Substantially equal rise and fall times are achieved. In one embodiment, the switching power converter is fabricated on a semiconductor die to generate an output voltage to one or more functional unit blocks on the die.

Abstract: A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.

Abstract: In the fabrication of semiconductor devices, and particularly, semiconductor memories, a gate oxide film and a gate electrode are formed on a semiconductor substrate, and a silicon oxide film is formed on the gate electrode. Thereafter, the entire surface is covered with a silicon nitride film and then with an interlayer oxide film. Bit line contacts are formed in source/drain regions each provided between adjacent gate electrodes according to a SAC technique utilizing the silicon nitride film. In the other source/drain region, a hole is made in the silicon nitride film to form a storage node contact.

Abstract: In a memory cell area (A) of a semiconductor storage device, a capacitor (8) formed on a first insulating layer (5) formed so as to cover MOS transistors (3, 4) includes a pillar-shaped insulating member (8a), a first capacitance electrode (8b) formed on the side surface of the pillar-shaped insulating member (8a), a capacitance insulating film (8c) formed on the first capacitance electrode (8b) and a second capacitance electrode (8d) formed on the capacitance insulating film (8c). A conductive member (7) for connecting the source or drain (3a) of the MOS transistor (3) to the first capacitance electrode (8b) is filled in a connection opening (6) formed in the first insulating layer (5).

Abstract: In a semiconductor device, formed are a lower capacitor electrode on an element isolation film on a silicon substrate, a capacitor insulating film and an upper capacitor electrode. A silicon oxide film is formed on the entire surface of the silicon substrate. On the silicon oxide substrate, formed is a resist pattern that covers a region extending from the inside of a periphery of the upper capacitor electrode to the outside of the periphery thereof. Sidewalls that cover side faces of a gate electrode and the lower capacitor electrode, and a sidewall that covers a side face and an upper periphery of the upper capacitor electrode, are formed by performing anisotropic etching.

Abstract: Within a method for fabricating a capacitor structure and a capacitor structure fabricated employing the method, there is provided a conductor barrier layer formed upon an upper capacitor plate formed within the capacitor structure. There is also provided a silicon layer formed upon the conductor barrier layer. The conductor barrier layer and the silicon layer provide for enhanced interdiffusion stability and enhanced delamination stability with respect to the upper capacitor plate, and thus enhanced reliability and performance of the capacitor structure.

Abstract: The present invention provides a cylindrically shaped stack electrode having a lamination structure which comprises a cylindrically shaped outer layer and a cylindrically shaped inner layer laminated on an inner wall of said cylindrically shaped outer layer, wherein hemispherical grains are formed on an inner wall of said cylindrically shaped inner layer. The cylindrically shaped stack electrode has the lamination structure of a plurality of layers.

Abstract: A process for fabricating trench capacitors in an interconnect layer of a semiconductor device is disclosed. In the process, at least one interconnect is formed in the interconnect layer, which is then planarized. To form the trench capacitor, a trench is formed in the dielectric material of the interconnect. The bottom of the trench communicates with a metal contact in the underlying layer. A barrier layer of material is formed on the interconnect layer and is anisotropically etched, leaving the barrier layer on the sidewalls of the trench. The lower plate of the capacitor is then formed by depositing a layer of metal over the interconnect layer. The layer of metal is then anisotropically etched, removing the metal on the surface of the interconnect layer and leaving the metal along the trench perimeter. The capacitor dielectric layer is then deposited over the interconnect layer and subsequently patterned. Another layer of barrier material is deposited on the interconnect layer.

Abstract: First and second impurity diffusion regions are disposed in partial surface layers of a semiconductor substrate and spaced apart by some distance. A gate electrode is formed above a channel region defined between the first and second impurity diffusion regions. A gate insulating film is disposed between the channel region and gate electrode. Of the gate insulating film, a portion thereof disposed at least in a partial area along the longitudinal direction of a path interconnecting the first and second impurity diffusion regions, having a lamination structure of a first insulating film, a charge trap film and a second insulating film sequentially stacked in this order. The charge trap film is made of insulating material easier to trap electrons than the first and second insulating films.

Abstract: A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned.

Abstract: A semiconductor body has source and drain regions (4 and 5) spaced apart by a body region (6) and both meeting a surface (3a) of the semiconductor body. A gate structure (7) is provided within a trench (8) for controlling a conduction channel in a conduction channel accommodation portion (60) of the body region (6) extending along at least side walls (8a) of the trench (8) and between the source and drain regions (4 and 5). A voltage-sustaining zone (600) consisting of first regions (6) of the same conductivity type as the source and drain regions interposed with second regions (62) of the opposite conductivity type is provided such that the first regions (61) provide a path for majority charge carriers to the drain region (5) when the device is conducting.

Abstract: The transistor has source and drain diffusion regions between which a gate electrode is disposed. In order to increase the sheet resistance of the source and/or drain diffusion regions, a plurality of strip-shaped insulating zones are provided, which penetrate through the corresponding diffusion region. The zones are oriented perpendicularly to the gate electrode and the end a given spacing distance from the gate electrode.