Abstract: To increase the withstand voltage and reduce ON-state resistance, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP layer (a P-type body region) formed so that the LP layer is adjacent to the gate electrode, an N-type source region and a channel region respectively formed in the LP layer, an N-type drain region formed in a position apart from the LP layer and an LN layer (a drift region) formed so that the LN layer surrounds the drain region is characterized in that the LP layer is formed up to the side of the drain region through an active region under the gate electrode and an SLN layer is formed from the drain region to a part before the active region.

Abstract: Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer. The power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.

Abstract: A radiation detector includes a top gate thin film transistor (TFT) including a source electrode, a drain electrode, a gate electrode, a TFT dielectric layer, a TFT semiconductive layer, and a TFT intrinsic amorphous silicon (a-Si) layer. The radiation detector also includes a capacitor including a first electrode, a second electrode substantially coplanar with the gate electrode, and a capacitor dielectric, the capacitor dielectric including a capacitor dielectric layer substantially coplanar with the TFT dielectric layer, a capacitor semiconductive layer substantially coplanar with the TFT semiconductive layer, and a capacitor a-Si layer substantially coplanar with the TFT a-Si layer.

Abstract: In a n+ snapback device, saturation current is limited by using one or more NLDD current blocking regions.

Abstract: An open drain driver circuit and a Vss to Vdd FET with a merged layout structure are formed to provide a short path for an ESD current from an associated pad and either Vss or Vdd. The short path reduces the IR drop in the path and thereby maintains a lower voltage at the pad during an ESD event. The driver and the Vss to Vdd FET are each formed of one or more cells that each comprise two source diffusions, two gates, and a common drain diffusion. A frame of the opposite conductivity type as the drain and source diffusions surrounds the components of each cell. The driver and Vss to Vdd FET cells are formed closely adjacent and share common parts of the frame. Several configurations with merged layout structures are disclosed that provide a short ESD current path.

Abstract: A semiconductor device protection circuit is composed of a first semiconductor portion of a first conductive type, a second semiconductor portion of a second conductive type connected to the first semiconductor portion, a third semiconductor portion of the first conductive type connect to the second semiconductor portion, and fourth and fifth semiconductor portions of the second conductive type, both connected to the second semiconductor portion. The first conductive portion is connected to a semiconductor circuit which is to be protected from electrostatic breakdown. The third, fourth, and fifth semiconductor portions are short-circuited. The fourth and fifth semiconductor portions are located at opposite sides of the third semiconductor portion.

Abstract: A Static Random Access Memory (SRAM) device includes at least a transfer transistor, a driving transistor and a load resistor which are commonly connected to a node. A well has a first conductive type, and is placed on a substrate. A first impurity region has a second conductive type opposite to the first conductive type, and is placed in the well. A second impurity region has the first conductive type and has higher impurity concentration than the well, and is placed at a lower portion of the first impurity region. The node is composed of at least the first impurity region and the second impurity region.

Abstract: A conductive line for programming a magnetoresistive memory device which includes a metal interconnect region positioned proximate to a magnetoresistive random access memory device, wherein the metal interconnect region supplies a current which produces a magnetic field and wherein the metal interconnect region includes a metal layer with a length and a width and has a first side, a second side, a third side, and a fourth side wherein a ferromagnetic cladding region with a thickness is positioned on the first side, the second side, the third side, and the fourth side of the metal layer, and wherein the ferromagnetic cladding region positioned on the first side has a trench having a length less than the length of the metal layer and a width approximately equal to the thickness of the ferromagnetic of the magnetic cladding region. The length of the trench can be changed to adjust the magnitude of the magnetic field.

Abstract: The leads of a light emitting device package are extended is flexible pins. These pins can be bent with respect to a motherboard so that the direction of the light entitled from the light emitting device can be adjusted. The package is tab-mounted to the motherboard for heat sinking or serving as a lead.

Abstract: A planar MESFET transistor includes a plurality of FET elements. Each FET element includes a doped planar channel, and source and drain coupled to the ends of the channel. A gate conductor extends over a portion of the channel at a location lying between the source and drain, a first predetermined distance from the drain. A field plate is connected to the gate conductor, and extends toward the drain a second predetermined distance, isolated from the channel except at its gate conductor connection by a dielectric material.

Abstract: A semiconductor memory device includes a semiconductor substrate; a plurality of word lines provided on the semiconductor substrate and arranged in parallel to each other; a plurality of memory cells provided along each of the plurality of word lines; a plurality of sub bit lines provided on the semiconductor substrate and arranged in parallel to each other, each of the plurality of word line intersecting the plurality of sub bit lines; a plurality of main bit lines arranged in parallel to the plurality of sub bit lines; a plurality of bank select lines arranged in parallel to the plurality of word lines; a plurality of bank select transistors provided along each of the plurality of bank select lines and connected to the respective sub bit lines; and a plurality of auxiliary conduction regions provided for each of the plurality of the main bit lines, connecting each of the plurality of the main bit lines to a set of the plurality of bank select transistors of the plurality of sub bit lines.

Abstract: An insulating wall of a second conductivity type intended for separating elementary components formed in different wells of a semiconductive layer of a first conductivity type, a component located in one at least one of the wells being capable of operating with a high current density. The insulating wall includes at least two elementary insulating walls separated by a portion of the wafer material and, in operation, this portion is connected to a reference potential.

Abstract: An antifuse structure has an antifuse between first and second thermal conduction regions. Each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity. The portion having low thermal conductivity is between the respective portion of high thermal conductivity and the antifuse.

Abstract: An exemplary embodiment of the invention is a semiconductor device comprising a substrate of a first conductivity type and a subcollector of a second conductivity type provided on the substrate. An intrinsic epitaxial layer is formed on the substrate. A collector region of the second conductivity type is adjacent the subcollector and a base region of the first conductivity type is adjacent the collector region. An emitter region of the second conductivity type is adjacent the base region and the emitter region has an emitter size. The subcollector and collector region both have a size not substantially greater than the emitter size. An alternate embodiment includes a spacer layer formed between the emitter region and the base region.

Abstract: An MOS heterostructure includes: a single crystal silicon substrate; an insulating film formed on the substrate; and a conductive film formed on the insulating film. The substrate includes a plurality of terraces and steps, which have been formed as a result of rearrangement of silicon atoms on the surface of the substrate. Each of the step is located in a boundary between an adjacent pair of the terraces. The insulating film contains crystalline silicon dioxide that has grown epitaxially over the steps.

Abstract: An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.

Abstract: A siloxan polymer insulation film has a dielectric constant of 3.1 or lower and has —SiR2O— repeating structural units with a C atom concentration of 20% or less. The siloxan polymer also has high thermal stability and high humidity-resistance. The siloxan polymer is formed by directly vaporizing a silicon-containing hydrocarbon compound of the formula Si&agr;O&agr;−1R2&agr;−&bgr;+2(OCnH2n+1)&bgr; wherein &agr; is an integer of 1-3, &bgr; is 2, n is an integer of 1-3, and R is C1-6 hydrocarbon attached to Si, and then introducing the vaporized compound with an oxidizing agent to the reaction chamber of the plasma CVD apparatus. The residence time of the source gas is lengthened by reducing the total flow of the reaction gas, in such a way as to form a siloxan polymer film having a micropore porous structure with low dielectric constant.

Abstract: A method and apparatus which provide one or more electromagnetic shield layers for integrated circuit chips containing electromagnetic circuit elements are disclosed. The shield layers may be in contact with the integrated circuit chip, including magnetic memory structures such as MRAMs, or in a flip-chip carrier, or both. A printed circuit board which supports the chip may also have one or more shield layers.

Abstract: Disclosed is a tape carrier package for electrically connecting LCD panel with source and gate driver PCBs and an LCD module to which the tape carrier package is applied.

Abstract: In a device for attaching a semiconductor chip (10) to a chip carrier (12), thereby producing an electrically conducting connection between contact areas (22, 24) arranged on a surface of the semiconductor chip (10) and contact areas (26, 28) on the chip carrier (12) by means of an anisotropically conducting film (16) or an anisotropically conducting paste (16), a pressure die (18) is used for the application of the pressure to the chip (10) with an adjustable pressing force against the chip carrier (12). A counter-pressure support (14) accepts the chip carrier (12) with the semiconductor chip (10) arranged on it with the interposition of the anisotropically conducting film (16) or the anisotropically conducting paste (16). An elastic body (20) is arranged either between the pressure die (14) and the semiconductor chip (10) or between the chip carrier (12) and the counter-pressure support (14).

Abstract: A COF-use tape carrier for a semiconductor device has dummy leads not to be electrically connected to a semiconductor chip, in the proximity of an edge of an opening of a solder resist. The dummy leads are provided on an insulating tape, between adjacent two inner leads that are relatively widely spaced from each other. The dummy leads extend across the edge of the opening of the solder resist, so that one end of each dummy lead is located within the opening of the solder resist, while the other end of the dummy lead is located under the solder resist. A semiconductor chip is to be mounted on a chip-mounting region of the insulating tape.

Abstract: A semiconductor package having heat sink at the outer surface is constructed on a lead frame. The package comprises a chip, a die pad, a plurality of leads, a plurality of bonding wires, and a molding compound. The die pad has a first surface and a second surface, and the chip has its active surface bonded to the first surface of the die pad. The area of the die pad is smaller than the area of the chip in order to expose the bonding pads on the active surface of the chip. The leads having an inner lead portions and an outer lead portions are disposed at the periphery of the die pad, and the inner lead portions are electrically connected to the bonding pads by a plurality of bonding wires. The molding compound encapsulates the chip, the die pad, the inner lead portions of the leads, and the bonding wires. The second surface of the die pad is exposed on the top surface of the package structure while the outer lead portion of the leads is exposed at the side edge of the package structure.

Abstract: A structure of a stacked-type multi-chip stack package of the leadframe, the shape of the stair-like inner leads can be regulated for the high and the amount of stacked chips and to match different bonding technology. The process for forming the present structure can be easily performed by visible equipment and materials, and the present structure can raise the reliability of bonding process. The present invention can stack multi-chip (more than two).

Abstract: A method of forming non-spherically shaped solder interconnects, preferably conical, for attachment of electronic components in an electronic module. Preferably, the solder interconnects of the present invention are cone shaped and comprise of depositing a first solder followed by a second solder having a lower reflow temperature than the first solder. Warm placement of the electronic component at a somewhat elevated temperature than room temperature but less than the solder reflow temperature reduces the force required during placement of a semiconductor chip to a substrate. After warm placement, reflow of the module occurs at the lower reflow temperature of the second solder. The conical shape of the solder interconnects are formed by a heated coining die which may also coin a portion of the interconnects with flat surfaces for stand-offs.

Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.

Abstract: A force-fit diode for high circuit application has a cylindrical constant diameter conductive body which has a tapered top and bottom peripheral edge. An axial conductor extends from one end of the housing. The tapered top and bottom peripheral edges allow the housing to be forced into an opening in the bus, with either the housing bottom or the axial lead being the first to enter the openings.

Abstract: A method of integrating MEMS devices with non-MEMS circuitry requires fabricating non-MEMS devices on a substrate in a conventional fashion. A thick dielectric layer is deposited on the completed devices, and the MEMS devices fabricated on the dielectric layer. Vias through the dielectric layer interconnect the MEMS devices to the non-MEMS electronics. The interposed dielectric layer allows the common substrate to have characteristics that best suit the non-MEMS components, without degrading the MEMS performance. Another approach involves bonding together two separate wafers—one for the MEMS devices and one for non-MEMS electronics. A package lid, having filled vias formed therethrough, is bonded to the MEMS wafer, sealing the MEMS devices within. The non-MEMS wafer is mounted to the lid, with the vias effecting the necessary interconnections between the two wafers.

Abstract: An integrated circuit device includes first and second arrays of semiconductor dice. Each array of dice is arranged in face-to-face relation to the other array of dice, thus forming a lower layer of dice and an upper layer of dice. The layers are aligned so that each upper layer die straddles two or more of the lower layer dice, thus defining overlap regions. In the overlap regions, signal pads of one layer are aligned with corresponding signal pads of the other layer. The two layers are spaced apart, thus creating a capacitance-based communication path between the upper and lower layers via the signal paths.

Abstract: Nine bidirectionally blocking power components are attached on a substrate in the form of a three-row matrix. The power components are attached between three respective current conductors arranged parallel to each other above and below the power components. The current conductors above the matrix proceed at a right angle relative to the current conductors under the matrix. The interconnects to the gate and auxiliary emitter terminals are situated on or in a thin insulating printed circuit board or film and are secured to the corresponding contacts of the chips in recesses of the current conductors.

Abstract: The high-frequency package according to the present invention has a base plate made of copper; a ceramic frame having a space for accommodating a circuit device and mounted on the base plate; and a pattern of circuits developed on the ceramic frame. The base plate and the ceramic frame, and the ceramic frame and the patterned circuits, are both joined together by a DBC technique. According to the present invention, the high-frequency package can be fabricated by a simpler procedure.

Abstract: A thermal capacitor component which includes, on a substrate, a stack of different layers defined in the form of a mesa terminating at its upper part in an electrical contact layer, which layer is coated with an electrically and thermally conducting layer surmounted by a heat sink element in contact with the conducting layer. The heat sink element has a plane shape. In addition, the component has at least one pad including another stack of layers which is also coated with an electrically and thermally conducting layer. The heat sink element is also in contact with the conducting layer of this stack so as to conduct the heat from the heat sink element into the substrate. Such a thermal capacitor may find application in the cooling of semiconductor components.

Abstract: A sealing package for an integrated circuit chip including a lead structure with first lead members and second lead members. The first lead members are located proximate the corners of the sealing package and have two lead portions external to the sealing package and one lead portion internal to the sealing package. The second lead members are fanned out along the sides of the sealing package and have one lead portion internal to the sealing package and one lead portion external to the sealing package. Each first lead member adapted to provide a connection to ground for at least two sides of the sealing package. Each second lead member adapted to provide a connection between an integrated circuit chip internal to the sealing package and external circuitry.

Abstract: A semiconductor device includes a semiconductor chip, a substrate electrically connected to the semiconductor chip and heat spreading plate thermally connected to the semiconductor chip. The substrate is provided with external connection terminals on a first surface and electrically connects the semiconductor chip and the external connection terminals. The substrate is provided with joining , parts made of metal on a second surface. The heat spreading plate and the substrate are joined together by welding the joining parts and the heat spreading plate.

Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.

Abstract: An integrated circuit device having a built-in thermoelectric cooling mechanism is disclosed. The integrated circuit device includes a package and a substrate. Contained within the package, the substrate has a front side and a back side. Electric circuits are fabricated on the front side of the substrate, and multiple thermoelectric cooling devices are fabricated on the back side of the same substrate. The thermoelectric cooling devices are utilized to dissipate heat generated by the electric circuits to the package.

Abstract: A stacked package structure of an image sensor used for electrically connecting to a printed circuit board includes a substrate, an image sensing chip, an integrated circuit, and a transparent layer. The substrate has a first surface and a second surface. The first surface is formed with signal input terminals. The second surface is formed with signal input terminals and signal output terminals for electrically connecting to the printed circuit board. The image sensing chip is mounted on the first surface of the substrate and is electrically to the signal input terminals of the substrate. The integrated circuit is arranged on the second surface of the substrate and is electrically connected to the signal input terminals of the substrate. The transparent layer covers over the image sensing chip, which can receive the image signals via the transparent layer and convert the image signals into electrical signals that are to be transmitted to the substrate.

Abstract: The present invention provides a semiconductor device comprising: a semiconductor substrate; at least a pad electrode provided over the semiconductor substrate; a passivation film provided over the semiconductor substrate; an insulative resin stress buffer layer provided over the at least pad electrode and the passivation film, the insulative resin stress buffer layer having at least an opening positioned over at least a part of the at least pad electrode; and at least a land portion provided over the insulative resin stress buffer layer and also electrically connected to the at least pad electrode, and a top surface of the at least land portion being electrically connected to at least a bump which is positioned over the at least land portion, wherein the at least land portion and the passivation film are isolated from each other by the insulative resin stress buffer layer.

Abstract: A connection structure is configured such that electrodes formed on an overcoat layer on a substrate are connected to other electrode terminals using an anisotropically electroconductive adhesive 30 comprising electroconductive particles dispersed in an insulating adhesive, wherein the angle of encroachment A of the electroconductive particles 32 into the overcoat layer 4 is made to be at least 135°.

Abstract: Sides of via hole do not bow horizontally, thereby preventing an increase of a resistance of a wiring layer connected to a conductor in the via hole. A semiconductor device comprises a first wiring layer, an insulating layer over the first wiring, a second wiring on the insulating layer, a first hole formed in the first wiring, a second hole formed in the insulating layer connecting with at least a part of the first hole, and a conductive material in first and second holes that electrically connects the first wiring layer to the second wiring layer.

Abstract: Disclosed is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. The joined fill shapes serve to reinforce and support the dielectric, which may be a non-rigid or low-k dielectric.

Abstract: A structure for selectively programming interconnections between an input contact and an output contact segment in a multilayer semiconductor, comprising a first group of metal segments each being formed on successive layers of the semiconductor and being interconnected by vias, the first group including the output contact segment; a second group of metal segments each formed on successive layers of the semiconductor and being interconnected by vias, the second group including the input contact segment; and means for connecting a metal segment in the first group to a metal segment in a corresponding layer in the second group, thereby connecting the input contact to the output contact.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps.

Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material.

Abstract: The semiconductor structure has a layer structure formed from a metalization layer and a dielectric layer. The metalization layer is patterned and has contact areas. The dielectric layer is composed of a depositable material and covers the metalization layer. The contact areas are formed from many contiguous individual structures, which are so narrow that the depositable material does not form, over the individual structures, any areas which run parallel to the metalization layer. The grid of contiguous individual structures forms a contact area which causes dielectric layer elevations which are particularly low and therefore easy to planarize.

Abstract: A wiring layer is covered with a first organic SOG layer, a reinforcement insulating layer consisting of a silicon oxide film or a silicon nitride film formed by means of a plasma CVD method, and a second organic SOG layer, in this order. A via hole is formed in the first organic SOG layer and the reinforcement insulating layer, and a trench is formed in the second organic SOG layer to correspond to the via hole. A conductive via plug and an electrode pad are embedded in the via hole and the trench, respectively. The second SOG layer is covered with a passivation layer in which a through hole is formed to expose the electrode pad. A wire is connected to the exposed electrode pad in the through hole.

Abstract: A tape carrier package with a widow that is capable of confirming an alignment extent between the tape carrier package and a print wiring board in bonding the tape carrier package mounted with an integrated circuit on the liquid crystal panel and the print wiring board. In the package, the integrated circuit is mounted onto a base film. Input pads are connected to the integrated circuit and formed on the base film. Dummy pads are formed at the left and right side thereof not to be connected to the integrated circuit. Windows are provided by opening the base film adjacent to the dummy pads to expose at least two of said dummy pads.

Abstract: A system and method for supplying electricity for use with a host device. The system includes a structure and an interface. The structure includes an array of single-walled carbon nanotubes arranged with respect to a matrix. In operation, the system receives a force stimulus for facilitating piezoelectric generation of electricity. In particular, the array receives the force and piezoelectrically generates electricity therefrom. The array is electrically coupled with the interface. The interface allows the structure to supply electricity to electrical devices that are coupled to the interface.

Abstract: A starter device, preferably for cold-starting, for fuel cell systems, including a current generation system, for generating electrical energy, and a gas generation system, for generating H2-rich gas for the current generation system. An internal-combustion engine generates mechanical energy, which can be connected to an air compressor for supplying air to the gas generation system via a drive shaft.

Abstract: The rain, wind, wave, and solar energy 4-in-1 electric generating installation comprises mainly a wind wheel (2), a water wheel (3) two solar plates (1 and 1A), a wind and current plate (4), a turntable (6), and four floats (14). All these components work in combination to convert 4 natural resources, namely rain, wind, waves, and sunlight into useful electricity with automatic adjustment to the level of tide, and direction of wind and current. The installation can be used either in water or, with some minor modifications, on land. By means of this installation, even without 1, 2, or 3 of the 4 natural resources, generation of electricity will not be suspended. The invention, therefore, has great advantages over the conventional electric generators.

Abstract: A small-sized hydroelectric power generating apparatus includes a body case having a fluid passage, a water wheel provided at the above fluid passage and rotating with passing of the fluid having the predetermined flowing amount, a rotator coupled to this water wheel, and rotating with the water wheel, the rotator serving as a rotor portion arranged opposed to a stator portion, the rotor portion being relatively rotated in relation to the stator portion by passing the fluid to generate electric power, the stator portion having comb-shaped pole teeth which are arranged in the circumferential direction at regular intervals so as to be opposed to the peripheral surface of a rotor magnet of the above rotor portion, and a circumferential gap between the adjacent pole teeth is set to 1.5 times or less the size of a radial gap between each pole tooth and the rotor magnet.