Abstract: A method and system for determining an inductance value of an inductive element are presented. The method includes energizing the inductive element using an N-pulse AC to DC converter in electrical communication with the inductive element and an AC source. The method further includes determining at each of a plurality of periodic time intervals an inductive element voltage value, an inductive element current value, and an equivalent source phase angle. An Nth harmonic impedance squared value is then determined for the inductive element using the inductive element voltage and current values and the equivalent source phase angles. The inductive element inductance value is then calculated using the Nth harmonic impedance squared value and an AC source frequency value.

Abstract: A system for analyzing agricultural products on harvesting equipment includes a test chamber and a near infrared spectrometer disposed within a housing capable of being mounted on the harvesting equipment. A source of near infrared radiation is disposed in the housing adjacent the test chamber so as to emit near infrared radiation into the test chamber, and a near infrared detector is disposed in the housing adjacent the test chamber so as to receive near infrared radiation exiting the test chamber. The spectrometer is mounted on vibration damping elements. A computer controls operation of first and second doors for controlling ingress and egress of product samples from the test chamber and can also be used to process signals from the spectrometer.

Abstract: Measurement of the permittivity of thin films is facilitated through the use of a short cylindrical metal cavity containing parallel plates between which a specimen to be measured is placed. The use of such parallel plates contained within such a cavity is particularly advantageous when swept frequency measurement methods utilizing frequency ranges from 0 to 20 GHz are employed. A test fixture which is preferred for use in providing such a cavity is disclosed as are methods of using the test fixture.

Abstract: A method and apparatus for processing a time domain reflectometry (TDR) signal having a plurality of reflection pulses to generate a valid output result corresponding to a process variable for a material in a vessel. The method includes the steps of determining a reference signal along a probe in the vessel, establishing a first fiducial reference point, a reference end of probe location, a measuring length and a maximum probe length. The method also includes the steps of periodically detecting a TDR signal along the probe, establishing a second fiducial reference point, a detected end of probe location, an end of probe peak to peak amplitude, and attempting to determine a process variable reflection on the TDR signal. The method indicates a broken cable condition, a loss of high frequency connection, a low amplitude reflection condition, an empty vessel condition.

Abstract: An electromagnetic field presence sensor independently evaluates the presence or absence of an object in a variety of frequency ranges. Conflicting indications of the presence of the object in these different ranges, such as may be caused by electromagnetic interference, is resolved through a voting system. In this way, band limited noise may be resisted while improving the sensitivity of the sensor and without reducing its response speed.

Abstract: A soil moisture sensing device for sensing moisture levels in a particular soil area. The device has a porous body with at least two zones, a first one of the zones having pore sizes that approximate a range of pores in typical soils, a second one of the zones having pores arranged to be small enough to remain hydrated at higher matric tensions. The first and second zones contain respective electrodes, each being paired with an electrode common to both zones. As the matric tension of the soil solution increases, the pores within the first zone dehydrate causing increased resistance between the first electrode and the common electrode while the pores in the second zone remain hydrated, the resistance between the second electrode and the common electrode changing only in response to conductivity of the soil solution in the second zone.

Abstract: A monitoring circuit is provided to determine the proper operating condition of a cathodic protection circuit including a plurality of diodes and a capacitor. The monitoring circuit determines whether or not any of the diodes are shorted or open and whether or not the capacitor is open or operating properly. In addition, it determines whether or not the cathodic protection circuit is properly connected between a boat ground point and a shore ground point.

Abstract: A circuit arrangement is described for compensating temperature non-linearity of the characteristics of piezoresistive, metallic or polycrystalline resistors (bridge resistors) connected in a bridge circuit, the non-linearities being caused by non-linearities of the resistors, in particular due to the physical quantities affecting the bridge circuit (temperature, pressure, bimetal effects, non-linear membrane stresses), and the resistors being composed of partial resistors having different temperature coefficients, with each of the partial resistors having a certain linear and non-linear temperature response. The partial resistors of each bridge resistor are selected on the basis of their known linear and non-linear temperature characteristics so that an asymmetric layout of the bridge circuit is obtained and a non-linear variation of a bridge output voltage of the circuit arrangement can be essentially compensated.

Abstract: A plurality of measuring positions on a sample are sequentially irradiated with electron beams having identical cross sectional shapes, currents produced in the sample when the individual measuring positions are irradiated with electron beams are measured and the measured currents or physical amounts derived from the measured currents are displayed on a two-dimensional plane as a function of measuring position.

Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with: the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.

Abstract: An enhanced probe plate assembly for a circuit board test fixture is disclosed. A conductive surface or surfaces is laminated to the underside of a probe plate assembly located between an electrical test system and circuit board under test. These conductive surface(s) of the probe plate assembly provide an improved interface between the signal probes and personality pins of the circuit board test fixture and can be used for grounding planes, voltage sources, and common interconnection grids. The enhanced probe plate assembly results in increased signal quality due to reduced signal path length, less crosstalk and signal loss between personality pin and signal probe connections, and perfect alignment of personality pins and signal probes through the conductive surface. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: A test socket for an IC device has relatively thin contact interface wall in which an having an array of double-ended pogo pins. The double-ended pogo pins provide resilient spring-loaded contacts for the I/O contacts of an IC device held in the socket as well as for the circuit contacts of a PC board to which the socket is mounted.

Abstract: A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium.

Abstract: A thermal test chip array and method of forming the same allows access to any test die in the array regardless of the size of the array. The thermal test chip arrangement has a plurality of thermal test chips arranged in an array, each thermal test chip having a heating circuit and a temperature-sensing circuit. A first set of conductive lines traverse unbroken across the entire array. The heating circuit of each thermal test chip is connected to some of the first set of conductive lines. These conductive lines provide power to the heating circuits of the thermal test chips. A second set of conductive lines traverse unbroken across the entire array with the temperature-sensing circuit of each thermal test chip being connected to some of the second set of conductive lines. Power is carried to the temperature sensing circuits of the thermal test chips by the second set of conductive lines.

Abstract: A low-current pogo probe card for measuring currents down to the femtoamp region includes a laminate board having a layer of conductive traces interposed between two dielectric layers. A plurality of probing devices, such as ceramic blades, are edge-mounted about a central opening so that the probing needles or needles included therein terminate below the opening in a pattern suitable for probing a test subject workpiece. A plurality of pogo pin receiving pad sets, each including a guard pad, occupy the periphery of the board. Each guard pad is electrically connected to a trace from the layer of conductive traces. The pad sets may be connected to the probing devices by low noise cables or traces. Air trenches separate the pad sets for reducing cross talk and signal settling times.

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Abstract: A process is herein described for analyzing an integrated circuit chip for defects by observing changes in the appearance of a liquid crystal applied to the backside of the integrated circuit. The process includes spreading a thin film of a liquid crystal material on the backside of the integrated circuit. Using an optical microscope, the liquid crystal film is optically inspected as the chip is biased.

Abstract: A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.

Abstract: The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (&dgr;) which minimizes the standard deviation of the function F to be obtained (step ST1.

Abstract: Multiple devices can be tested simultaneously for power continuity or for other power performance characteristic(s). If any of the devices have short circuit defects, for example, the fuse devices connected between these defective devices and a single power supply restrict the amount of current drawn by the defective devices. This allows power continuity testing to continue for all of the other devices. At the same time, the reduced voltage level of the defective devices, caused by the restriction of current by their corresponding fuse device, can be detected by the voltage measurement device. The reduced voltage levels allow the defective devices to be identified by a test control apparatus and to be excluded from subsequent testing.

Abstract: There can be provided a variable function information processor in which a logic module (10) with the further decreased number of transistors used in the logic module constituting the variable function information processor is provided, a function of being able to realize both a combinational logic circuit for-performing a full addition operation of input signals in accordance with a control signal and outputting the sum and a sequential circuit for temporarily holding the input signal to delay the signal and outputting it by the same logic module is provided, and in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits, whereby the number of elements can be further decreased, and the resources of the variable function information processor can be effectively exploited.

Abstract: Disclosed is a data processing system comprising a control unit for receiving data from a main core and outputting given control signals, a level shifter for amplifying the electric potential of said given control signals and outputting corresponding driving signals, a data output buffer for receiving said driving signals from said level shifter and outputting a driving voltage having a voltage range defined in the PCI or/and PCI-X specifications, to an input/output pad, and said data output buffer being in a high impedance state to prevent a PCI mode voltage inputted to said pad from being leaked to a power source terminal when said data processing system is operated in PCI mode.

Abstract: An output buffer circuit includes first and second MOS transistors connected in series between a power supply and ground, a first pull up transistor coupled between the power supply and a gate of the first MOS transistor, a first pull down transistor coupled between ground and the gate of the first MOS transistor, a second pull up transistor coupled between the power supply and the gate of the second MOS transistor, a second pull down transistor coupled between ground and the gate of the second MOS transistor, a slew-rate control node, a third MOS transistor coupled between the power supply and the slew-rate control node, a fourth MOS transistor coupled between ground and the slew-rate control node, a first variable resistance provided between the first pull up and pull down transistors, and a second variable resistance provided between the second pull up and pull down transistors.

Abstract: A driving circuit includes a driving signal generating circuit which generates a plurality of driving signals; a plurality of switching circuits which are supplied with the driving signals so as to supply driving voltages in response to the driving signals, respectively; an output node which is connected to each of the switching circuits and is supplied with one of the driving voltages selectively; and a control circuit which controls the switching circuits so that any two of the switching circuits are not turned on simultaneously.

Abstract: A node predisposition circuit for driving an output node of an output buffer circuit is provided which is formed of a delay circuit, a pre-charge pull-up circuit, and a pre-charge pull-down circuit. The pre-charge pull-up and pull-down circuits are used for pre-charging the output node to approximately one-half of the power supply voltage with a single phase system. The predisposition circuit has significantly reduced supply bounce and ground bounce, but yet maintains a high speed of operation with minimal static current.

Abstract: In a glitch free clock multiplexer circuit and a method thereof, the glitch free clock multiplexer circuit includes a delay unit for receiving asynchronous clock signals (Clock A, Clock B) and an external selection signal (Sel) and outputting a delay signal by delaying a clock signal selected by the external selection signal (Sel) for a certain clock cycle, a state region transition generating unit for comparing the delay signal with a count value provided from a user, outputting a first control signal (Sel_clock) according to a comparison value and a second control signal (enable) for controlling the first control signal in a logic low state, and a glitch removal unit for outputting a clock output signal (Clock_out) by performing an AND operation of a temporary clock signal (Temp_clock) selected by the first control signal and a third control signal generated by delaying the second control signal (enable) for a certain clock cycle.

Abstract: A domino circuit may be provided with additional keeper transistors that are selectively activated when one of the input transistors in a logic structure has a low or inactive signal applied to it during the evaluation stage. Thus, the potential of the output node of the domino circuit may be maintained, improving the soft error rate.

Abstract: A method and apparatus for operating logic circuitry with recycled energy. Logic circuitry is used which has a node for storing energy and a return node that is connected to energy storage circuitry. The logic circuitry operates, using energy stored on the node, to determine a logic output based on a logic input during a first phase. The energy storage circuitry capture a portion of the stored energy during the operation of the logic circuitry and transfers a portion of the captured energy back to the node during a second phase. In one embodiment, the logic circuitry and the energy storage circuitry form a resonant circuit and the logic circuitry operates synchronously to a clock. In another embodiment, the energy storage circuitry includes a resonant circuit configured to oscillate with a determinable period. The resonant circuit is tunable so that its oscillations can be synchronized to a clock.

Abstract: A loss of signal detection circuit using Gilbert mixers. A differential input signal is provided to an input Gilbert mixer. Reference signals are provided to a reference Gilbert mixer. The two Gilbert mixers pull reference lines in opposing directions such that a one line is higher than another line when the differential input signal provides valid data.

Abstract: A bi-directional high-voltage RESURF EDMOS (REduced SURface Extended Drain MOS) transistor which can endure a high voltage at its source by providing drift regions at both sides, i.e., the source and drain of the conventional RESURF LDMOS (Lateral DMOS) transistor, and exchanging the drain and the source when an analog signal of high voltage is inputted. Further, the bi-directional high-voltage RESURF EDMOS transistor provides a high-voltage analog multiplexer circuit employing a RESURF EDMOS transistor which is capable of reducing the number of necessary high-voltage elements and performing a stable operation, by constructing a high-voltage analog multiplexer having at least three inputs and a multistage high-voltage multiplexer circuit of push-pull type, pass transistor type, and combined form of push-pull type and pass transistor type by using the bi-directional high-voltage, RESURF EDMOS transistor.

Abstract: A system and method for current sensing which is substantially consistent over device, temperature, and process variations is provided. A current sensing system includes a first switch coupled to one or more variable resistive elements. The resistive elements being configured to scale down the voltage across the first switch which is provided to an input of an amplifier. The amplifier is coupled to the resistive elements and the second switch and is configured to sense the voltage across the first switch, and force the voltage across the second switch to be equal to the first switch scaled down voltage. Thus, a current of known proportion can be provided at the output of the amplifier. A driver and timing circuit may be provided to prevent the amplifier from providing an excessive slewing of current during the off period.

Abstract: Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay.

Abstract: A circuit configured to (i) receive a differential signal pair and (ii) generate one or more common mode signals. The circuit generally provides a large impedance on each input line.

Abstract: A full rail-to-rail CMOS comparator is provided. The comparator includes a gain stage and a bias stage. The bias stage is responsive to the common mode input voltage level to provide a bias signal that maintains the gain stage with an optimum operating range regardless of the level of the common mode input voltage, thus maintaining the comparator output responsive to the differential input voltage. Accordingly, when operating in the optimum operating range, duty cycle distortion of the signal at the comparator output is minimized. The comparator also offers improved performance due to a lower component count and fewer comparator stages, thus decreasing power consumption and improving propagation delays.

Abstract: A voltage comparing circuit of the invention includes a first and a second capacitor terminals on one side of which are respectively connected to a positive side voltage of an analog input signal and a negative side voltage of a reference voltage via a first and a second switch and terminals on other side of which are commonly connected, a third and a fourth capacitor terminals on one side of which are respectively connected to a positive side voltage of the reference voltage and a negative side voltage of the analog input signal via a third and a fourth switch and terminals on other side of which are commonly connected, a first and a second inverter respectively connected to a common connection terminal of the first and the second capacitors and a common connection terminal of the third and the fourth capacitors and connected with a fifth and a sixth switch respectively between input and output terminals thereof, a seventh and an eighth switch respectively connected between the input terminal of the first in

Abstract: A circuit for providing a control voltage to a switch includes a capacitor, a first pair of switches for coupling the capacitor to an input voltage source and a second pair of switches for coupling the capacitor to the switch. The first pair of switches is controlled by a control signal in response to the voltage across the capacitor in order to prevent overcharging the capacitor beyond a first predetermined level. The second pair of switches is controlled by a second control signal in response to the voltage across the switch in order to replenish the capacitor voltage when the capacitor voltage falls to a second predetermined level. The first and second pairs of switches are closed during non-overlapping time intervals in order to isolate the switch from the input voltage source, thereby preventing switching transients from affecting the input voltage source and permitting the circuit to be used to drive a variety of switch types arranged in a variety of configurations.

Abstract: An integrated circuit device is discussed that includes an data output driver having two modes of operation for driving a data bus. The output driver includes a circuits to produce a full drive output high signal, a partial drive output high signal, a full drive output low signal and a partial drive output low signal. The output driver is protected against negative voltages on the data bus. The output driver is selectable and adaptable to drive terminated loads and unterminated loads.

Abstract: An Nch-Tr having a gate connected to an input terminal and an Nch-Tr having a gate connected to an output signal voltage supply terminal through a Pch-Tr are connected to an output terminal for outputting an output signal carrying a second voltage level. In changing the output signal from a high level to a low level in accordance with a change of an input signal carrying a first voltage level, both the Nch-Trs are initially turned ON to lower the voltage of the output signal, and then the Nch-Tr having its gate connected to the output signal voltage supply terminal through the Pch-Tr is brought into a high ON state (a state of higher driving power) to turn the voltage of the output signal to the low level, so that the output signal can be changed quickly by a simple circuit configuration.

Abstract: A multi-path unity gain buffer circuit and method are implemented in a slew amplifier. The multi-path unity buffer has a high frequency signal path and a low frequency signal path. The high frequency signal path has a differential amplifier powered for providing a high frequency, low accuracy buffering operation. The low frequency signal path is coupled to the high frequency signal path. The low frequency signal path has an operational amplifier powered to provide a low frequency, high bandwidth buffering operation. An output of the operational amplifier is fed back to an input of the operational amplifier through a current varying element that varies current levels of the input of the operational amplifier to remove a level shift of an output signal of the differential amplifier.

Abstract: Techniques designing an electronic circuit system including multiple transistors and passive components are presented. According to one aspect of the techniques, some or all of the transistors and passive components are systematically adjusted to minimize artifacts resulting from system-level interactions among these functional building blocks. The adjustment is based on a ratio of Electrically Equivalent Channel Geometry (EECG) of each of the adjusted the transistors and passive components.

Abstract: Object of the present invention is to provide a timing signal occurrence circuit capable of precisely adjusting timing, without complicating a circuit. A timing signal occurrence circuit according to the present invention has a tristate buffer connected to a delay clock line, a tristate buffer connected to an operand bus, a calculator connected to an input terminal of each of the tristate buffers, a pulse generating circuit for generating an one shot pulse based on a delay clock on the delay clock line, and a calculator for fetching operands on the operand bus and carrying out calculation using the fetched operands. Either of a plurality of tristate buffers is arbitrarily selected to adjust delay time of the delay clock. Because of this, it is possible to generate a one shot pulse with optimum timing for carrying out calculation by the calculator.

Abstract: It is an object of the present invention to provide a semiconductor circuit apparatus that allows an increase in circuit size associated with an increase in number of holders. A counter circuit (102) is used as means for selecting a certain data from data held in a holder. Output data of the counter circuit (102) is compared with data held in the holder by a comparator circuit (103) and data selected according to the result of the comparison is held. This allows a decoder circuit and selector circuit as comparator means to be replaced with the comparator circuit (103) and the holder (106), thereby reducing circuit size.

Abstract: To synchronize a controllable oscillator with a first reference clock signal, a first phase locked loop having a first phase comparison device is provided. In addition, the synchronous-frequency clock signal from the oscillator is supplied to a second phase comparison device for phase comparison with a second reference clock signal via an inventive phase control element for inserting and removing clock phases. On the basis of the output signal from the second phase comparison device, phase correction information is formed and on the basis of this phase correction information the insertion and removal of clock phases is controlled in the phase control element. If the first reference clock signal disappears, the oscillator is stabilized using the second reference clock signal by taking into account the phase correction information formed previously.

Abstract: A multiplied clock generating circuit for generating and outputting an output clock signal that has a higher frequency than an input clock by a factor M is described.

Abstract: To restrain cycle-to-cycle jitter in a clock generator subjected to EMI a 2nd order PLL having a loop filter including a first capacitor and a first resistor, is provided where a reduction in a comparison frequency is avoided by using a clock modulating circuit. The clock modulation circuit is controlled by an intermediary signal provided by dividing an oscillation signal of a voltage controlled oscillator. The output of the clock modulation circuit is used to recurrently control a divider for dividing the output of the voltage controlled oscillator. Generation of high frequency noise is minimized by using a 1st order &Dgr;&Sgr; modulator(21) in the clock modulation circuit. The system behaves like a 3rd order PLL due to the presence of a second capacitor having a capacitance value of about {fraction (1/10)} or more than that of the first capacitor. The second capacitor is placed in parallel with the loop filter to restrain the cycle-to-cycle jitter by effectively removing the high frequency noise.

Abstract: A delay line comprised of analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

Abstract: A semiconductor integrated circuit includes a plurality of logical elements connected in series or parallel, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate; and a buffer circuit connected between a logical element group including at least two of the plurality of logical elements and another logical element group including at least two of the plurality of logical elements.

Abstract: A method of reducing power rail transients on integrated circuits. The power rail transients are reduced by controlling clock skew in a manner which minimizes dI/dT current demands. The method provides that the phase of the clock to latches/flip flops is shifted in order to spread out the number of simultaneous switching elements. By controlling the number of simultaneous switching devices, a significant reduction in time rate of current demanded from the power rails can be achieved, thereby reducing the magnitude of VSS/VDD voltage transients due to parasitic inductances and resistances supplying power to the integrated circuit. Theoretically, the entire timing spread of the slack graph for clock skew can be used to control the number of simultaneous switching devices.

Abstract: A method as well as a bias generator and associated output circuit architecture (300) that protects output skew voltage capabilities for the associated output circuit (304) to a greater extent than that achievable using presently known circuit architectures and techniques. A voltage level detector (306) comprising a differential-pair circuit detects bias voltage levels and provides a signal (308) to skew adjusting assist devices (310, 312) when the bias voltage levels get close to a “choking off” voltage level. The signal (308) turns on the skew adjusting assist devices (310, 312) to assist the skew adjusting devices (102, 104).

Abstract: A bus switch is protected from undershoots on either of its terminals. The bus switch transistor is an n-channel metal-oxide-semiconductor (MOS) with its source connected to a first bus and its drain connected to a second bus. During isolation, the gate node of the bus switch transistor is discharged to ground by a pulsed transistor, and then kept at ground by a leaker transistor. Sense-pulse circuits are attached to the first and second bus. When a low-going transition is detected by a sense-pulse circuit, an n-channel connecting transistor is turned on, connecting the bus with the low-going transition to the gate node through a grounded-gate n-channel transistor. If an undershoot occurs, it is coupled to the gate node. Since both the gate and source of the bus switch transistor are coupled to the undershoot, the gate-to-source voltage never reaches the transistor threshold and the bus switch transistor remains off.