Abstract: A semiconductor device comprises a channel of a first conductive type formed on a surface layer of a semiconductor substrate, source and a drain of a second conductive type formed on both sides of the channel, a gate insulation film with a first relative permittivity formed at least on the channel directly or through a buffer insulation film, a gate electrode formed on the gate insulation film, and a side insulation film formed at least on a side of the gate insulation film and having a second relative permittivity which is smaller than the first relative permittivity, and, when assuming that an area of the gate insulation film, which is adjacent to the surface layer on a gate electrode side, is S1, and an area thereof, which is adjacent to the surface layer on the channel side, is S2, the area S1 is larger than the area S2.

Abstract: An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process instead of two, as conventionally required. In one embodiment, each capacitor of a capacitor pair is provided with at least one plug contacting a common diffusion region of two adjacent cell transistors. In another embodiment, a large plug with sufficient overlap to the bottom electrodes of pair of capacitors is used.

Abstract: A magnetic random access memory module includes a magnetic memory array. A permeable metal layer extends over a first side of the magnetic memory array. An electrically insulating layer is disposed between the permeable metal layer and the magnetic memory array.

Abstract: In an array of integrated transistor/memory structures the array includes one or more layers of semiconducting material, two or more electrode layers, and memory material contacting electrodes in the latter. At least one layer of a semiconducting material and two electrode layers form transistor structures such that the electrodes of the first electrode layer forms source/drain electrode pairs and those of a second electrode layer form the gate electrodes thereof. The source and drain electrodes of a single transistor/memory structure are separated by a narrow recess extending down to the semiconducting layer wherein the transistor channel is provided beneath the recess and with extremely small width, while the source and drain regions are provided beneath the respective source and drain electrodes on either side of the transistor channel. Memory material is provided in the recess and contacts the electrodes of the transistor.

Abstract: A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.

Abstract: A method for forming a back-side contact for a vertical trench device includes grinding a back-side of a semiconductor substrate, milling a trench in the back-side of the semiconductor substrate, wherein a vertical trench fill is exposed, and depositing a conductive material, wherein the conductive material shorts the vertical trench fill to a buried plate. Grinding the back-side of the semiconductor substrate further includes grinding a dimple beneath a portion of the vertical trench device, wherein the trench is milled in the bottom portion of the dimple.

Abstract: A dynamic random access memory cell comprising: a trench capacitor formed in a silicon substrate; a vertical MOSFET formed in a silicon substrate above the trench capacitor, the vertical MOSFET having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical MOSFET, the adjacent vertical MOSFET having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and a punch through prevention region disposed between the buried second and third source/drain regions.

Abstract: A non-volatile multiple bit memory (10, 50) has electrically isolated storage elements (17, 21, 78, 80) that overlie a channel region having a central area (24, 94) with high impurity concentration. A planar gate (30, 84) overlies the storage elements. The high impurity concentration may be formed by a centrally located region (24) or by two peripheral regions (70, 72) having lower impurity concentration than the central portion of the channel. During a read or program operation, the channel area of high impurity concentration effectively controls a channel depletion region to enhance reading or programming of stored data bits. During a hot carrier program operation, the channel area of high impurity concentration enhances the programming efficiency by decreasing leakage currents in a memory array.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

Abstract: In a semiconductor integrated circuit device, a polycrystalline silicon film is formed along an inner wall of a trench in which a capacitor is to be formed, and the polycrystalline silicon film and a lower electrode is contacted to each other on the entire inner wall of the trench. Oxygen permeated into the lower electrode during a thermal treatment of a tantalum oxide film is consumed at an interface between the polycrystalline silicon film and the lower electrode. Thus, oxygen does not reach the surface of a silicon plug below the lower electrode that would cause oxidation on the surface of the silicon plug and form a high-resistance oxide layer when a dielectric film formed on a lower electrode of a capacitor of a DRAM is subjected to a thermal treatment in an oxygen atmosphere.

Abstract: A process for producing a semiconductor memory device comprises the steps of: (a) forming a floating gate on a semiconductor substrate having a dielectric film; (b) forming a side wall spacer comprising an insulating film on a side wall of the floating gate; (c) forming a groove by etching the semiconductor substrate using the side wall spacer as a mask; and (d) forming a low concentration impurity layer from one side wall to a bottom surface of the groove by an oblique ion implantation to the semiconductor substrate thus resulting, and forming a high concentration impurity layer from the other side wall to the bottom surface of the groove by in inverse oblique ion implantation.

Abstract: A stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling is described. An unconventionally high isolation oxide layer is formed in a shallow trench isolation (STI) in a substrate. The deep opening in the space between the STIs is conformally lined with a polysilicon to form a floating gate extending above the opening. A conformal intergate oxide lines the entire floating gate. A layer of polysilicon overlays the intergate oxide and protrudes downward into the openings to form a control gate with increased coupling to the floating gate.

Abstract: A nonvolatile memory transistor with multi values being capable of suppressing a short channel effect is provided. In an active region of a memory transistor, stripe-shaped impurity regions (pinning regions) are formed in a channel length direction. The pinning regions suppress the spread of a depletion layer of a drain region, and a short channel effect caused by fine processing. Furthermore, in a memory transistor using pinning regions, by assigning one value or one bit of data to each channel forming region, the memory transistor is allowed to have multi values. More specifically, the present invention has a configuration in which a floating gate electrode is provided on each of a plurality of channel forming regions via a first gate insulating film, and an electric potential can be applied independently to a plurality of pinning regions.

Abstract: A memory element includes a number of material areas isolated from one another to form at least one area with changed electrical and/or magnetic characteristics in an isolation area, which material areas have or form free charge carriers. An information unit can correspondingly be written to, deleted, and/or read from by influencing the material areas by applying an electrical potential to line devices that are provided in areas.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity and a semiconductor layer disposed on the substrate and also having the first conductivity. A recess is disposed in the layer and has a sidewall and a bottom. A gate insulator is disposed on the layer and extends to the sidewall of the recess, and a gate is disposed on the gate insulator. A body region is disposed in the semiconductor layer beneath the gate, has a second conductivity, and is contiguous with the sidewall of the recess. A source region is disposed in the body region, has the first conductivity, and is contiguous with the sidewall. A Schottky contact is disposed on the bottom of the recess, and a source metallization is disposed on the Schottky contact and on the sidewall of the recess.

Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.

Abstract: There is disclosed a semiconductor device comprising: at least one cell comprising a base region (32) of a first conductivity type having disposed therein at least one emitter region (36a, 36b) of a second conductivity type; a first well region (22) of a second conductivity type; a second well region (2a) of a first conductivity type; a drift region (24) of a second conductivity type; a collector region (14) of a first conductivity type; a collector contact (16) in which each cell is disposed within the first well region (22) and the first well region (22) is disposed within the second well-region (20); the device further comprising: a first gate (61) disposed over a base region (32) so that a MOSFET channel can be formed between an emitter region (36a, 36b) and the first well region (22); the device further comprising: a second gate disposer over the second well region (20) so that a MOSFET channel can be formed between the first well region (22) and the drift region (24).

Abstract: A MOSFET device design is provided that effectively addresses the problems arising from the parasitic bipolar transistor that is intrinsic to the device. The MOSFET device comprises: (a) a body region; (b) a plurality of body contact regions; (c) a plurality of source regions; (d) a plurality of drain regions; and (d) a gate region. In plan view, the source regions and the drain regions are arranged in orthogonal rows and columns, and at least a portion of the body contact regions are bordered by four of the source and drain regions, preferably two source regions and two drain regions.

Abstract: In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is formed in a first region of the semiconductor substrate. The second semiconductor layer is formed in a second region of the semiconductor substrate with an insulation film interposed between the semiconductor substrate and the second semiconductor layer. The third semiconductor layer is formed in a third region of a part of the semiconductor substrate with the insulation film and the second semiconductor layer extending in the third region and interposed between the semiconductor substrate and the third semiconductor layer. The top surface of the third semiconductor layer is higher than that of the second semiconductor layer in the second region.

Abstract: A method for fabricating a body contact silicon-on-insulator transistor (10) includes forming a semiconductor substrate (12) over an insulator (14) and lightly doping the semiconductor substrate (12) to form a body region (18). The method also includes forming a gate (20) over the semiconductor substrate (12) and separated from the semiconductor substrate (12) by a gate insulator layer (21). The gate (20) defines a source region (22), a drain region (24) and a contact region (26). The method also includes masking a portion (36) of the gate (20) and the contact region (26) and heavily doping the source region (22), the drain region (24) and an unmasked portion (36) of the gate (20) with a material having a conductivity substantially opposite a conductivity of the body region (18).

Abstract: An integrated circuit using silicon-on-insulator (SOI) has most of its transistors with their channels (bodies) floating. Some of the transistors, however, must have their channels coupled to a predetermined bias in order to achieve desired operating characteristics. In order to achieve the needed bias, a contact path is provided in the semiconductor layer of the SOI substrate and under an extension of the gate of the transistor. The extension is separated from the semiconductor layer by an insulator that is thicker than that for most of the transistor but advantageously is the same as that used for some of the thick gate insulator devices used, typically, for high voltage applications. This thicker insulator advantageously reduces the capacitance, but does not increase process complexity because it uses an insulator already required by the process.

Abstract: A semiconductor device comprising a source region, a drain region, and a buried insulating film. The buried insulating film is composed of a first part lying below the source and drain region, and a second part lying below the space between the source and drain regions. The first part of the buried insulating film is thicker than the second part. The bottoms of the source and drain regions contact the first part of the buried insulating film.

Abstract: A vertical bipolar transistor having low breakdown voltage, low ESD clamping voltage and high beta is fabricated in a semiconductor 301 of a first conductivity type, which has a buried layer 360 of the opposite conductivity type with sharp junctions, suitable as collector. This layer extends laterally to deep wells 371 of the opposite conductivity type, thus isolating the subsurface band 301a of the semiconductor of the first conductivity type. This band is suitable as the base and has a width 301c controlled by the proximity of the buried layer junction 360a. The emitter 310 is supplied by a surface region of the opposite conductivity type. The photomask, which is needed for implanting the low energy ions to create the extended emitter, is also used for the process step of implanting, at high energy and high dose, the ions needed (opposite conductivity type) to create the buried layer.

Abstract: A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide, first and second sidewall spacers, and nickel silicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first and second sidewall spacers are respectively disposed adjacent the first and second sidewalls. The first and second sidewall spacers are formed from a low-K spacer material that is substantially non-reactive with nickel, for example, SiHC, hydrogen silsesquioxane and methyl silsesquioxane. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. A method of manufacturing the semiconductor device is also disclosed.

Abstract: A semiconductor device includes a substrate of a first conductive type, and a well region of an opposite second conductive type is formed in the substrate. A first impurity region of the first conductive type extends to a first depth within the well region, and a second impurity region of the first conductive type is spaced from the first impurity region to define a channel region therebetween and extends to a second depth within the well region. Preferably, the second depth is greater than the first depth. A gate electrode is located over the channel region, and a silicide layer is formed at a third depth within the first impurity region. The third depth is less than the first depth, and a difference between the first depth and the third depth is less than or equal to a difference at which a leakage current from the silicide layer to the well region is sufficient to electrically bias the well region through the silicide layer.

Abstract: P-type metal-oxide semiconductor field effect transistor (PMOSFET) devices have a characteristic property known as threshold voltage. This threshold voltage may consist of separate threshold voltages associated with the main portion of the gate region of the device and with the sidewall corner of the device. Under some conditions, the threshold behavior in the sidewall corner region of the device may dominate the performance of the device, not necessarily in the manner intended by the designer of the device. A method of controlling threshold voltage behavior is described. In particular, ion implantation of nitrogen in the gate sidewall region of the device can provide such control. Devices made by this method are also described.

Abstract: A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.

Abstract: The semiconductor structure has an interconnect that is isolated by a cavity from an underlying insulating layer on a support. The fabrication method provides for the interconnect firstly to be patterned on a double layer and to be provided with an insulating covering. Then, an opening is etched into the insulating covering, and the lower conductive layer is selectively removed. As a result, one the one hand, low-capacitance wiring can be fabricated and, on the other hand, this enables MOS transistors to be programmed in a simple manner.

Abstract: A field-effect transistor (FET) includes a source electrode, a drain electrode, a gate electrode, a gate dielectric, and a semiconductor layer that functions as an active channel of the transistor. The active channel is configured to carry a current between the source and drain electrodes and has a conductivity responsive to voltages applied the gate electrode. The gate dielectric is located between the gate electrode and the semiconductor layer and includes a quasi-1D charge or spin density wave material.

Abstract: A semiconductor device capable of effectively preventing defective short-circuiting across a gate electrode and an impurity region and reducing the resistance of the gate electrode and the impurity region is provided. In this semiconductor device, a first gate film is formed on a channel region through a gate insulator film. A second gate film consisting of a first compound layer is formed on the first gate film. A second compound layer is formed on the surface of the impurity region. A reaction preventing film for preventing the first compound layer and the second compound layer from reacting with each other is formed on the second gate film. The first and second compound layers are formed independently of each other without reaction in the process of formation due to the reaction preventing film. Thus, defective short-circuiting across the gate electrode and the impurity region is effectively prevented while process tolerance is increased.

Abstract: A recess is produced in a material layer by creating at least a first and a second structure in various steps. The layers define each other laterally and extend to the bottom of the recess. The first structure and the second structure are so narrow that they can be made by creating conformally produced layers that have an independent thickness and are smaller than the depth of the recess. The conformally produced layers are formed in an appropriate deposition process. A covering structure can be produced on top of the first and second structure. An opening can be made in the covering structure, through which the first structure and the second structure can be removed in an etching step.

Abstract: The present invention provides a thin magnetoelectric transducer which has a projected size substantially equal to that of a pellet and which can be subjected to an inspection test nondestructively. The magnetoelectric transducer has a semiconductor device provided on the upper surface of a projecting portion of a projecting nonmagnetic insulating substrate 9 and comprising a magnetosensitive section 3 and inner electrodes 2 made of metal. A conductive resin layer 4 is formed on the internal electrodes 2 and on part of the side surfaces of the projecting portion. A strain buffering layer 5 is formed at least on the magnetosensitive section 3. Furthermore, at least the strain buffering layer 5 on the magnetosensitive section 3 is coated with a protective layer 6.

Abstract: An N-type impurity diffusion region is formed in an element forming region surrounded by a field insulating film. In a region between an end portion of the N-type impurity diffusion region and an end portion of the field oxide film, a P-type impurity diffusion region is formed so as to contain an interface level present portion under a bird's beak portion. Thus, a PN junction is formed in a position distant from the interface level present portion. Therefore, even if a voltage is applied to the PN junction, a depletion layer will not reach the interface level present portion. Consequently, a semiconductor device, which suppresses an occurrence of a leakage current along the lower surface of an element isolation insulating film caused by the interface level present portion undesirably included in the depletion layer, as well as a manufacturing method of the same can be obtained.

Abstract: The invention provides an optical device having an optical element, a substrate, and a flexible member. A first portion of the flexible member is disposed so as to be spaced from the substrate, a second portion surrounding the first portion is adhered to the substrate, and a closed space is defined between the first portion and the substrate. The optical element is mounted on the substrate within the closed space.

Abstract: A semiconductor energy detector as disclosed herein is arranged so that an aluminum wiring pattern is formed on the front side of transfer electrodes of a CCD vertical shift register, which pattern includes meander-shaped auxiliary wirings for performing auxiliary application/supplement and additional wirings for performing auxiliary supplement of transfer voltages in a way independent of the auxiliary wirings with respective ones of such wirings being connected to corresponding transfer electrodes to thereby avoid a problem as to lead resistivities at those transfer electrodes made of polycrystalline silicon, thus achieving the intended charge transfer at high speeds with high efficiency.

Abstract: Besides the central pn-junction and the central electrode, a PD chip has a peripheral pn-junction and a peripheral electrode which do not appear on the sides. The ends of the peripheral pn-junction are covered with a protection layer for preventing self-shortcircuit. A reverse bias is applied to the peripheral electrode for making a wide depletion layer beneath the peripheral pn-junction. Extra carriers generated by peripherally-incidence rays are fully absorbed by the peripheral depletion layer and annihilated by the reverse bias.

Abstract: A photoelectric conversion element comprising a substrate and a light sensor disposed on a surface of the substrate and receiving high speed optical pulse signals and converting them into high frequency waves in which the light sensor comprises at least carbon nano-tubes, as well as a photoelectric conversion device having the element, for directly converting high speed optical pulses signals in a communication band into signals of high frequency waves or electromagnetic waves.

Abstract: In an SRAM, memory cells are each constructed of four NMOS transistors and two PMOS transistors 25 and 26. The four NMOS transistors are each constructed of DTMOS in which the channel region is electrically connected to the gate. In each NMOS transistor, a threshold voltage Vth is lower in an ON stage than in an OFF stage. The threshold voltage Vth in the OFF stage is equivalent to that of an ordinary NMOS transistor in which the channel region is not electrically connected to the gate. Read and write circuits of the SRAM also include MOS transistors formed of DTMOS in which the channel region is electrically connected to the gate.

Abstract: An integrated circuit that includes a high breakdown voltage bipolar transistor. The bipolar transistor includes an emitter 36, a base 32, and a collector structure. The emitter 36 is adjacent to and overlies the base 32 and the base 32 is adjacent to and overlies a core portion 48 of the collector structure. The collector structure includes, in addition to the core portion 48, a collector contact region 31 and a lateral collector region 50 between the core portion 48 and the collector contact region 31. The lateral collector region 50 is thinner than said collector contact region at some point along its length.

Abstract: A thermal and electrical interconnect for heterojunction bipolar transistors is disclosed wherein the interconnect is essentially comprised of gold and in thermal and electrical contact with each of the interdigitated emitter fingers and is capable of transporting heat fluxes between 0.25-1.5 mW/&mgr;m2. The interconnect is electrodeposited to form a low-stress interface with the emitter finger, thereby increasing the lifetime and reliability of the transistor.

Abstract: An optical semiconductor device having a low threshold current and easiness of a single transverse mode oscillation is provided. The optical semiconductor device has a low device parasitic capacitance that allows a direct modulation at high speed. The optical semiconductor device comprises a first conduction type substrate, a stripe shaped active layer formed on the first conduction type substrate, a mesa shaped burying layer formed around the active layer and having a larger band gap than that of the active layer, and a groove that electrically isolates the burying layer, wherein the section of the burying layer is in an inverse trapezoid shape of which the upper base side is longer than the lower base side.

Abstract: A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.

Abstract: A lead frame including a first set of leads in a first plane and a second set of leads in a second plane offset vertically from the second plane. The leads in the first and second planes are offset from each other by a lead width.

Abstract: A molded plastic package for semiconductor devices incorporating a heat sink, controlled impedance leads and separate power and ground rings is described. The lead frame of the package, separated by a dielectric layer, is attached to a metal heat sink. It has more than one ring for power and ground connections. The die itself is attached directly onto the heat sink through a window on the dielectric and provides high power dissipation. The package is molded using conventional materials and equipment.

Abstract: The preferred embodiments provide a lead frame wherein a first air vent 29 and a second air vent 30 are formed in an air vent forming region 32. When resin-molding, one end of this first air vent 29 is disposed within the cavity, whereby air in the cavity when resin-molding can be completely released to the outside of the cavity. As a result, a package after resin-molding includes no unfilled regions or voids, whereby a semiconductor device with excellent product quality can be provided. In the background, air in cavities could not be completely released when resin-molding since, for instance, one air vent was provided at a position apart from the cavity region, and unfilled regions or voids were created.

Abstract: A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A stack package has a lead frame and first and second stacked chips. The lead frame comprises first and second lead groups respectively corresponding to the first and second chips and a plurality of external connection terminals for electrically interconnecting the first and second chips to an external device. Each of the first and second chips has its own common and independent electrode pads, and each of the first and second lead groups has its own common and independent leads. The common leads and the common electrode pads are for address and control signals to and from the first and second chips, and the independent leads and the independent electrode pads are for data input and output to and from the first and second chips.