Abstract: A MOSFET logic circuit for performing a logic AND operation is presented including three transistors, wherein at least two input signals are provided to the circuit and an output signal indicative of an AND operation performed on a first and second input signal of the at least two input signals is output from the circuit. In another embodiment, a MOSFET true and complement signal generating signal is presented including at least one MOSFET inverter logic circuit, and first and second MOSFET AND logic circuits, wherein each of the first and second AND logic circuits includes three transistors. The true and complement signal generating circuit receives first and second input signals and outputs a true signal and a complement signal indicative of the first input signal.

Abstract: A signal transmission circuit, which is capable of improving DC characteristics, delay characteristics, and linearity in a voltage region and maintaining tolerant functions, is provided. The signal transmission circuit includes a first transmission circuit, a second transmission circuit, an inverting circuit, a first switching circuit, and a second switching circuit. The first transmission circuit transmits a signal of a first node to a second node, and the second transmission circuit transmits the signal of the first node to the second node. The inverting circuit inverts the signal of the second node, and the first switching circuit pulls down a third node in response to an output signal of the inverting circuit. The second switching circuit transmits the signal of the first node to the third node, and the second transmission circuit is controlled in response to the signal of the third node.

Abstract: In a composite IC in which integrated are a power transistor, a bipolar analog circuit and a MOS logic circuit, a load-driving semiconductor device is provided which is capable of certainly placing the power transistor into an off-condition at power-on for stopping the driving of a load. In the semiconductor device, a high-side switch MOS transistor, a charge pump, a bipolar analog circuit, a charge pump driving CMOS logic circuit, a level conversion CMOS logic circuit and a forcibly stopping bipolar transistor 90 are made in the form of an IC, and the forcibly stopping bipolar transistor receives, through its base terminal, a signal which inverts when a drive voltage exceeds a predetermined value to turn to an on-condition. This operation places the bipolar analog circuit into a driving-stopped condition.

Abstract: A phase difference between a feedback clock signal corresponding to an internal clock signal generated via a variable delay line and a buffered clock signal corresponding to an external clock signal is detected by a phase detector, and a result of detection is transferred via a shifting circuit. When a down signal from the shifting circuit is activated by a delay control circuit, the down instruction signal is forcibly maintained to be active for a predetermined clock cycle period. When the down instruction signal becomes inactive from the active state, a count control circuit sets a count unit of the counting circuit to the minimum value. The delay amount of the variable delay line is set according to an output count bit of the counting circuit. Therefore, it is possible to reduce the number of clock cycles required until an internal clock signal is synchronized in phase with the external clock signal.

Abstract: A semiconductor integrated circuit comprising a voltage controlled delay cell including a first voltage controlled resistor and a current source transistor of a MOS type differential amplifier circuit, the first voltage controlled resistor functioning as a load resistor, wherein a resistance value of the first voltage controlled resistor is controlled according to a first bias voltage, and a current of the current source transistor is controlled according to a second bias voltage, and a bias circuit including a first replica circuit and a second replica circuit, the first replica circuit having a structure equivalent to that of the voltage controlled delay cell, the second replica circuit having a structure equivalent to a structure in which the first voltage controlled resistor is replaced by a constant resistor, the bias circuit configured to generate and supply the first bias voltage and the second bias voltage to the voltage controlled delay cell.

Abstract: A semiconductor integrated circuit including a clock signal propagation gate capable of reducing clock signal skew and controlling a clock signal is provided. The clock signal inputted at a clock origin propagates through buffers (30, 31) to a clock propagation control gate (32). The two-level clock propagation control gate (32) includes an inverter at the first level, and a NAND gate at the second level. The clock signal passed through the clock propagation control gate (32) propagates through buffers (33, 34) to reach a sequential circuit (35) at an end point. The NAND gate (39) at the second level of the clock propagation control gate (32) includes nMOS transistors (42, 43) and pMOS transistors (40, 41). The inverter (36) at the first level includes a pMOS transistor (37) and an nMOS transistor (38).

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to (i) a clock signal and (ii) one or more second control signals. The second circuit may be (i) coupled to the first circuit via one or more path circuits and (ii) configured to present an output signal in response to the one or more first control signals. All of the one or more first control signals may have a preferred edge skew.

Abstract: An absolute value circuit includes an operational amplifier, the output of which is coupled to control inputs of complementary polarity transistors having current flow paths therethrough coupled in series with inputs of current mirror amplifier stages. A common node of the current flow paths through the transistors is coupled to an input of the operational amplifier to which a current waveform is applied. The current mirror amplifier stages are configured so as to provide like polarity output currents. The outputs of the current mirror amplifier stages are combined to produce an output current that corresponds to a full wave rectification or absolute value of an input current coupled to the operational amplifier.

Abstract: A signal-level compensating system consists of a voltage-follower stage, a sensor and a output signal compensator. The voltage-follower stage includes a signal input for receiving an input signal, a signal output, and at least one transistor coupled between the signal input and the signal output for providing an output signal responsive to the input signal. The sensor provides a control signal indicative of variations in at least one of the power supply voltage and transistor characteristics of the transistor. The output signal compensator is coupled to the signal output and provides a compensator output signal responsive to the control signal for reducing the impact of the variations on the voltage-follower output signal.

Abstract: A variable-gain BiCMOS transconductance amplifier (VGA). An NMOS differential pair amplifier with bipolar cascoding provides continuous gain control by adjustment of drain-source voltage to shift the NMOS differential pair from a saturation region operation and high gain to a triode operation and low gain. A simple control circuit is used in order to generate the desired exponential gain to linear control voltage characteristic that is stable over temperature and process. The shift from saturation to triode operation of the input NMOS differential pair simultaneously increases the input linearity as the gain is reduced.

Abstract: A buffered bootstrapped input switch employs cancelled charge sharing for use in high performance sample and hold switched capacitor circuits especially useful for implementing, for example, an analog-to-digital converter (ADC) or amplifier circuit front end sampling network, among others. A scheme is employed for estimating the charge loss from the bootstrapping capacitor to the gate of the bootstrapped input switch, storing the estimated charge loss on a small capacitor, buffering the small capacitor, and then adding the estimated charge loss in series to the bootstrap capacitor, to provide an almost ideal bootstrap network.

Abstract: A semiconductor integrated circuit can variably set the driving power of all or part of internal input/output terminals and internal output terminals used within a multi-chip package. It can increase the driving power at an individual wafer test before packaging to sufficiently drive a load connected between a tester and the internal input/output terminals and internal output terminals, and can reduce the driving power after packaging. It can prevent noise and power consumption from being increased.

Abstract: An apparatus and method for improving the gate oxide reliability of an antifuse circuit is provided by coupling the gate input of a protection device of the antiftise circuit to a voltage converter circuit. In a program mode, a first voltage is applied through the voltage converter circuit to the gate input of the protection device to limit the voltage passed to internal transistor devices, thus increasing their gate oxide reliability. In a normal operation mode, however, a second, lower voltage is applied through the voltage converter to the gate input of the protection device to remove the large voltage stress placed across the gate oxide of the protection device itself. The voltage converter may attenuate the first voltage to create the second voltage or it may switch its output between the first and second voltage levels.

Abstract: A voltage boost circuit includes a boost capacitor; a charge circuit for charging in the charging mode the boost capacitor to a supply voltage, the charging circuit including a charging MOS switch interconnected between the supply voltage and one terminal of the boost capacitor and a back gate isolation circuit connected to the back gate of the charging MOS switch and including a first switch for connecting the back gate to the supply voltage for reverse biasing the back gate in the charging mode and the second switch for connecting the back gate to the one terminal of the boost capacitor for reverse biasing the back gate in the boost mode to prevent charge loss from the boost capacitor; and a boost bias voltage and a boost switch for connecting the second terminal of the boost capacitor to the boost bias voltage in the boost mode.

Abstract: A method and an integrated circuit for boosting a voltage are disclosed. A two-stage charge pump is used and has switches and capacitors. Known charges pumps can be single-stage or multi-stage and can achieve only a doubling of the input voltage in practice, depending on the configuration of the switches and capacitors and whereby each stage is provided with a separate drive. An improved two-stage charge pump can triple the input voltage and is advantageously achieved. N-type field effect transistors that are embedded in the substrate of an integrated circuit are utilized as the switches. It is further provided that a second series pass transistor is driven at its bulk terminal and/or its gate by a capacitor and a level shifter. This advantageously obviates the need to expand the width of the additional series pass transistor.

Abstract: A variable charge pump circuit uses a plurality of selectable loads to minimize the voltage ripples of the pumped output by selecting the appropriate load for a preselected pump voltage. The charge pump circuit also compares the pump voltage to a reference voltage to shut down the variable charge pump circuit if the pump voltage is larger than the reference voltage. The charge pump circuit also compares the maximum voltage output to the reference voltage to monitor whether the maximum ripple on voltage output is larger than the reference voltage. The charge pump circuit comprises one or more stages operable to receive a supply voltage and generate one or more pump voltages, a plurality of loads each associated with a specific pump voltage, and a load selector means coupled to the output pump and the plurality of loads for selecting a load associated with a specific pump voltage.

Abstract: Boosted voltage generates and methods for an integrated circuit are configured to boost an initial boosted voltage to a first boosted voltage in response to detecting a drop in the initial voltage. The first boosted voltage is then boosted to a second boosted voltage in response to a pulse. The second boosted voltage is then repeatedly boosted to approach the initial boosted voltage in response to an oscillating signal. Accordingly, stable boosted voltages may be generated.

Abstract: A bias circuit integrated on a silicon wafer includes first, second and third branches. The first branch includes a first PMOS transistor in series with a first NMOS transistor. The second branch includes a second PMOS transistor, a second NMOS transistor and an electric resistor in series. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. The first branch and the second branch are arranged as a current mirror. The third branch includes a third PMOS transistor in series with a third NMOS transistor. The third PMOS and NMOS transistors are arranged to maintain a drain voltage of the first PMOS transistor that is substantially identical to a drain voltage of the second PMOS transistor.

Abstract: A stable current source circuit with a compensation circuit, comprising: a PMOS current mirror, connected to a power supply so as to output a stable current; an NMOS current mirror, connected to a third bipolar junction transistor and a fourth compensation resistor; a third bipolar junction transistor, the emitter of the third bipolar junction transistor connected to the NMOS current mirror and both of the base and the collector grounded; and a fourth compensation resistor, interconnected between the NMOS current mirror and the compensation circuit. Alternatively, a compensation capacitor can be added so as to obtain better stability.

Abstract: The present invention relates to a boosting circuit. A boosting voltage (VBOOT) is dropped to a given voltage level through a pre-select clamp circuit and the boosting voltage (VBOOT) is again dropped through a clamp circuit, depending on the power supply voltage, so that a final target word line voltage is generated. Accordingly, a read access time is rapid upon a read operation, the current consumption is minimized and a stabilized word line voltage can be generated.

Abstract: The present invention relates to a demodulation structure and method for downconverting and demodulating a digitally modulated signal So, with a local oscillator means (1; 5; 8) for providing a local oscillator signal Slo a mixer means (2) for mixing said local oscillator signal Slo and said digitally modulated signal S0 in order to obtain a mixed signal, a lowpass filter means (3) for lowpass filtering the mixed signal from the mixer means (2) and an analog-to-digital converting means (4) for converting the filtered signal from the lowpass filter means (3) into a downconverted and demodulated digital signal Sl, whereby the local oscillator signal is set in respect to the modulated digital signal so that the downconverted and demodulated digital signal output from the analog-to-digital converting means comprises to serially arranged information parts. The present demodulation structure provides a very simple structure with improved amplitude and phase imbalances.

Abstract: An FM demodulator compensates for DC offset by detecting the positive peak value of the frequency demodulated signal (D1, C2, R1) and the negative peak value of the frequency demodulated signal (D2, C3, R2). The mean of the positive and negative peak values is determined (C1, R3, R4) to produce an estimation of a DC offset value. This estimated DC offset value is then used to compensate for DC offset in the frequency demodulated signal. This circuit has the advantage of enabling the DC offset to be calculated without requiring complex digital signalling processing, and without requiring the input signal to have a zero mean. A signal strength signal RSSI may be used to disconnect the DC offset compensation circuitry during periods when the input signal strength is weak.

Abstract: A differential amplifier includes first and second outputs and first and second supply rails. The differential amplifier further includes offset cancellation circuitry. The offset cancellation circuitry is operable during a calibration mode to generate an offset cancellation signal when the first and second outputs are both coupled to a voltage between the first supply rail and the second supply rail. The offset cancellation signal is for facilitating at least partial cancellation of an offset voltage associated with the first and second outputs during a normal operation mode of the differential amplifier.

Abstract: A method to generate virtual multi-level output pulses for a Class-D Amplifier, where the time-voltage-area corresponds to a multiple of digital levels is achieved. A class-D Amplifier using PDM (Pulse Density Modulation) normally converts the input signal with a Sigma Delta Modulator into high-frequency pulses of equal width and typically drives an H-Bridge, with its 3 physical output levels. The disclosed invention however adds the methods to produce pulses with a multiple of discrete values of width and provides the method to generate a pulse length select control signal for these variable-width-pulses. Using multi-level pulse widths, in contrast to just a single pulse width, allows the reduction of the pulse-sampling rate by the same factor. Or Multi-level pulse widths allow a better quality output signal. In addition, better power efficiency is achievable.

Abstract: A transformer of power-amplifier module for an audio device includes a casing having a first plug and a second plug formed thereon. In the casing, there is an amplifying circuit having an input electrically connected to the first plug and an output electrically connected to the second plug of the casing. The amplifying circuit terminates in a transformer at the output. Furthermore, the transformer is adjustable so as to control the amplitude of output voltage of the transformer of power-amplifier module.

Abstract: A circuit with low noise and reduced offset that feeds an input of an opamp with a programmable feedback resistor that provides variable gain settings. Input biasing currents are varied using control bits that are also used to adjust the gain. When the input signal is small (gain at higher setting), a minimum bias current is provided to source the input voltage swing. This scheme reduces the noise and offset generated by the lower transconductance of a biasing transistor while maintaining a constant SNR and fixed offset even in the presence of relatively small input swings. Also, when the input signal is large (gain at lower setting), a maximum bias current can be provided to accommodate the relatively large input swing level. Although the overall noise and offset current are increased for large input swings, the overall SNR and offset is maintained for relatively lower input swings.

Abstract: An amplifier chain that switches between a saturated mode of operation and a linear mode of operation comprises at least two amplifier stages. A switch is associated with the first amplifier stage and dampens the gain of the amplifier chain when the switch is closed. In a first embodiment, this is done by bypassing the first amplifier stage. In second and third embodiments, this is done by providing a feedback loop to the first amplifier stage. Dynamic device scaling and changing the bias may also be used to affect the performance of the amplifier chain.

Abstract: In a predistortion type linearizer including a FET, an input matching circuit connected to the drain of the FET for receiving an input signal, an output matching circuit connected to the source of said the FET for outputting an output signal, and a inductor having a first terminal connected to the gate of the FET and a second terminal for receiving a first control voltage, a variable impedance circuit is connected to the second terminal of the inductor, and the impedance of the variable impedance circuit is adjusted by a second control voltage.

Abstract: The amplifier comprises a power suppl, a current sensing element for sensing a current in the current path of the power supply, a detecting circuit responsive to the current sensing element, and voltage reducing means for reducing the signal amplitude of at least one of the audio signals in response to the detection circuit. The detecting circuit comprises in a preferred embodiment a threshold circuit, and when the current in the current path of the power supply is above a predefined threshold, the detection circuit together with the voltage reducing means reduce at least the signal amplitude of one of the audio channels. The current sensing element is for example a current sensing resistor and the detecting circuit is a voltage detection circuit in parallel to this resistor. The voltage reducing means comprise advantageously two diodes for each channel, via which a positive and a negative voltage limit is applied to the signal path of the audio signals.

Abstract: The present invention discloses a new family of switching amplifier classes called “class E/F amplifiers.” These amplifiers are generally characterized by their use of the zero-voltage-switching (ZVS) phase correction technique to eliminate of the loss normally associated with the inherent capacitance of the switching device as utilized in class-E amplifiers, together with a load network for improved voltage and current wave-shaping by presenting class-F−1 impedances at selected overtones and class-E impedances at the remaining overtones. The present invention discloses a several topologies and specific circuit implementations for achieving such performance.

Abstract: A receiver is provided with delay generally insensitive to input amplitude and slew rate. The receiver includes a first differential transistor pair having a common emitter connection. A differential input is applied to a respective base of the differential transistor pair. A pair of load transistors is connected to the respective collector of the differential transistor pair. A respective resistance is coupled to a base of the load transistors for providing a delay independent of the differential input; and a pair of bias transistors is coupled to the respective collector of the differential transistor pair for biasing the load transistors.

Abstract: An error amplifier circuit includes a differential amplifier with a cascode gain stage and an amplifier. The differential amplifier receives a first input signal and a second input signal and generates an output signal on an output terminal indicative of the difference between the first input signal and the second input signal. The cascode gain stage is coupled to receive the output signal of the differential amplifier and generates a second output signal. The cascode gain stage is biased by a bias current generated by a current mirror. The amplifier receives the second output signal from the cascode gain stage and generates a third output signal. The cascode gain stage is biased by a control signal for causing said current mirror to generate a bias current having substantially constant magnitude over variations in voltage differences of the first input signal and the second input signal.

Abstract: A voltage controlled transconductor (VCT) for receiving a differential input signal comprising a first voltage signal and a second voltage signal, and for providing a differential output signal comprising a first output current signal and a second output current signal. The VCT includes a first side transconductor circuit having two parts of the same construction, the first part being capable of conducting a first current signal and the second part being capable of conducting a second current signal, the first current signal and the second current signal being controlled by the first voltage signal. The VCT also includes a second side transconductor circuit having two parts of the same construction, the first part being capable of conducting a third current signal and the second part being capable of conducting a fourth current signal, the third current signal and the fourth current signal being controlled by the second voltage signal.

Abstract: It is an object of the present invention to provide a variable gain amplifier of which impedance does not change when gains are switched. A transistor is turned on in a high-gain state and transistors are turned on in a low-gain state to switch between the gains, the area of the transistor is made equal to the area of the transistor to keep the same output load conditions and the same output impedance both in the high-gain state and the low-gain state. While the input impedance of a transistor becomes high because the transistor in a high-gain path is turned off in the low-gain mode, current passes through a transistor to lower the impedance of the collector of a transistor and, as a result, the input impedance is kept the same both in the high-gain state and the low-gain state.

Abstract: A low power current feedback amplifier having a lower output impedance input stage is provided. To reduce the output impedance, an input stage comprises a closed-loop input buffer. An exemplary input buffer comprises a closed-loop current feedback amplifier configured within the overall current feedback amplifier, wherein the output of the input buffer corresponds to the inverting node of the overall current feedback amplifier. The closed-loop configuration of the input buffer is facilitated by the use of an internal feedback resistor coupled from an inverting input terminal of the input buffer to the output of the input buffer, which corresponds to the inverting input terminal of the overall current feedback amplifier. The closed-loop input buffer realizes a low output impedance since the loop gain reduces the output impedance of the input buffer. With a lower output impedance, the bandwidth of the current feedback amplifier becomes more independent of the gain, even at low current implementations.

Abstract: An active radio frequency cavity amplifier (ARFCA) is provided having a housing defining an input cavity and an output cavity; a plurality of transistors mounted to said housing, each of the plurality of transistors having an input lead and an output lead; a first RF power coupling mechanism disposed within the housing in proximity to the input cavity for coupling RF power from a source into the input cavity to generate an RF field; a first conducting assembly having a plurality of conductors each configured to contact a respective input lead of each of the plurality of transistors for coupling the RF field in the input cavity to the input leads of the plurality of transistors; a second conducting assembly having a plurality of conductors each configured to contact a respective output lead of the plurality of transistors for coupling the amplified RF power from the output leads of the plurality of transistors to the output cavity; and a second RF power coupling mechanism disposed within the housing in proximi

Abstract: A high-frequency power amplifier includes a transistor which is inputted with a high-frequency signal, amplifies the high-frequency signal and outputs the same; a fundamental-signal matching circuit, one end of which is connected to an output of said transistor and which matches at least the impedance of fundamental signal in the amplified high-frequency signal and outputs the same from the other end; a power supply which supplies electric power to said transistor from a node located in an interval from the output of said transistor to said fundamental-signal matching circuit; a first inductor, one end of which is connected to said power supply; a second inductor connected in series between the other end of said first inductor and said node; and a first capacitor, one end of which is connected between said first inductor and said second inductor while the other end thereof is connected to a reference potential, said first capacitor forming a first series-resonant circuit with said second inductor and a parall

Abstract: A device characteristic changing apparatus is provided for changing a characteristic of a device. The device characteristic changing apparatus comprises a time scale generator unit for generating a time scale on which a device operates, and a time scale changing unit for changing the time scale, so that a characteristic of a device is changed by changing the time scale on which the device operates.

Abstract: A system is provided for compensating for tuning gain variations in a phase lock loop. Compensation is performed by a calibration system that estimates the tuning gain of the oscillator and then adjusts the charge pump current value by a ratio of the nominal tuning gain to the measured tun gain. The tuning gain measurement is performed by measuring the change in the voltage controlled oscillator's tuning control voltage when the phase lock loop is locked to two different frequencies, which are separated by a fixed, predetermined amount. The two frequencies may be above or below the final output frequency of the VCO, or the second frequency may be the final frequency in order to reduce calibration time and settling time.

Abstract: The device (1) includes a mixer (4) which generates a signal (S4) having a frequency (F4) equal to the difference between two frequencies (F2, F3), which are those of two signals (S2, S3) each generated by a generator (2, 3) and which vary parabolically as a function of the temperature (T) with quadratic coefficients (&bgr;1,&bgr;2) that are different to each other. In order for the frequency (F4) of the signal (S4) generated by the mixer (4) to be at least substantially independent of the temperature (T), the generators (2, 3) are arranged such that the ratio of the quadratic coefficients (&bgr;1,&bgr;2) is equal to the inverse of the ratio of values (F2r, F3r) that the corresponding frequencies (F2, F3) have at a determined temperature (Tr).

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: An inventive voltage-controlled ring oscillator provides a relatively stable oscillation frequency even with a lower power supply voltage. The oscillator includes an odd number of inverters and a variable delay circuit connected in a ring. The variable delay circuit comprises first and second control terminals to which first and second control signals that determine the amount of delay are applied; and a switching circuit including a first and second switching elements each comprising a MOS transistor.

Abstract: A circuit to generate antipodal PSK signal and a correlator circuit for recovering information from PSK (phase shift keying) UWB transmissions includes providing a circuit component characterized by a transfer function having alternating stable and unstable regions. By setting the operating point in a stable region or an unstable region, a non-oscillatory or an oscillatory output signal can be produced.

Abstract: An oscillation circuit comprises first and second transistors and a load. The first transistor includes a base inputted an oscillation signal, an emitter connected to a ground potential, and a collector. The second transistor includes a collector connected to a power supply potential, a gate and an emitter. The load has one end connected to the collector of the first transistor, and the other end connected to the emitter of the second transistor, and causes a voltage drop proportional to the power supply potential. The voltage drop caused by the load reduces dependency of a base-collector voltage of the first transistor upon the power supply potential.

Abstract: A vibrating reed includes a base; and a vibration arm section formed so as to protrude from this base wherein a through groove is formed in the vibration arm section, and a rigidity reinforcing section is provided in the through groove, and thus the frequency is not decreased and the CI value is not increased.

Abstract: A frequency tracking circuit and method comprising a master crystal oscillator circuit is used for frequency tracking between a handset and a base station comprising a calibration subsystem for taking a temperature measurement, a reference control circuit for determining a numerical value needed to align a handset frequency with a base station frequency, an adder for adding the numerical value to a previous numerical value determined by the reference control circuit, a latch for latching the output of the adder, and a low precision master crystal oscillator for clocking the frequency of the latch. The most significant bit from the latch is input into a phase/frequency detector for forcing a voltage controlled oscillator to track a desired frequency.

Abstract: The controlling circuit element of a voltage controlled oscillator (VCO) for use in a phase lock loop (PLL) is a varactor connected between the terminals used to convey the power supply voltage and the frequency control voltage. The loop filter, implemented in a shunt configuration at the input of the VCO, is also connected between the power supply and frequency control voltage terminals. As a result, any variations in the power supply voltage appear at both terminals of the varactor due to the voltage coupling effect of the loop filter between the shared power supply and frequency control voltage terminals.

Abstract: A frequency-switching oscillator which satisfies the conditions for oscillation, even when the switch width of the oscillation frequencies is great, without requiring a number of components to be increased. The impedance of a resonance system is set to satisfy the conditions for oscillation at two or more oscillation frequencies. A switching member is provided in the amplification system, and the oscillation frequencies are switched by changing the impedance of the amplification system. Since the resonance system does not require a switching member, loss is not caused by switching member in the resonance system, so the output level does not drop and the carrier-to-noise ratio does not deteriorate. Furthermore, without a switching member in the resonance system, the number of components can be reduced, making miniaturization and cost reduction possible.

Abstract: A nonreciprocal circuit device includes a resin case, and external terminals insert-molded with the resin case when the resin case is molded, so as to project from the resin case. The resin case is provided with concavities each formed in a bottom face of the resin case and enclosing a position at which each external terminal projects. During insert molding, any excess resin is absorbed by the concavities, whereby the resin is prevented from being applied to bottom faces of the external terminals.

Abstract: A non-reciprocal circuit device includes a lower metal case, a terminal resin case, a central-electrode assembly, an upper metal case, and a permanent magnet. The central-electrode assembly includes a ferrite to which a dc magnetic field is applied by the permanent magnet, and central electrodes disposed around the ferrite. The terminal resin case includes two sets of opposing side walls and a bottom wall, and cut surfaces formed when a lead frame is separated are provided in one set of side walls, respectively. Terminals for surface mounting are provided on another set of side walls which is different from the one set of side walls.