Abstract: In an overload current protection device for cutting off power from a power supply to a load (3) such as a motor by means of a contactor (switch) (2) at overloading, an MI element having a magnetic impedance (MI) effect as current detectors (4a, 4b, and 4c) is installed at a position capable of detecting a current flowing through the secondary winding of power supply transformers (5a, 5b, and 5c) that generate a control power supply to thereby reduce costs without using a constant voltage power supply and expand a current detection range by eliminating magnetic saturation due to a core, a problem with a conventional current transformer, thereby providing at low costs a high-precision overload current protection device having a wide current detection range.

Abstract: A description is given of a measuring instrument to be connected to a higher-order unit having at least a first and an identical second pair of terminals, which can be connected electrically, very simply and without errors, to the higher-order unit, the measuring instrument comprising: a first pair of lines, to be connected to the first pair of terminals, via which a signal current flows during operation, the signal current being a measure of an instantaneous measured value, and a second pair of lines, to be connected to the second pair of terminals, via which a supply current flows during operation, whose value is greater than or equal to a minimum signal current and less than or equal to a maximum signal current.

Abstract: A method for measuring properties of a flowing fluid composition comprising at least two different components, while the fluid composition is flowing through a duct or channel, which flow meter comprises: at least one sensor (2, 3) in the shape of a cavity resonator through which at least a portion of the fluid composition passes; at least one electronic circuit (4) comprising a transmitting means (11) adapted to transmit an electronic signal (9) into the flowing fluid via a probe (7, 11); at least one receiving means adapted to receive a signal which has traveled through the flowing fluid composition; and at least one signal processing unit (12) adapted to deduce fluid specific signals from the received signals. An oscillator included in the electronic unit (4) may, in a preferred embodiment, be phase locked to the resonant frequency of the sensor (2, 3) (in a so-called FSA (feedback self-oscillating amplification) method).

Abstract: A compact and light semiconductor sensor for detecting pressure and acceleration. A pressure sensor is formed on a first surface of an intermediate plate. An acceleration sensor is formed on a second surface of the intermediate plate. A first plate having a diaphragm is bonded to the intermediate plate to define a hermetic chamber of the pressure sensor. A second plate is bonded to the second surface of the intermediate plate. A spring support supports the mass in a manner relatively movable with respect to the second plate.

Abstract: A sensor assembly for sensing angular position of one object relative to another object. A capacitor is formed between a transmitter capacitor plate having a pair of transmitter electrodes and a receiver capacitor plate having preferably eight receiver electrodes forming four receiver electrode pairs. A dielectric rotor rotates between the plates, the rotor having first and second segments each subtending 67.5 which are mutually separated by a vacancy subtending 45 degrees, and further having a third segment subtending 45 degrees disposed between the first and second segments diametrically opposite the vacancy. An electrical circuit measures net charge induced on each of the receiver electrode pairs, wherein the charges indicate the angular position of said rotor relative to said transmitter and receiver capacitor plates.

Abstract: An on-line method for determining the condition of low conductivity working fluids using alternating current, electro-impedance spectroscopy is provided by making measurements over a range of frequencies at temperatures at or above 50° C.

Abstract: A probe that connects test and measurement equipment to a device under test via a plurality of cables. The probe is formed of a plurality of printed circuit boards that are stacked together. Each board is connected to one of the plurality of cables and has a longitudinal set of pads along an edge electrically connected to the cable. The stacked plurality of printed circuit boards form a two dimensional array of pads for connecting to a similar set of pads on a device under test.

Abstract: A clock generation circuit for providing high-frequency scan testability with a low-speed tester includes a clock selector and control logic. The clock selector receives a reference clock signal and a high-frequency clock signal and produces an output signal selected from the reference clock signal and the high-frequency clock signal based on a clock selector control signal. The control logic that receives a capture signal and produces the clock selector control signal to modify the clock selector output signal in response to the capture signal. The clock selector output signal may be used to provide high-frequency scan testability with a low-speed tester.

Abstract: A method for performing backside Photon Emission Microscopy (PEM) on wafer-level failure analysis. The method provides that a die is located by applying reversed-biased voltage to the wafer and the backside of the wafer is thereafter observed. The die of interest will illuminate brightly, because of the electron-hole recombination from the reverse-biased protection diode. Such a method is easy to perform and provides a low cost and time-saving way to accurately identify a die and acquire emission.

Abstract: A method and apparatus is provided for stress testing integrated circuits to determine their susceptibility to hot carrier charge injection damage. The system includes a hot carrier injection source formed on a semiconductor wafer carrying the ICs under test. The carrier source comprises an adjustable, voltage controlled oscillator having a variable frequency AC output test signal, and a modulator circuit for varying the duty cycle of the test signal applied to the ICs.

Abstract: An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die.

Abstract: A method of predicting current boost levels and applying them to precharge current-driven elements in a matrix, and a method of manufacturing devices for this purpose. Elements are driven during successive scan cycles, each having a precharge period and an exposure period. One or more conduction voltages are sensed while an element conducts a selected current, either during a calibration cycle or during an exposure. A correct boost current is predicted from the conduction voltage(s) based upon other parameters including column capacitance, which may be determined upon manufacture, and the predicted boost current is then applied to matrix elements.

Abstract: A method for error detection in a drive mechanism, having a multiphase electric motor and a converter connected upstream thereof, wherein the converter controls voltages of individual phases of the electric motor, and individual phase currents in the individual phases of the electric motor each extend periodically. The method includes measuring a phase current of the electric motor at a predetermined point of a respective period, simultaneously varying a voltage that is associated with the measured phase current and evaluating a measured value of the measured phase current as a function of the voltage that is associated with the measured phase current.

Abstract: A method of enhancing noise margin on digital signal lines of a system includes steps of evaluating impedances and lengths of the digital signal lines. Resonances of each digital signal line are determined, and target waveforms for each digital signal line optimized for noise margin are determined. A configuration is generated for a programmable device driver to configure the device driver to generate the waveform optimized for noise margin. An alternative embodiment selects waveforms, and corresponding configurations, from a group of possible waveforms at boot time to ensure that data is transferred with optimum noise margins. Also claimed is apparatus embodying bus drivers capable of driving a bus with a waveform approximating blended trapezoidal and sinusoidal edge shapes, this waveform being optimum for noise margin in certain systems having multidrop busses.

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract: Circuitry for providing a method (semi-analog) for normalization procedure of the Head Driver ASIC is disclosed. The circuitry utilizes current DAC's (Digital-to-Analog Converts) to adjust the amplitudes of the voltages across piezo-electric elements, based on predetermined normalization (calibration) data which are stored in separate latches (a different normalization data for each individual transducer). The transducers all receive their respective calibrated voltage values all at the same time by varying the current slope delivered to each. This method provides more simplicity and more accuracy for normalization procedure and results in better performance then using digital circuitry and digital counters.

Abstract: An inventive driver stage for driving an output on one of n-levels, which are each spaced from each other by a voltage difference of &Dgr;V, includes a plurality of field effect transistors for driving the output by supplying or removing a current to or from the output, with the relationship of the channel widths of at least two field effect transistors, which both function either to lead a current to or away, being set in dependence on the value of the voltage difference.

Abstract: Provided is a level shifter including: a first level shifter circuit having first and second transistors whose sources are applied with a power source voltage and drains are connected with gates of the other transistors, and third and fourth transistors whose gates are applied with input and inverted signals, drains are connected with the drains of the first and second transistors, and sources are grounded; and a second level shifter circuit having fifth and sixth transistors whose sources are grounded and drains are connected with gates of the other transistors, and seventh and eighth transistors whose sources are applied with the power source voltage, gates are applied with the input and inverted signals, and drains are connected with the drains of the fifth and sixth transistors, the drains of the first and fifth transistors and the drains of the second and eighth transistors being connected with each other, respectively.

Abstract: A combination of a current limiting resistor and a clamping Schottky diode prevent substantial forward biasing of a pn junction associated with a pad in a snapback device during normal operation, but do not substantially affect triggering of the device during an unbiased electrostatic discharge event.

Abstract: Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer, to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.

Abstract: The present invention relates to a logic circuit, comprising a first and a second MOS transistor wherein the two transistors are coupled to each other with the control electrodes and the drain electrodes.

Abstract: A system for determining the instantaneous amplitude (a) and phase (&phgr;) of an analog sinusoid includes a sensor which produces the analog sinusoid output in response to the measurement of a parameter, an analog-to-digital converter which receives the analog sinusoid from the sensor and converts the analog sinusoid to a digital sinusoid, a delay device which receives the digital sinusoid and produces an in-phase signal (I) associated with the digital sinusoid, a transformer which receives the digital sinusoid and produces a quadrature signal (Q) associated with the digital sinusoid by introducing a phase shift plus a delay to the digital sinusoid, an amplitude computation device which receives the in-phase (I) and quadrature (Q) signals and computes the instantaneous amplitude (a) of the digital sinusoid by processing the in-phase (I) and quadrature (Q) signals according to the equation a={square root}{square root over ((Q2+I2))} and a phase computation device which receives the in-phase (I) an

Abstract: The differential comparator circuit for receiving an input voltage within a pre-determined range, amplifying the input voltage, and outputting an output voltage is provided. The circuit includes: a first differential comparator for receiving the input voltage within a first range portion of the range, amplifying the input voltage within the first range portion, and outputting the output voltage, a detecting circuit electrically connected to the first differential comparator, wherein a trigger signal is produced by the detecting circuit when the first differential comparator is shut down and is detected by the detecting circuit, and a second differential comparator electrically connected to the detecting circuit for receiving the input voltage within a second range portion of the range, amplifying the input voltage within the second range portion, and outputting the output voltage in response to the trigger signal.

Abstract: An input circuit in a DRAM includes a differential amplifier circuit amplifying a potential difference between a potential of an input signal and a reference potential, an inverter outputting an inversion signal of an output signal of the differential amplifier circuit, a latch circuit holding an output signal in a preceding cycle, and two resistive elements for switching the reference potential in accordance with an output signal of the latch circuit. Thus, the reference potential is switched in accordance with the logic level of the input signal in the preceding cycle, allowing accurate determination of the logic level of the input signal.

Abstract: An integrated circuit with a power and ground distribution system having a first conductive layer, a second conductive layer, and an insulating layer disposed between the first layer and the second layer. A first ring is formed in the first layer, where the first ring forms a first loop around a peripheral portion of the integrated circuit. First straps are formed in the first layer, where the first straps have connections to the first ring. First horizontal members are formed in the first layer, where the first horizontal members have connections to the first ring. Second horizontal members are formed in the first layer, where the second horizontal members do not have connections to the first ring. A second ring is formed in the second layer, where the second ring forms a second loop around the peripheral portion of the integrated circuit. The second ring is interleaved with the first ring. Second straps are formed in the second layer, where the second straps have connections to the second ring.

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN)

Abstract: A direct conversion type of frequency transposition device includes a transconductor block receiving the input signal and a current switching block connected to the output from the device. At least the common mode (Iif1+Iif2) is servocontrolled to static output currents from the frequency transposition device on a current proportional to a reference current (Iref) and independent of the static output currents from the transconductor block.

Abstract: The present invention comprises an integral triangular voltage waveform generator (170, 180) and triangular to pseudo-sinusoidal current waveform converter (170, 180). The outputs of the present invention are preferably differential (130, 131), although the invention can easily be modified for single ended output. The frequency of the output waveforms corresponds to the frequency of the input reference clock.

Abstract: A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals maybe removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift.

Abstract: A capacitive charge pump that can be implemented in such devices as e.g. a phase locked loop (PLL). The charge pump includes at least one capacitor in the charge path and discharge path for limiting the amount of charge provided to or removed from a filter capacitor of a PLL. In one example, a second capacitor may be provided in the charge path or discharge path to reduce the capacitance (if provided in series) or increase the capacitance (if provided in parallel) to adjust the maximum amount of charge transferred to a filter capacitor. In one example, multiple capacitive stages may be implemented in parallel to increase the maximum amount of charge transferred to a filter capacitor. Each stage is enabled after a delayed period of time from when the previous stage was enabled.

Abstract: A dual signal path provides enhanced noise cancellation for phase locked loop applications. According to various aspects of the invention, dual charge pumps are used to split the phase locked loop signal into dual signal paths, wherein each path carries an information signal with an injected noise component. The dual signal paths are arranged to maintain the magnitude and phase characteristics of the injected noise component. Filter blocks process the signals, retaining the injected noise component. The filtered signals are coupled to the input of an adder circuit where the filtered signals are subtracted. Because each filtered signal contains the injected noise component, the subtraction operation effectively cancels the injected noise component from the filtered signals.

Abstract: The present invention is to provide a charge pump circuit for improving switching speed and compensating mismatch between a source and a sink currents flowing to output terminal. A charge pump circuit according to the first embodiment of the present invention comprises a first and second switching elements, a discharging and charging elements, a biasing unit, a first and second compensating unit, a charge pumping unit, a current mirror unit, a contol unit, and a biasing unit. The compensating circuit removes the deterioration owing to the parasitic capacitance, and the control circuit controls the charge that is flowed or emitted from the parasitic capacitance. A charge pump circuit according to the second embodiment of the present invention comprises a charge pumping unit, a current mirror unit, a contol unit a biasing unit. The charge pump circuit decects the mismatch between the output currents via the control unit, and compensates the mismatch by the biasing unit.

Abstract: The present invention provides for a register controlled delay locked loop having an acceleration mode for improving accuracy to be correspondent to an increase of the operation speed of a memory device. For this object, in the present intention, the register controlled delay locked loop includes a delay line, a delay model, a delay means, a first and a second phase comparators, a mode decision means, a shift register control means, and a shift register.

Abstract: The clock generator of this invention saves a buffer memory for the data transfer interface, which has conventionally been required, when using a spectrum spread clock in circuits and devices inside a system. The clock generator can easily be applied as the operational clock in a system, and enhances the performance of the system. In the clock generator, the variable delay circuit controls the phase of the reference clock generated by an oscillator. The delay setting circuit is able to vary the setting of the control voltage to the variable delay circuit at each clock cycle, and modulates the phase of the reference clock. The phase modulation means of the delay setting circuit fluctuates the cycle of the output modulation clock to thereby spread the spectrum.

Abstract: An IC including skew-programmable clock buffers, fixed skew logic, an external interface and a skew controller. Each skew-programmable clock buffer receives a distributed clock signal and provides a corresponding local clock signal having a programmed skew. The fixed skew logic enables permanent programming of static skew values and the external interface enables programming of dynamic skew values. The skew controller selects between the static and dynamic skew values and programs the skew-programmable clock buffers based on selected skew values. In one embodiment, the skew controller is operative to detect a skew over-ride command upon reset of the IC and to select between the static and dynamic skew values based on the skew over-ride command. The programmable memory may be integrated on the IC or externally coupled via the external interface. The fixed skew logic is implemented as any type of permanent programmable block, such as laser-blown fuses, an EPROM, etc.

Abstract: A control arrangement is operable to control an electrical relay to supply current. The arrangement comprises current supply means and control means operable to provide a relay make signal and a relay break signal to control the state of the relay to respectively make and break a connection to the current supply means. Further control means are operable to enable or disable the current supply means. A first delay means operates to delay enabling the current supply means until after a relay make signal has been provided, to allow the relay to make the connection before current supply commences. Excess current is also sensed and controlled by a form of pulse-width modulation.

Abstract: Circuit for correcting a duty factor of a clock signal, including a phase comparator for detecting a phase difference of an input clock signal having a duty factor to be corrected, and a corrected clock signal having the duty factor corrected, and generating a shift control signal, a control signal generating part for shifting a clock generating reference signal in response to the shift control signal, and delaying the clock generating reference signal for a preset time period to generate 180° and 360° clock generating control signals, and a clock signal generating part for generating a clock signal having a corrected duty factor according to the 180° and 360° clock generating control signals.

Abstract: A phase shift circuit and a phase shifter are achieved which are small in size and wide in bandwidth. The phase shift circuit includes a capacitor, and a series circuit composed of a switching element which exhibits capacitivity when it is in an off-state and an inductor connected in series with this switching element, the series circuit being connected in parallel with the capacitor. The capacitor and one terminal of the series circuit are connected with a high frequency signal input/output terminal, and the other terminal thereof is connected with ground.

Abstract: For generating a delay signal, a series of source signals based on the same high frequency signal are first provided. Every adjacent two of the source signals have a phase difference of a certain clock unit therebetween. A first and a second output signals are then generated on the basis of the plurality of source signals at a first and a second time points selected as desired. The first and the second output signals are processed by a logic operation to obtain the accurate and adjustable delay signal. For obtaining the first and the second output signals, the source signals are duplicated at first, and then respectively processed in response to respective clock signals.

Abstract: Output driving circuit including at least one or more than one level shifter for receiving an input signal to be provided to an outside of an integrated circuit and shifting a voltage level of the input signal to a voltage level required at the outside of the integrated circuit while maintaining a duty ratio of the input signal constant, and an output driving unit for forwarding the input signal to the outside of the integrated circuit under the control of an output enable signal, thereby permitting application to the integrated circuit operative at a high speed, readily.

Abstract: When a set signal goes high, a gate-source voltage is stored by an input capacitor such that an NMOS transistor maintains a source potential at a drain current. Next, when a set signal goes low and a write signal goes high, the NMOS transistor performs a source-follower operation and enters a stable state while charging a load capacitor. At timing when writing into the load capacitor is finished, the set signal and the write signal are put into low states. By doing this, the writing voltage is stored by the load capacitor. At the same time, current sources are forcibly turned off and the flow of a very small amount of bias current completely stops so that no power is consumed.

Abstract: A circuit for combining on/off key and warm boot key to obtain a function of cold boot key in a portable information device is disclosed, which uses an on/off key to control a first switch circuit to be on and off and a warm boot key to control a second switch circuit to be on and off. The first switch circuit has the on/off key capable of restoring boot and halt functions. The second switch circuit has warm boot function. As the on/off key and the warm boot key are pressed at the same time, the first switch circuit and the second switch circuit are simultaneously turned on to drive a switch driving circuit to be active and thus the switch driving circuit outputs a signal to cold boot a connected portable information device.

Abstract: The invention relates to a method and to a device for switching on and off power semiconductors, especially IGBTs or power MOS-FETs with inductive load, such as are preferably used for the torque-variable operation of asynchronous machines, in ignition systems for spark ignition engines, in switched-mode power supplies or in power factor controllers. A voltage (UCE; UDS) dropping across the power semiconductor and a current (IC; ID) flowing through the power semiconductor are detected and their temporal progression during a switching operation is controlled. The temporal progression of the voltage (UCE; UDS) and the temporal progression of the current (IC; ID) are substantially controlled in a time-delayed manner.

Abstract: This invention relates to a high frequency switch circuit including a plurality of high frequency terminals (101, 102, 103) which input/output a high frequency signal, and a plurality of high frequency semiconductor switch sections (121, 122) which switch between these high frequency terminals. The plurality of high frequency semiconductor switch sections are isolated from each other in a DC state by a DC potential isolating section (131), and a DC potential opposite in level to a DC potential applied to a switching signal terminal (111, 112) arranged on the control side of each high frequency semiconductor switch section is applied to both or at least one of the input side and output side of each high frequency semiconductor switch section.

Abstract: A method and circuit for controlling fuse blow including sending signals to a plurality of fuse latches, sending fuse select signals to a blow control circuit to determine if a fuse should be blown or not, activating a delay timer after a fuse is blown to control after-blow time. After the delay timer has expired, issuing a Stop signal that causes the blow control circuit to shut off a blow device. This process continues until successful blow completion of all to-be-blown fuses.

Abstract: An embodiment of the invention is circuitry that contains a fuse 9 connected between a decoupling capacitor 4 and a power rail 11. Another embodiment of the invention is a method of eliminating defective decoupling capacitors 4 by applying power to a power rail 10 to blow a fuse 9 that is connected to a defective decoupling capacitor 4.

Abstract: A method for reducing a leakage current in an integrated circuit is provided that includes controlling one or more inputs of an integrated circuit such that one or more logic elements within the integrated circuit are set to one or more selected values. The selected values produce a minimum leakage current associated with the integrated circuit when the integrated circuit is operating in a standby mode.

Abstract: The invention includes an apparatus and a method for minimizing power supply sensitivity of a differential amplifier. The apparatus includes a current source providing a differential amplifier bias current to a common source node of the differential amplifier. A voltage sensor senses variations of a power supply associated with the current source. Variations sensed by the voltage sensor control a magnitude of the differential amplifier bias current. The method includes a current source providing the source current. A voltage potential of the common source node is sensed. The current source is adjusted depending upon the sensed voltage potential of the common source node, thereby adjusting a magnitude of the source current.

Abstract: The invention relates to an integrated circuit arrangement with an active filter comprising transconductance stages, each being adjustable by means of a bias current to be supplied, and comprising a tuning device for tuning the filter, which tuning device adjusts the bias currents of the transconductance stages, wherein the tuning device adjusts the bias current of a first transconductance stage, for the purpose of achieving a desired characteristic of this transconductance stage, and adjusts the bias current of at least one further transconductance stage such that the transconductance of this further transconductance stage deviates from the transconductance of the first transconductance stage by a certain value, wherein the bias current (0.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.