Abstract: A universal electromagnetic resonance system is aimed at detecting and measuring local non-uniformities in objects made from conductive or non-conductive materials. The system comprises a composite measuring unit composed of two identical and symmetrically arranged individual oscillation circuits with measurement elements in the form of identical and symmetrically arranged inductive coils or capacitor chips. The unit is connected to an impedance analyzer for supplying RF current and for measuring the voltage signal in the oscillation circuit. Since all the elements of individual oscillation circuits are identical, in the case of non-uniformity of the object on the scanned area, the parameters of the resonance will hanged. This change will violate the symmetry in the operation of the individual oscillation circuits. The variation in measured signal can be calibrated in terms of the target parameter or characteristic of the object.

Abstract: A method for high throughput mechanical property testing of materials libraries using capacitance. The method monitors the responses of a plurality of samples on a substrate to a force induced by a capacitor.

Abstract: A proximity switch which operates according to an inductive or capacitive action principle and contains a LC tuned circuit and a dynamically connected amplifier, and in which the approach of a suitable influencing element or article changes at least one oscillation parameter, the operating state of the amplifier being changed when the article does not reach a certain distance to the tuned circuit, the oscillation not however being interrupted with reaching the operating point. The proximity switch (1), likewise contains display elements (5) which are able to signal the presence of influence on the tuned circuit before the operating point or value of the amplifier is reached.

Abstract: A sensor array for measuring localized corrosion based on electrochemical reactions is disclosed. The sensor has an array of electrodes that are made from the material of interest. The electrodes are electrically insulated from each other and arranged so that a small area of the electrode contacts a corrosive environment. The voltage outputs across the electrodes connected to the electrodes are measured and used as the signals to indicate localized corrosion.

Abstract: A device for supporting and securing thin wafers comprising a housing having an upper shelf extending radially inwardly from the housing and a lower shelf extending radially inwardly from the upper shelf. An upper seal is disposed within the upper shelf and an inspection windowpane is disposed within the lower shelf. A vacuum is provided between the inspection windowpane and the upper seal to secure the wafer to the inspection windowpane and to secure the inspection windowpane to the housing. A ring-shaped frame assembly may further support and secure the wafer.

Abstract: A load board adapter which is removably attachable to a load board and provides removable and replaceable sockets for individual integrated circuit packages to provide an electrical connection between the integrated circuits and the circuit tester to facilitate testing of relatively small quantities of electronic devices on high volume testers. The chip sockets can be configured to hold a variety of devices such as a DIP, an SOJ, a TSOP, a ZIF, a PLCC, etc. A first set of contacts are clamped to a main adapter base which is removably securable to a load board or similar test fixture. Each contact within the first set of contacts includes a load board engagement portion which is configured to frictionally engage pad sites on the test fixture. A second portion of each contact within the first set of contacts is configured to engage an individual contact within a second set of contacts. The second contacts are electrically connected to pin receptacles on a substrate such as a printed circuit board.

Abstract: A device for testing liquid crystal display (LCD) prior to the installation of a drive chip is provided. The device at least includes a testing platform, a slope adjusting device, and a height adjusting device, wherein the slope adjusting device is used to adjust the slope of the testing platform while the height adjusting device is used to adjust the height of the testing platform. The testing platform is further equipped with rectangular fasteners with which the LCD can be fastened and a signal outputting device. The signal outputting device has a horizontal shifter which is fixed onto the testing platform, a vertical shifter which is coupled to the horizontal shifter, and a plurality of probes which are coupled to the vertical shifter, wherein the horizontal shifter and the vertical shifter can enable these probes to move along a plane perpendicular to the testing plane.

Abstract: An apparaus is disclosed which includes a converter circuit and a noise suppression circuit. The converter circuit has a dynamic logic input, and is configured to generate a static logic output on an output node responsive to the dynamic logic input. The noise suppression circuit is coupled to receive a clock signal and is coupled to the output node. Responsive to a first phase of the clock signal, a precharge of a dynamic logic circuit generating the dynamic logic input occurs. The noise suppression circuit is configured to actively drive the static logic output on the output node responsive to the first phase. In some embodiments, the noise suppression circuit may reduce the noise sensitivity of the static logic output during the precharge phase, and may not impede operation of the converter circuit during the evaluate phase.

Abstract: An I/O circuit disposed on an integrated circuit substrate and having reduced parasitic capacitance. The I/O circuit includes a signal line segmented into a first signal line segment and a second signal line segment, and an inductive structure disposed between the first and second signal line segments. An on-chip termination element is coupled to the first signal line segment, and an electrostatic discharge (ESD) element is coupled to the second signal line segment.

Abstract: Disclosed is a configurable logic circuit that includes at least 6 inputs and at least two outputs. The configurable logic element can carry out only a subset of all 6-input logic functions and, thus, requires a substantially smaller silicon area than a 6-LUT that can perform all 6-input logic functions. Also, the configurable logic circuit can be configured such that a first subset of the inputs drive one of the outputs and a second subset of the inputs drive another output.

Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

Abstract: A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an output of the testable, prechargeable circuit to be in a low state when the clock signal is low. The timing circuit also causes the output of the circuit to be timed with a state change in the clock signal to provide a domino logic output signal. Either a data signal or a test signal are multiplexed to the input of the driving circuit to produce respectively the domino logic output signal or a test output signal. A static logic circuit receives the test output signal to produce a test signal output.

Abstract: A signal-level converter is provided between a first terminal and a second terminal. The first terminal is connected to a first logic circuit operating at a first supply voltage higher than a given reference voltage. The second terminal is connected to a second logic circuit operating at a second supply voltage higher than the first supply voltage. The signal-level converter has a switching transistor that forms a current passage between the first and the second terminals in response to a control signal supplied to a gate of the switching transistor and a bus-hold circuitry, provided between the switching transistor and either the first or the second terminal as the output terminal, the other being the input terminal, and configured to convert a voltage level of a signal transferred via the switching transistor into another voltage level at the output terminal. The bus-hold circuitry may have two bus-hold circuits between the input and the output terminals, for two-way signal transfer.

Abstract: To output a digital signal in particular according to the LVDS (low voltage differential signalling) standard, a driver stage is supplied with a constant current and thus supplies the digital signal in the form of a current signal with defined current values. As a result of line capacitances of a transmission line, because of the current limited according to the standard the edge steepness and hence the maximum transmittable bit rate can deteriorate. According to the invention, therefore, at least essentially in synchronization with a triggering of the driver stage, at least one current increase signal is generated which via a capacitor causes an additional current increase in the output current of the driver stage. Preferably, the current increase signal via the respective capacitor is switched directly to an output of the driver stage. By using a capacitor, with very little expenditure a limited current pulse can be switched in a temporally targeted manner on the switching processes of the driver stage.

Abstract: An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of (and evenly spaces) the power switches according to the size of the serviceable area to which each of the power switches can provide power. The size of the power switches are matched to the current and voltage that will be provided by the power buses. The size of the serviceable area to which each of the power switches can provide power is dependent upon the size of the power switches.

Abstract: A sense amplifier has a pair of internal nodes that are precharged to a power-supply level. A first pair of n-channel transistors supplies current to the internal nodes responsive to a pair of data signals, both of which are initially high. When one of the data signals begins falling toward the low level, the corresponding n-channel transistor immediately reduces the current supplied to one of the internal nodes. A second pair of n-channel transistors, cross-coupled to the internal nodes, amplifies the resulting potential difference between the internal nodes, thereby pulling down the potential of one of the internal nodes. An output signal is generated from one or both of the internal nodes. The output signal is obtained quickly, because amplification begins without delay.

Abstract: Methods and systems for sensing load conditions and for adjusting output current drive according to the sensed load conditions to maintain one or more signal characteristics within a desired range. Load conditions are sensed by monitoring one or more signal characteristics that are affected by load conditions, such as voltage changes with respect to time. Output current drive is then adjusted, as needed, to maintain the one or more desired signal characteristics. In an embodiment, rising and/or falling edge slopes are monitored. For example, a dV/dt may be monitored. The dV/dt can be monitored by coupling a capacitance to the output signal, generating a current with the capacitance, and generating a voltage from the current. The voltage is generally proportional to the dV/dt. Depending upon the load conditions, a supplemental current is generated and/or adjusted and added to the output signal to maintain the desired signal characteristics within a desired range.

Abstract: A digital frequency synthesizer (DFS) circuit adds little additional delay on the clock path. True and complement versions of an input clock signal are provided to a first and second passgates, respectively. Under the direction of a control circuit, the passgates pass selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the DFS circuit. When neither the true nor the complement clock signal is passed, a keeper circuit retains the value already present at the output clock terminal. In some embodiments, both passgates can be disabled and a ground or power high signal can be applied to the output terminal. Other embodiments include PLDs in which the DFS circuits are employed to allow individual clock control for each programmable logic block.

Abstract: Systems and methods for providing frequency compensation over a wide range of frequency drift are shown. The preferred embodiment utilizes a sweep mode function to provide frequency compensation over a range of frequency drift broader than the frequency drift accommodated by a phase lock loop, without increasing the noise characteristics of the phase lock loop. Accordingly, the preferred embodiment operates in a phase lock loop mode while frequency drift can be compensated for by the lock range of the phase lock loop circuitry. The preferred embodiment operates in sweep mode to step through a range of offset frequencies to position the phase lock loop mode where frequency drift can be compensated for by the lock range of phase lock loop circuitry. Additionally, a preferred embodiment of the present invention includes a drift mode in order to monitor frequency offset information, such as may be used in performing sweep mode functions and/or other control or management functions.

Abstract: An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generate a delay locked internal clock signal having a corrected duty cycle based on the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs.

Abstract: A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 &mgr;m CMOS technology.

Abstract: A pulse generator circuit includes a first logic means, a second logic means, a first delay means, and a second delay means. The first logic means is for receiving an input clock signal. The first delay means is for delaying the input clock signal by a first delay time. The second logic means is for receiving a signal output from the first logic means. The second delay means is for delaying the signal output from the first logic means by a second delay time.

Abstract: A differential input receiver with hysteresis on both sides of the reference voltage may include a two-input, one-output differential amplifier including two input transistors having a common terminal connected together. The control terminal of each transistor may be connected to one of the inputs of the differential amplifier. The output of the differential amplifier may be connected to a set of cascaded digital inverters/buffers, and an output of each digital buffer may be connected to the control terminal of a feedback transistor. The feedback transistor may be connected in parallel across each of the input transistors so that when one input voltage increases above or decreases below the input voltage at the second input by a predetermined threshold value, the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.

Abstract: Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.

Abstract: A step-up circuit is equipped with a step-up clock signal generation device that generates a clock signal to be used for stepping up voltage, a plurality of step-up stages for successively stepping up a power supply voltage based on the clock signal, and control devices that controls, after starting an operation, the stepped up clock signal generated by the step-up clock signal generation device to be supplied to the plurality of step-up stages at different timings.

Abstract: A gate driver includes a control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch. The gate control signal generator is provided proximate a high side of the gate driver. A first sub-circuit has a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay. A comparator is configured to receive signals from the high side. The comparator is provided proximate a low side of the gate driver.

Abstract: In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit.

Abstract: A multiplier circuit with a multiplier core with two cross-coupled transistor pairs (2, 3; 4, 5) is specified, wherein a first and a second signal source (10, 11, 13, 14), which are driven by a first and, respectively, second signal to be multiplied, are in each case connected to control inputs of the transistors (2 to 5) of the multiplier core for diversion between the transistor pairs (2, 3; 4, 5) or, respectively, differentially between the transistors (2, 4; 3, 5) of the differential amplifiers. Due to the high degree of symmetry which can be achieved at the input gates of the circuit, a particularly precise multiplication with good linearity is possible. The multiplier described can be used, for example, as radio-frequency mixer circuit or as 90° phase detector circuit.

Abstract: A multiplexer containing multiple cells sharing a common output line. The cells select one of multiple input bits. The output line is first charged to a first logical value (e.g., 0), and one of the cells drives the output line to a second logical value (1) if the corresponding input bit does not equal the first logical value. The remaining cells may not affect the output line. Due to such an implementation, the number of transistors may be reduced.

Abstract: A bias generator adjustment system adjusts a PLL or DLL bias generator dependent on negative bias temperature instability effects in an integrated circuit. The bias generator adjustment system uses an aging independent reference circuit and a bias circuit to operatively adjust a bias generator such that transistor ‘aging’ effects that occur over the lifetime of an integrated circuit are compensated for or corrected.

Abstract: Charging a storage cell requires the electromotive force exerted at a photogenerating cell in addition to the voltage equal to or higher than the forward on voltage developed at an backflow preventing diode. Therefore, the charging is inefficient. Moreover, the area of the backflow preventing diode must be large in consideration for a current supply from the photogenerating cell at a high intensity of illumination.

Abstract: A digital circuit which can operate normally regardless of binary potentials of an input signal is provided. A semiconductor device comprising a correcting unit and one or a plurality of circuit elements, the correcting unit including a first capacitor, a second capacitor, a first switch, and a second switch, wherein the first electrode of the first capacitor is connected to an input terminal, the supply of a first potential to the second electrode of the first capacitor is controlled by the first switch, the supply of a second potential to the second electrode of the second capacitor is controlled by the second switch, and a potential of the second electrode of the first capacitor or a potential of the second electrode of the second capacitor is supplied to the one or the plurality of circuit elements.

Abstract: A multiphase charge pump including first and second phase charge pump circuits. Each of the first and second phase charge pump circuits includes a bootstrap capacitor. The bootstrap capacitors are switchingly connected by an equalization circuit that periodically transfers charge from a discharging capacitor to a charging capacitor, thereby reducing the charge that must be externally supplied to charge the charging capacitor.

Abstract: A bandgap reference voltage generator includes, in part, a first closed-loop circuit having a first operational amplifier and adapted to generate a first current with a positive temperature coefficient and a second closed-loop circuit having a second operational amplifier and adapted to generate a second current with a negative temperature coefficient. The bandgap reference voltage generator is further adapted to include a multitude of output stages. Each output stage may be independently scaled to sum any selected multiple of the first current to any selected multiple of the second current to generate an output voltage having either a nearly zero, a positive or a negative temperature coefficient. For example, the first output stage may be scaled to generate a reference output voltage with a nearly zero temperature coefficient. Similarly, the second output stage may be scaled to generate a reference output voltage with a negative temperature coefficient.

Abstract: An internal voltage generator of a semiconductor device features a tuning unit, a characteristic controller and an internal voltage generator. The tuning unit receives a test mode signal, an external signal and a signal stored in an internal setup device, and outputs a control signal. The characteristic controller receives the control signal, and outputs a characteristic controlling signal. The internal voltage generator receives a reference input signal and the characteristic controlling signal, and controls a characteristic of an internal voltage.

Abstract: An active filter circuit for removing high frequency noise from an input signal, particularly RF noise from an ECG signal, has an active first circuit having an input and an output, an RC-filter network arranged in electrical connection with the input and a second circuit connected in a positive feedback loop with the RC-filter network and adapted to reduce high frequency signals at an output of the first active circuit.

Abstract: A circuit for correcting the offset of an amplification and filtering chain having a predetermined gain and cut-off frequency depending on the value of at least one capacitor, comprising: a correction means for subtracting from the chain input a correction signal depending on the value of a programmable digital word; a digital automaton for, in a setting phase, searching, then memorizing one of two consecutive values of the digital word between which the output signal of the chain switches sign, the input signal being canceled during a setting phase; and comprising a means for, during the setting phase, reducing the value of said at least one capacitor with respect to its normal operating value.

Abstract: The present invention provides a novel feed forward amplifier (“FFA”) and a pilot tone generator-receiver therefor. In an embodiment of the invention, the feed forward amplifier only requires a single oscillator to operate both the pilot tone generator and pilot tone receiver used in conjunction with the amplifier circuitry of the FFA. In another embodiment of the invention, a method is provided of generating and detecting a pilot tone from a single oscillating signal.

Abstract: A signal processing module provides high-gain amplification of received signals, while canceling some or all low-frequency error in the received signal. The signal processing module includes a multi-stage amplification series and a low-frequency error cancellation feedback loop.

Abstract: The invention is a dual band power amplifier with a small footprint having excellent band-to-band isolation. An improved second and fourth harmonic trap at the output of the low band power amplifier comprises a first capacitance shunted to ground placed in series with an inductance, the inductance preferably in the form of a transmission line of predetermined length, and a second capacitance coupled between an intermediate point of the transmission line inductance and ground. Band-to-band isolation can be additively increased by further forming a ground loop between the outputs of the two power amplifiers. The ground loop further isolates the high band amplifier from the low band amplifier by causing the magnetic fields generated around the output wire bonds of the low band power amplifier to set up circulating currents primarily in the ground loop, rather than coupling into the output wire bonds of the high band power amplifier.

Abstract: A polynomial predistorter and predistorting method for predistorting a complex modulated baseband signal are provided. In the polynomial predistorter, a first complex multiplier generates first complex predistortion gains, using a current input signal and complex polynomial coefficients modeled on the inverse non-linear distortion characteristic of the power amplifier, and multiplies them by I and Q signal components of the current input signal, respectively. At least one second complex multiplier generates second complex predistortion gains using the complex polynomial coefficients and previous predistorted signals and multiplies them by I and Q signal components of the previous predistorted signals, respectively. A summer sums the outputs of the first and second complex multipliers and outputs the sum as a predistorted signal to the power amplifier.

Abstract: A radio frequency (RF) driver amplifier system and method that provides linear in decibel gain control is provided. The RF driver amplifier system comprises a linear transconductor receiving an input voltage and providing a controlled current based on input voltage received, temperature compensation circuitry for varying current from the linear transconductor according to absolute temperature, an exponential current controller receiving current varied according to temperature and providing an exponential current in response, and an inductive degeneration compensator receiving exponential current and providing a control current to driver amplifier circuitry, thereby compensating for inductive degeneration due to at least one inductor in the driver amplifier circuitry. Control current passes from the inductive degeneration compensator to the driver amplifier circuitry. Output gain from the driver amplifier circuitry varies linearly in decibels with respect to the input voltage.

Abstract: In a circuit according to the present invention, a multi-collector transistor is provided which includes first to third collectors so that, when a current does not flow from the second collector, a current from the first collector increases but a current from the third collector does not vary. When transistors of the circuit turn off because the voltage of an input signal gets out of an in-phase input voltage range, the supply of the current from the second collector comes to a stop and, hence, the current from the first collector increases. In this situation, further transistors carry out their on/off operations, thereby fixing the output of the circuit to a low level. That is, this circuit can, irrespective of poor pair compatibility between the transistors, fix the output logical level to a desired level when the voltage of an input signal gets out of an in-phase input voltage range.

Abstract: A low noise amplifier topology includes a dual gate transistor device, such as a HEMT device and employs resistive feedback with a DC block associated with the amplifier output to provide a desired high voltage gain and a low noise figure over a desired range of frequencies.

Abstract: A power amplifier system having a high frequency power amplifier circuit section 10 employing as its amplifying elements source-grounded enhancement type n-channel MESFETs J1, J2 for receiving a drain bias voltage Vdd and a gate bias voltage Vgg of zero volts or positive low potentials as supplied from a unipolar power supply and for amplifying an input signal superposed therewith to thereby output an amplified signal indicative of a change in drain currents Id1, Id2, an output matching circuit section 11 for applying impedance matching to such amplified high frequency signal and then outputting the resultant signal, and a gate bias voltage circuit section 12 for supplying a gate bias voltage to the high frequency power amplifier circuit is disclosed along with a mobile communications terminal device including the system, wherein the MESFETs J1, J2 are such that in cases where a forward direct current (DC) gate voltage is applied to a gate terminal with a source terminal coupled to the ground, the DC gate vol

Abstract: A high-frequency circuit comprises a substrate having an electronic component on an obverse side thereof, a first ground pattern formed on almost an entire reverse side of the substrate, a microstrip line formed on the obverse side of the substrate, and a bias line connected to the electronic component on the obverse side of the substrate and formed continuously on the obverse side and the reverse side of the substrate so as to cross the microstrip line on the reverse side of the substrate in plan view so as to supply a bias voltage to the electronic component, wherein the first ground pattern is formed so as to circumvent the bias line formed on the reverse side of the substrate, a portion of the first ground pattern that circumvents the bias line on the reverse side of the substrate is continuously formed on the obverse side of the substrate as a second ground pattern so as to divide the microstrip line in two parts, and a chip jumper is arranged to bridge the two divided parts of the microstrip line over t

Abstract: A transimpedance amplifier having a voltage amplifier and a feedback circuit coupled to an input terminal and an output terminal of the voltage amplifier. The feedback circuit includes an impedance element in parallel with a feedback resistive network. The feedback resistive network has a fixed effective resistance value. The feedback resistive network may have a first resistive element disposed between the input terminal of the voltage amplifier and a node, a second resistive element disposed between the output terminal of the voltage amplifier and the node, and a third resistive element disposed between the node and a ground terminal. Various systems utilizing a transimpedance amplifier consistent with the invention, including an optical communication system are also provided.

Abstract: An oscillation circuit comprises a plurality of constant current supplies for outputting a constant current according to a voltage supplied from a control current terminal; a plurality of switching elements which are charged or discharged by the constant current outputted from the constant current supplies and are turned on or off when exceeding a predetermined threshold voltage; and restriction elements for restricting a charging target voltage or a discharging target voltage at nodes between the constant current supplies and the switching elements to a constant value.

Abstract: A PLL (Phase-Locked Loop)-controlled oscillator has a temperature-compensated crystal oscillator having a quartz crystal unit, an oscillating circuit connected to the crystal unit, and a temperature compensating mechanism for generating a temperature compensating voltage for compensating for frequency vs. temperature characteristics of the crystal unit, and a voltage-controlled oscillator having an LC oscillating circuit, for being controlled by a PLL using the temperature-compensated crystal oscillator as a reference signal source. The temperature-compensated crystal oscillator has circuit components except for the crystal unit, the circuit components and the voltage-controlled oscillator being integrated in a one-chip IC. The one-chip IC and the crystal unit are integrally combined with each other in the PLL-controlled oscillator.

Abstract: A piezoelectric oscillator using zinc oxide as a piezoelectric plate which eliminates unwanted resonance called inharmonic overtone by optimizing ratio Le/H of driving electrode length Le to oscillator thickness H. Ratio Le/H is set between 4 and 100 in the piezoelectric oscillator polarized in a thickness direction of a piezoelectric plate and using thickness extension vibration as main vibration or the piezoelectric oscillator polarized in a length direction of the piezoelectric plate and using thickness shear vibration as main vibration. This achieves stable characteristic because no unwanted resonance exists between the resonance frequency and anti-resonance frequency of the main vibration.