Abstract: The present invention provides a clock signal input circuit that is able to provide inverse internal clock signals generated by the same input buffer as the address and data signals which exhibit reduced skew. When a skewed external noninverse clock signal and a corresponding external inverse clock signal are passed through respective reference voltage input buffers there is no reduction in skew between the two internal signals. In a preferred embodiment, the invention provides back to back inverters connected to both lines carrying the noninverted and inverted internal clock signals. The slower internal clock signal has an extra inverter driving it when it switches states and the faster internal clock signal has an extra inverter fighting it when it switches states. The skew of the two signals is reduced, allowing for faster operation of the integrated circuit and a reduction in misread data signals.

Abstract: A power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is applied to a multiplier, which generates a squared difference. The squared difference is smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage, either explicitly or implicitly, to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The multiplier can be implemented with a Gilbert cell, while a filter-comparator converts the differential Gilbert-cell output to a single-ended signal and filters the signal. The reference voltage compared can be set by the switching threshold of the filter comparator or other logic gates. A complementary Gilbert cell and filter-comparator can be used to increase the operating range.

Abstract: An active cascode differential latch for providing a logic output signal indicative of whether or not a first current is greater than a second current. The first and second currents are fed into two input ports of the active cascode differential latch. The active cascode differential latch has a relatively small input impedance, and has utility for comparators and discrete-time analog filters, to name just a few, particularly when used in high bandwidth and low voltage applications.

Abstract: As a power-supply voltage VCC is applied to a second terminal, a latch is reset by a reset signal POR from a power-on reset unit. Subsequently, as the voltage of a signal IN applied to a first terminal is increased to higher than the voltage VCC by a threshold voltage Vth of a PMOS 11, the PMOS 11 turns on, causing a node N1 to become “H.” Thus, a test mode is set in the latch. Subsequently, even if the signal IN is reduced to VCC or lower, the test mode is maintained. A high-voltage test can be conducted by increasing the power-supply voltage at the second terminal, thereby eliminating the need for applying the first terminal with a higher voltage than required to set the test mode. It is therefore possible to prevent a gate oxide film of a buffer from being destroyed.

Abstract: A hold cell implementing a closed-loop, common mode negative feedback method is provided. The hold cell enables generation of an accurate constant output voltage regardless of temperature-dependent leakage currents associated with parasitic diodes and non-ideal devices. The accurate constant output voltage provided by the hold cell is used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal is used to maintain long-term timing accuracy in host devices during sleep modes of operation. Incorporation of the hold cell in a low power oscillator is fully implementable in a CMOS process.

Abstract: The DC to DC converter has an oscillator and generates an output voltage to drive a system. The modulation frequency is used for modulating a pulse width modulation (PWM) circuit in the DC to DC converter. The method includes steps of: 1. providing the modulation frequency from the oscillator; 2. switching the source of the modulation frequency from the oscillator to the system clock to provide the modulation frequency when the system is driven by the output voltage from the DC to DC converter; and 3. stopping the oscillator for reducing a power loss.

Abstract: Circuit interconnect communication circuitry dual edge triggered latching circuits transmit two data signals over a common interconnect line during one clock cycle; on signal is transmitted during each phase of a system clock over the common interconnect line. The latching circuits may be flip-flop circuits. A repeater circuit may have dual edge triggered flip-flop circuits for repeating the common interconnect line signal on a second common interconnect line. A receiver, including dual edge triggered latching circuitry, decodes the combined incoming data signals into separate outgoing data signals.

Abstract: A circuit arrangement for an LVDS driver, which uses combined bipolar and MOSFET technology with at least two MOSFETs, is shown, wherein a multiplier circuit is connected to an output stage of the LVDS driver and the multiplier circuit is controlled by means of an automatic control circuit, which generates control signals for controlling a current source of the multiplier circuit and for controlling the amplification factor of differential input signals of the multiplier circuit. Advantages of the invention are that it enables said technology, in which semi-conductor components are used in bipolar techniques (e.g. NPN and/or PNP transistors) (as well as MOS technology), to take advantage of the high speed of the bipolar elements compared with MOS elements.

Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.

Abstract: A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

Abstract: The present invention discloses a universal clock generator, which comprises a high frequency clock region for generating high frequency clocks and a low frequency clock region for generating high frequency clocks. The low frequency clock region includes at least one delay lock loop for increasing the number of high frequency clocks of the high frequency clock region. When the number of high frequency clocks (such as a CPU clock, SDRAM clock, AGP clock and PCI clock) is not enough, the delay lock loop of the low frequency clock region can be cascaded to support insufficient clocks.

Abstract: A delay locked loop having improved synchronization times has a variably adjustable delay line which accepts two incoming clock pulses. As each pulse propagates through the delay line an edge of the pulse toggles or retoggles a shift bit corresponding to a delay element. When the first pulse reaches the end of the delay line, the status of the shift bits is frozen, and a starting point for a synchronization sequence begins at the transition point between toggled and retoggled shift bits.

Abstract: A method to reduce clock noise in a multiple clock circuit is achieved. The method comprises, first, providing a periodic signal. Next, a first clock signal is provided having a frequency that is a constant multiple of the frequency of the periodic signal. Finally, a second clock signal is derived from the periodic signal. The second clock signal has a frequency that is a non-constant multiple of the periodic signal frequency. The non-constant multiple comprises the sum of a constant value plus a time-varying value. The spectral energy at the sum and difference frequencies of the first and second clock signals is reduced by frequency distribution spreading. A circuit is achieved comprising the above method.

Abstract: The invention describes a method for reducing the leakage current in thin gate dielectric MOS capacitors in integrated circuits. A bias voltage is determined for the MOS capacitor such that the capacitor area and leakage current constraints are satisfied. The MOS capacitor is not biased in inversion.

Abstract: A delay adjustment circuit for a delay locked loop, comprises a delay rough adjustment circuit unit (to which input clock signal CLK-IN, and delay control signals A1 to A6 are transmitted) for selectively obtaining outputs of roughly adjusted delays A and B of two systems having a delay difference indicating a maximum delay value of fine interval delay quantity adjustment from selected ones of selection circuits S1, S3 and S5 of an odd-number stage and selection circuits S2, S4 and S6 of an even-number stage connected to delay elements D1 to D3. Furthermore, a delay fine adjustment circuit unit (to which delay control signals B1 to B4, and enable signal ENABLE are transmitted) including delay elements FA and FB for receiving outputs of roughly adjusted delays A and B, and selectively carrying out fine interval delay quantity adjustments of the two systems by opposite operations.

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

Abstract: A feedback latch circuit includes a first logic OR gate for performing a logic OR operation upon a clock input signal and a latch output, a first logic AND gate for performing a logic AND operation upon output of the first logic OR gate and a data input signal, a second logic AND gate for performing a logic AND operation upon a complementary clock input signal and the latch output, and a second logic OR gate for performing a logic OR operation upon outputs of the first and second logic AND gates to result in the latch output that is provided to the first logic OR gate and the second logic AND gate. The complementary clock input signal received by the second logic AND gate complements the clock input signal received by the first logic OR gate.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: According to the present invention, a variable delay circuit includes a delay circuit unit group, a control unit and an offset delay amount memory group. The delay circuit unit group includes a plurality of delay circuit units, and the plurality of delay circuit units includes two paths having different delay amounts. The offset delay amount memory group includes a plurality of offset delay amount memories, and offset delay amounts corresponding to delay amounts of the first paths of the corresponding delay circuit units are set in the plurality of offset delay amount memories. The control unit includes a plurality of subtracting units, and the plurality of subtracting units select paths of the delay circuit units through which an input signal may pass by using a delay setting value and offset delay amounts. It is possible to reduce volume of the circuit and remove a table since the path is selected by calculation.

Abstract: In an exemplary embodiment, a system (10) is formed to include a semiconductor device (11) that is formed to function as a voltage regulator. The semiconductor device (11) is formed to have a control loop that includes an amplifier (30) and a feedback transistor (19) that provide a small signal AC gain that varies inversely to a load current of an output transistor (12) in order compensate for the manner in which the output transistor (12) transconductance depends on the load current flowing through the output transistor (12).

Abstract: In a CMOS level shifting circuit including N-channel transistors that have sources to which a digital signal is supplied, a bias voltage Vref is supplied to gates of the N-channel transistors, and the bias voltage Vref is set to be higher than a high level voltage of the digital signal and lower than a value obtained by adding a threshold voltage of the N-channel transistors to the high level voltage of the digital signal. Thus, a level shifting circuit is provided that is capable of outputting a signal having subjected to stable level conversion, even when a voltage level of a low voltage signal is lowered.

Abstract: A signal level shift circuit is provided for different circuit systems operating based on different supply voltages (VDDL, VDDH), wherein a supply voltage detection circuit detects a reduction of a first supply voltage (VDDL) regarding an input signal (IN). A level shift circuit comprises a load circuit portion consisting of PMOS transistors and a drive circuit portion consisting of NMOS transistors, all of which are connected together to form current paths. A switch circuit arranged for the current paths opens when a reduction is detected in the first supply voltage so that both the NMOS transistors are turned on. Thus, it is possible to effectively avoid occurrence of through currents flowing in the level shift circuit. The level shift circuit is followed by a flip-flop, which provides an output signal (OUT) in conformity with a second supply voltage (VDDH).

Abstract: An anti-jitter circuit has an integrator storage capacitor. A charge pump derives from an input pulse train at least one charge packet during each cycle of the input pulse train and supplies the charge packets to the storage capacitor. A controlled current sink operating in conjunction with a high impedance low pass filter continuously discharges the storage capacitor to create a sawtooth voltage waveform having a mean d.c. voltage level. A differential comparator compares the sawtooth voltage waveform with the mean d.c.

Abstract: Power supply sequencing systems and methods are disclosed. In one embodiment, a programmable charge pump supplies a programmable current source, which drives an external NFET that controls whether power is supplied to a device or a portion of circuitry. The maximum voltage and the turn-on ramp rate supplied to the NFET are programmable and, therefore, the NFET can be operated safely within its rated limits without requiring external protection devices. If a high-voltage output terminal is not required to drive an external NFET, the output terminal, in accordance with another embodiment, may be configured to function as an open drain logic output terminal.

Abstract: The present invention relates to a boost circuit. A precharge voltage of a positive voltage applied to a capacitor is constantly applied regardless of the power supply voltage, so that the pumping voltage is constantly and stably generated. The operating characteristic and reliability of the circuit can be improved.

Abstract: A circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (Vct) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control tern connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as Vct.

Abstract: A constant current circuit delivering a constant current to a load connected between first and second output terminals comprises, a reference current generator configured to generate a reference current, a current mirror circuit configured to amplify the reference current, an output transistor configured to deliver the constant current based on an output of the current mirror circuit, a signal source configured to deliver a pulse control signal, an auxiliary switching circuit having a switch terminal configured to deliver a switch signal in response to the pulse control signal, and a discharge terminal configured to deliver a discharge signal to the current mirror circuit when the switch signal is stopped; and a switch circuit configured to turn off the output transistor with receiving the switch signal.

Abstract: A data token with extended operational lifetime incorporates operational circuitry requiring D.C. power, a battery for supplying D.C. power to the circuitry, a power switch coupled between the battery and the circuitry, and a frequency selector for sensing remotely generated signals and for operating the switch when such signals are received so that D.C. power is applied to operate the circuitry only when the remotely generated signals are sensed in order to confine energy drain from the battery to only those periods when circuit operation is needed and extend the useful lifetime and range of the data token. The frequency selector is a crystal having a specific resonant frequency which only responds to remotely generated signals of the matching frequency. The switch is an FET switch. An integrator circuit is coupled between the frequency selector and the FET switch to smooth the D.C. voltage developed by the crystal.

Abstract: A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter, an active current mirror, and a current multiplier to provide a current signal indicative of a weighted sampled voltage signal. The current signals from the filter taps are summed by one or more active cascode differential latches to provide an output logic signal indicative of the filtered output. The discrete-time analog filter finds applications in channel equalization, and is suitable for high data rates and low voltage applications. The voltage and current signals may be differential. The voltage-to-current converter may include a common-mode high-pass filter to reject common-mode voltage variations.

Abstract: A frequency-tuning loop of the invention used in the Transconductor-Capacitor filter is composed of: a first switching device and a second switching device, both having two signal-inputting ends and two signal-outputting ends for switching the output of two signals alternately from two signal-outputting ends according to a fixed clock signal. A transconductor's inputting ends linking to the two signal-outputting ends of said first switching device. One end of a first switch linking to the positive outputting end of the transconductor and the other end linking to the first capacitor and a signal-inputting end of the second switching device. One end of a second switch linking to the negative outputting end of the transconductor and the other end linking to the second capacitor and another signal-inputting end of the second switching device; and a integrated circuit composed of an integrator, a third capacitor, and a fourth capacitor.

Abstract: A Gm-C filter includes a filter passing an intended signal SI# in an input signal SI, and a control signal producing portion detecting a peak voltage value of an output signal of a filter to be controlled and a peak voltage value of the intended signal SI#, and making a comparison between them to produce a gain control signal CS for controlling a gain, and corrects a gain loss in the filter by applying the gain control signal CS to the filter.

Abstract: A filter (3) is described, which filter is provided with field effect (FET) capacitors (M1-32; M′1-32) arranged for controlling their respective capacity values, each such FET capacitor (M1-32; M′1-32) having a source (S) and a drain (D). The source (S) and the drain (D) of each FET capacitor (M1-32; M′1-32) are coupled to one another. The filter acting as an impedance transformer is a passive low power consuming and tunable filter, such as for a radio frequency (RF) receiver. It occupies only a very small area, while integrated on chip.

Abstract: RF filter circuits are described which include a bottom dielectric substrate fabricated of a high dielectric material having a relative dielectric constant in a range of 30 to 100. A conductor pattern defining a circuit topology is fabricated on a surface of the substrate.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: The integrating circuit of the triangular wave generating circuit includes an operational amplifier and a capacitor. Switch elements are alternatively turned ON and capacitors are alternatively recharged by the currents flowing in constant-current circuits thus obtaining a triangular wave on an output terminal. In this practice, when the voltage on the output terminal reaches ±1 V, comparator circuits (41, 42) and a flip-flop including NAND gates change over the switch elements. The currents flowing in the constant-current circuits are controlled depending on the current flowing in a load circuit. The current flowing in the load circuit is controlled by a PLL circuit including a phase comparator circuit, a loop filter, an LPF, an operational amplifier and an FET. This provides an output triangular wave having the same frequency as a clock pulse (CK).

Abstract: The present invention relates to a power servo-loop in particular for controlling a power amplifier, the loop comprising a detection circuit (100) having coupling means (1) for taking off RF signals, and a detection unit (400) for delivering a detection signal (Vdet) partially representative of a first RF signal taken off by the coupling means. The detection circuit of the invention comprises, between the coupling means and the detection unit, detection control means (21, 22, 4) for substantially eliminating an “interfering” second RF signal also taken off by the coupling means, such that the detection signal is entirely representative of the first RF signal.

Abstract: A power amplifier having a first stage amplifier and a second stage amplifier, each stage of the power amplifier being configured in one of at least two power states based on a desired power output. When the first and second stages are configured in a first state, the power amplifier delivers efficient amplification in a first output power range and, when the first and second stages are configured in a second state, the power amplifier delivers efficient amplification in a second output power range. By configuring each stage in one of at least two states, a high level of power efficiency can be achieved for a broad range of power levels.

Abstract: An amplifier system is disclosed. The amplifier system includes a first amplifier, a second amplifier, and a phase noise suppression circuit. The first amplifier includes an input signal terminal and an output signal terminal. The second amplifier includes an input signal terminal and an output signal terminal. The input signal terminal of the second amplifier is coupled to the output signal terminal of the first amplifier. The phase noise suppression circuit includes first and second input terminals and an output terminal. The first input terminal of the phase noise suppression circuit is coupled to the input signal terminal of the first amplifier. The second input terminal of the phase noise suppression circuit is coupled to the output signal terminal of the second amplifier. The output terminal of the phase noise suppression circuit is coupled to the first amplifier.

Abstract: (Object) It was difficult for a feedforward amplifier to perform stable and high-speed distortion compensation control. (Constitution) It is a feedforward amplifier having CPL1 of dividing an input carrier signal into two output signals, VAP1 of adjusting one of the two divided output signals, AMP1 of amplifying the adjusted one of the output signals to generate an amplification signal, CPL2 of extracting a distortion signal by utilizing the other output signal of the two divided output signals and the generated amplification signal, CPL3 of generating an output carrier signal by utilizing the generated amplification signal and the extracted distortion signal, and CNT1 having a log amplifier of controlling VAP1 based on the other output signal and the generated amplification signal.

Abstract: A feedforward amplifier, and a method of improving the performance thereof, are provided. More particularly, a feedforward amplifier using imperfect cancellation of a main signal and a method of improving the performance thereof, in which, by including a predetermined amount of a main signal in an error signal that is input to an error signal cancellation loop of the feedforward amplifier, more error components of a final output signal are removed, such that the linearity and efficiency of the final output signal improve.

Abstract: According to the invention, the high-frequency power amplifier is characterised in that the power transistor is switched in such a way that said transistor is operated in the breakdown region and that a control loop is provided. Charge carriers that are produced is the breakdown region are carried away from an output of the operational amplifier by means of said control loop.

Abstract: An output stage for a differential amplifier is presented. If the differential amplifier is a matched current differential amplifier where the non-inverted and inverted differentials have the same current, the output stages of the present invention may provide optimum gain to the differentials in a single output voltage.

Abstract: A variable gain amplifier is configured of an amplification circuit and a control circuit controlling a gain of the amplification circuit. The amplification circuit has first and second MOS transistors identical in characteristics and having respective sources connected to a first fixed potential. The amplification circuit has a differential gain proportional to a square root of a ratio between a current flowing through the first MOS transistor and a current flowing through the second MOS transistor. The control circuit applies a potential corresponding to a constant voltage plus a control voltage to a gate of the first MOS transistor and a potential corresponding to the constant voltage minus the control voltage to a gate of the second MOS transistor.

Abstract: A signal handling stage provides variable gain, for example for automatic gain control functions, in a radio frequency tuner. The stage comprises a transconductance stage having negative feedback via further transconductance stage. The output current of the transconductance stage is supplied to an AGC core, which steers the output current between output loads and loads for driving the transconductance stage in accordance with an AGC voltage. The amount of negative feedback is therefore varied in accordance with the AGC voltage. For relatively low gain, a large amount of feedback is used and this improves the distortion performance. For relatively high gain, the negative feedback is reduced but a good noise figure can be achieved.

Abstract: The invention pertains to an integrated circuit arrangement, in particular, in accordance with the CMOS technology, with at least one transconductance amplifier (1) in order to generate a current signal (outp, outm) from an input voltage signal (inp-inm), wherein the transconductance amplifier consists of a first transconductance stage (gm1) and a second transconductance stage (gm2) that are connected in parallel, wherein the first transconductance stage (gm1) has a transconductance that is essentially defined by an ohmic resistance and the second transconductance stage (gm2) has an adjustable transconductance that is essentially defined by a transistor arrangement, and wherein the transconductance of the first transconductance stage (gm1) is higher than the transconductance of the second transconductance stage (gm2).

Abstract: A variable gain amplifier has a gain control circuit. The gain control circuit includes a first control input and a second control input. The first control input receives a first control signal. The gain control circuit varies gain of the variable gain amplifier based on a value of the first control signal. The second control input receives a second control signal. The gain control circuit varies gain slope of the variable gain amplifier based on a value of the second control signal.

Abstract: An RF power amplifier circuit for amplifying an RF signal over a broad range of power with improved efficiency includes a carrier amplifier for amplifying an RF signal over a first range of power and with a power saturation level below the maximum of the broad range of power is disclosed. A plurality of peak amplifiers are connected in parallel with the carrier amplifier with each of the peak amplifiers being biased to sequentially provide an amplified output signal after the carrier amplifier approaches saturation. The input signal is applied through a signal splitter to the carrier amplifier and the plurality of peak amplifiers, and an output for receiving amplified output signals from the carrier amplifier and the plurality of peak amplifiers includes a resistive load R/2. The split input signal is applied through a 90° transformer to the carrier amplifier, and the outputs of the peak amplifiers are applied through 90° transformers to a output load.

Abstract: A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifier transistor to obtain a conduction angle of at least about 180 °. The dc bias circuit includes a dynamic bias boosting circuit for increasing the dc bias current provided to the amplifying transistor by the dc bias current in direct proportion to an increase in the input signal provided to the power amplifier. An input to the dc bias circuit is coupled to a stage of the power amplifier circuit by a capacitor. The bias boosting circuit permits the power amplifier circuits to operate in Class B or Class AB with improved linearity, improved efficiency and reduced idle current.

Abstract: A constant gain, constant phase RF power block, e.g., for use in a RF amplifier apparatus. In a preferred embodiment, the power block includes a DC to DC power supply circuit co-located with an RF power transistor device on a common heat sink. The power supply circuit has as an input a varying DC voltage and as outputs a constant supply voltage and a constant bias voltage. The power device has as inputs the constant supply voltage and the constant bias voltage, and further configured to receive and amplify an RF signal. The power supply circuit preferably includes a first laser trimmable resistor for setting the constant supply voltage and a second laser trimmable resistor for setting the bias voltage. In this manner, the constant supply and bias voltages may be easily tuned to a desired level during assembly of the power block device. The input and amplified RF signals are each matched to a relatively high impedance, e.g., approximately fifty ohms.