Patents Issued in September 14, 2004
  • Patent number: 6791169
    Abstract: A microelectronic package includes first and second microelectronic elements in spaced-apart relationship which are electrically interconnected by a plurality of flexible leads and a layer of anisotropic conductive material. The flexible leads having one end attached to terminals on one of the microelectronic elements extends away therefrom having its opposite tip end electrically interconnected to contacts on the other microelectronic element by virtue of an interposed layer of the anisotropic conductive material.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: September 14, 2004
    Assignee: Tessera, Inc.
    Inventor: Flynn Carson
  • Patent number: 6791170
    Abstract: There is provided a high performance onboard semiconductor device with low manufacturing costs and low repair costs. The onboard semiconductor device includes a power chip substrate on which a power chip is mounted, a control substrate provided with an electrical part in relation to the power chip, and an outer enclosing case in which the power chip substrate and the control substrate are contained, and is characterized in that the control substrate and the outer enclosing case are removably fixed to each other.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: September 14, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masaru Fuku, Hirotoshi Maekawa
  • Patent number: 6791171
    Abstract: Several embodiments of stress metal springs are disclosed, which typically comprise a plurality of stress metal layers that are established on a substrate, which are then controllably patterned and partially released from the substrate. An effective rotation angle is typically created in the formed stress metal springs, defining a looped spring structure. The formed springs provide high pitch compliant electrical contacts for a wide variety of interconnection systems, including chip scale semiconductor packages, high density interposer connectors, and probe contactors. Several embodiments of massively parallel interface integrated circuit test assemblies are also disclosed, comprising one or more substrates having stress metal spring contacts, to establish connections between one or more separated integrated circuits on a compliant wafer carrier.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: September 14, 2004
    Assignee: NanoNexus, Inc.
    Inventors: Sammy Mok, Fu Chiung Chong
  • Patent number: 6791172
    Abstract: The present invention discloses a power semiconductor device manufactured using a chip-size package. The power semiconductor device includes a die having a first surface and a second surface opposite to the first surface; at least one lead frame, each of the at least one lead frames having a first terminal and a second terminal, the first terminal electrically connected to a corresponding terminal of the first surface or a corresponding terminal of the second surface of the die; an electrically conductive plate electrically connected to a corresponding terminal of the second surface of the die; and a packaging material used to encapsulate the die, one terminal of the lead frame and the electrically conductive plate. The second terminal of each lead frame and a surface of the electrically conductive plate opposite to the surface electrically connected to the second surface of the die are exposed to the outside of the packaging material and lie on the same plane.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: September 14, 2004
    Assignee: General Semiconductor of Taiwan, Ltd.
    Inventors: Shih-Kuan Chen, Ching-Lu Hsu
  • Patent number: 6791173
    Abstract: In order to manufacture a thin and small semiconductor device at low cost, the semiconductor device and its manufacturing method are disclosed. The semiconductor device comprises: a film wiring substrate made of insulating resin; a semiconductor chip fixed to the main surface of the wiring substrate; conductive wires to connect terminals of the semiconductor chip and wirings on the main surface of the wiring substrate; an encapsulation made of insulating resin integrally laminated on the main surface of the wiring substrate and covering the semiconductor chip and the bonding wires; and conductors penetrating through the wiring substrate and having one ends connected to the wirings on the main surface of the wiring substrate and the other ends protruding to the rear surface of the wiring substrate to form external terminals formed of bump electrodes, wherein the external terminals form the ball grid array.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: September 14, 2004
    Assignees: Hitachi, Ltd., Akita Electronics Systems Co., Ltd.
    Inventor: Toru Saga
  • Patent number: 6791174
    Abstract: A semiconductor device, in which the air within a gel resin can be efficiently and well purged, comprising a casing, a semiconductor device electrically connected by bonding wires and a gel resin filled in the casing and serves for insulation covering of the semiconductor device and the bonding wire. The device further comprises a board-shaped vibration damper in contact with the gel resin and is provided with a plurality of perforations each having an air inlet and an air outlet for the purpose of air extraction during the filling of the gel resin. The sectional area of the perforations is tapered and larger at the inlet than at the outlet, thus causing the perforations to have the form of a substantially conical trapezoid as a whole.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: September 14, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Haruyuki Matsuo, Ryuuichi Ishii
  • Patent number: 6791175
    Abstract: Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Kenichi Imamiya
  • Patent number: 6791176
    Abstract: A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and removing a first portion of the masking material. In this embodiment, at least a portion of the first portion of the spring structure is freed of masking material. In one aspect of the invention, the method includes planarizing the masking material layer and structure material to remove a portion of the structure material. In another aspect, the spring structure formed includes one of a post portion, a beam portion, and a tip structure portion.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: September 14, 2004
    Assignee: FormFactor, Inc.
    Inventors: Gaetan L. Mathieu, Benjamin N. Eldridge, Gary W. Grube
  • Patent number: 6791177
    Abstract: A package substrate is contemplated herein for reducing cross-talk for noise-sensitive signals. The package substrate includes noise-sensitive conductors adapted to receive the noise-sensitive signals. In one embodiment, the cross-sectional width of the noise-sensitive conductors is increased to reduce certain parasitic effects such as resistance and/or inductance. The package substrate also includes guard conductors which are arranged co-planar with and substantially parallel to the noise-sensitive conductors. A plurality of vias spaced equidistant from one another extends from a ground conductor to the guard conductors, providing a substantially uniform voltage across the guard conductors. The overall effect will reduce the inductive and capacitive cross-talk from neighboring signals and increase the signal integrity of noise-sensitive signals.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: September 14, 2004
    Assignee: LSI Logic Corporation
    Inventors: Leah M. Miller, Aritharan Thurairajaratnam, Edwin M. Fulcher
  • Patent number: 6791178
    Abstract: A multi-chip module has semiconductor devices and a wiring substrate for mounting the semiconductor devices, in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: September 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihide Yamaguchi, Takao Terabayashi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Patent number: 6791179
    Abstract: A monolithic semiconducting ceramic electronic component includes barium titanate-based semiconducting ceramic layers and internal electrode layers alternately deposited, and external electrodes electrically connected to the internal electrode layers. The semiconducting ceramic layers contain ceramic particles having an average particle size of about 1 &mgr;m or less and the average number of ceramic particles per layer in the direction perpendicular to the semiconductor layers is about 10 or more. The internal electrode layers are preferably composed of a nickel-based metal.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: September 14, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Mitsutoshi Kawamoto
  • Patent number: 6791180
    Abstract: In a ceramic circuit board having a ceramic substrate and a metal circuit plate bonded to one surface of the ceramic substrate, assuming that the warpage of the ceramic circuit board is a difference in height between the center and edge of the metal circuit plate and is positive (+) when the circuit board warps so as to be concave on the side of the metal circuit plate, the warpage of the ceramic circuit board is in the range of from −0.1 mm to +0.3 mm when the ceramic circuit board is heated to 350° C., and in the range of from +0.05 mm to +0.6 mm when the temperature of the ceramic circuit board is returned to a room temperature after the ceramic circuit board is heated to 350° C. The initial warpage of the ceramic circuit board is in the range of from +0.05 mm to +0.6 mm.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: September 14, 2004
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Yukihiro Kitamura, Takayuki Takahashi, Mitsuru Ohta, Yuji Ogawa
  • Patent number: 6791181
    Abstract: The present invention discloses a semiconductor light emitting device comprising at least one semiconductor light emitting element of edge-emission type, a first heat sink and a second heat sink, wherein at least a part of an electrode for the first-conduction-type semiconductor of the semiconductor light emitting element is in contact with the first heat sink; at least a part of an electrode for the second-conduction-type semiconductor of the semiconductor light emitting element is in contact with the second heat sink; and the first heat sink and the second heat sink are in contact with each other in a junction overlooking one of the two side planes which do not compose the facets of the cavity in the semiconductor light emitting element.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: September 14, 2004
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Hideyoshi Horie, Nobuhiro Arai, Naoyuki Komuro
  • Patent number: 6791182
    Abstract: At least a part of the inner leads 1a of a lead frame 1 is covered with a plating for a metallic fine wire connection, at least the entire portion where the lead frame 1 joins with the adhesive layer 2 is covered by at least one metal or alloy thereof different from the metallic fine wire connecting use plating. The metal or alloy is selected from the group consisting of gold, platinum, iridium, rhodium, palladium, ruthenium, indium, tin, molybdenum, tungsten, gallium, zinc, chromium, niobium, tantalum, titanium and zirconium. Thereby, generation of defects, such as leakage and shorting, due to ion migration can be prevented.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: September 14, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Junpei Kusukawa, Ryozo Takeuchi, Toshiaki Ishii, Hiromichi Suzuki, Fujio Ito, Takafumi Nishita, Akihiko Kameoka, Masaru Yamada
  • Patent number: 6791183
    Abstract: A power semiconductor module and a cooling element for holding the power semiconductor module are described. The power semiconductor module has a housing that has an underside and an upper side. At least one spring element projects from the upper side of the housing and is disposed on the upper side of the housing.
    Type: Grant
    Filed: December 24, 2001
    Date of Patent: September 14, 2004
    Assignee: Infineon Technologies AG
    Inventor: Konstantinos Kanelis
  • Patent number: 6791184
    Abstract: A support assembly for supporting an integrated circuit package with an array of solder columns extending from a bottom surface of the integrated circuit package to a circuit board preferably includes: a pair of shims for supporting the integrated circuit package, the shims being positioned along opposite edges of the integrated circuit package and placed between and abutting the integrated circuit package and the circuit board; and a retention clip for aligning and securing in place the pair of shims.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeffrey L Deeney, Laszlo Nobi, Joseph D. Dutson
  • Patent number: 6791185
    Abstract: The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Alan G. Wood, Warren M. Farnworth
  • Patent number: 6791186
    Abstract: A mounting substrate on which a semiconductor element is to be mounted by flip-chip bonding, the semiconductor element having a surface on which a plurality of electrode terminals are arranged in a line, each of said electrode terminals having a protruded electrode formed thereon, wherein the surface of the mounting substrate on which the semiconductor element is to be mounted is provided with a protective film having an opening corresponding to an area of the semiconductor element where the protruded electrodes are located, a plurality of connection electrodes being arranged in the opening, the connection electrodes being provided with a solder for bonding it to the protruded electrodes, and being arranged at the same interval as that of the protruded electrodes, and each of the connection electrodes being connected to a wiring pattern of the mounting substrate, and wherein the length of a portion of the connection electrode from the center of the opening to the end thereof that is not connected with the wir
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: September 14, 2004
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Haruo Sorimachi, Yoshihiro Yoneda
  • Patent number: 6791187
    Abstract: A semiconductor device includes a semiconductor substrate; an insulating laminate formed over the semiconductor substrate, and including a lower part and a higher part formed over the lower part; a first conductor formed in the higher part of the insulating laminate, an insulator, having an etching characteristic different from the lower part and the higher part of the insulating laminate, formed between the lower part of the insulating laminate and the first conductor, a first contact hole formed through the higher part of the insulating laminate, penetrating inside peripheral edges of the first conductor, reaching the insulator; and a second conductor filled in the first contact hole and electrically connected to the first conductor at its side wall exposed in the first contact hole.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: September 14, 2004
    Assignee: Fujitsu Limited
    Inventors: Taiji Ema, Tohru Anezaki
  • Patent number: 6791188
    Abstract: Disclosed is a thin film aluminum alloy which is limited in the generation of hillocks while maintaining a low specific resistance and hardness irrespective of annealing temperature. In order to obtain the thin film aluminum alloy having a Vickers hardness of 30 Hv or less and a film stress (absolute value indication) of 30 kg/mm2 or less when performing annealing treatment at a temperature ranging from 25° C. to 500° C., wherein said hardness and said film stress are distributed in a predetermined hardness range and in a predetermined film stress range respectively within the temperature range of the above-mentioned annealing treatment and are respectively almost constant against annealing temperature, the thin film aluminum alloy being formed as a film on a substrate by a sputtering method using a sputtering target having a composition comprising 0.5 to 15 atom % of one or more types selected from Ag, Cu, Mg and Zn and 0.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: September 14, 2004
    Assignee: Vacuum Metallurgical Co., Ltd.
    Inventors: Junichiro Hagihara, Ichiro Tokuda
  • Patent number: 6791189
    Abstract: An apparatus to retain an assembled component on one side of a double-sided printed circuit board during reflow of other components subsequently positioned onto an opposite side of the double-sided printed circuit board and methods for manufacturing and using the same. Being formed from an epoxy material, the retainer is configured to be coupled with a component, which is then positioned onto a printed circuit board. During a subsequent solder reflow stage, an ambient temperature surrounding the printed circuit board increases, and the epoxy material is configured to enter a semi-liquid state, flowing onto, and adhering with, the printed circuit board. Upon reaching a typical solder reflow temperature, the liquefied epoxy material is configured to cure or harden, adhesively coupling the component with the printed circuit board. Thereby, the component is inhibited from separating from the printed circuit board when the printed circuit board is subsequently inverted, populated, and reflowed.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: Tom E. Pearson, Christopher D. Combs, Arjang Fartash, Raiyomand Aspandiar
  • Patent number: 6791190
    Abstract: A method for forming a self-aligned contact (SAC)/borderless contact opening includes forming a shallow trench isolation (STI) structure in a substrate to define an active area. A gate structure including a cap layer is formed. The gate structure is formed on the substrate and oriented perpendicular to the STI structure and the active area. An oxide spacer is formed on at least one of the sidewalls of the gate structure. A conformal liner layer is formed on the substrate covering the gate structure, the oxide spacer, and the STI structure. An inter-layer dielectric (ILD) layer is formed on the substrate covering the liner layer. The ILD layer is patterned and etched to define a SAC/borderless contact opening. A SAC/borderless contact opening structure also is described.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: September 14, 2004
    Assignee: Macronix International Co., Ltd.
    Inventor: Chia Chi Chung
  • Patent number: 6791191
    Abstract: A device adapted to protect integrated circuits from reverse engineering comprising a part looking like a via connecting two metal layers, but in fact attached only to one metal layer and spaced from the other. Having such “trick” via would force a reverse engineer to think there is a connection where there is none. A method for fabricating such device.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: September 14, 2004
    Assignee: HRL Laboratories, LLC
    Inventors: Lap-Wai Chow, James P. Baukus, William M. Clark, Jr.
  • Patent number: 6791192
    Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: September 14, 2004
    Assignee: Megic Corporation
    Inventors: Mou-Shiung Lin, Bryan Peng
  • Patent number: 6791193
    Abstract: A chip mounting substrate comprising: a mounting base defined by a first surface and a second surface opposite to the first surface; a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands; and a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Watanabe, Isao Ozawa
  • Patent number: 6791194
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: September 14, 2004
    Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Patent number: 6791195
    Abstract: Semiconductor device 3 comprises semiconductor chip 11, Au ball bumps 21 formed on pad electrodes 12 with a stud bump method, and thermoplastic adhesive layer 22 provided on the surface of semiconductor chip 11 on which pad electrodes 12 are formed, in which the tops of Au ball bumps 21 project from the surface of adhesive layer 22. Reliable bonding can be realized by forming the bumps for electrical connection and the adhesive resin having an adhesion function on the semiconductor chip. In addition, the present invention provides a method of bonding a copper foil to a semiconductor wafer to form a wiring pattern, a multi chip module in which electrical connection is established by bumps bonded to each other through an adhesive layer, and the like.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: September 14, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Michitaka Urushima
  • Patent number: 6791196
    Abstract: Devices that have bonding pads, and methods for fabricating the same. The bonding pads have two conductive layers, and an intermediate layer between them. The intermediate layer has a hybrid configuration of a relatively large conductive plate section, and a mixed plugs/mesh section. The plugs/mesh section has conductive portions interspersed with non-conducting portions, with features that are relatively small in size. The hybrid configuration achieves a proper balance between the plate section for the main electrical contact, and the plugs/mesh section for support and additional current density.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: September 14, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Whee Kwon, Jin Hyuk Lee, Yun Heub Song, Sa Yoon Kang
  • Patent number: 6791197
    Abstract: An apparatus and a method for reducing layer separation and cracking in semiconductor devices. A structure is formed over a semiconductor wafer that includes die separated by scribe streets and that includes probe pads for testing die. A notch is cut within a scribe street so as to expose an open area that does not contain any probe pad and that does not contain any metal layers. The wafer is then severed into semiconductor devices by extending a cutting blade through the open area. A semiconductor device is then electrically and physically coupled to a ball grid array substrate to form a ball grid array device having reduced layer separation and cracking.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: September 14, 2004
    Assignee: Integrated Device Technology, Inc.
    Inventor: Anne T. Katz
  • Patent number: 6791198
    Abstract: A method and device for providing a gate blocking material. Specifically, a method for molding a substrate having known good and bad sites thereon, by blocking the gate area of the bad sites during the molding process. A blocking material or an injection pin are used to interrupt the flow of molding compound through an injection molding system, and thereby prevent molding compound from flowing onto the known bad substrate sites.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Bret K. Street, Casey L. Prindiville, Cary Baerlocher
  • Patent number: 6791199
    Abstract: AS conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided. Thickness of an electric connection means SD is substantially made definite as the electric connection means SD does not flow to a conductive path 11B by using a flow-prevention film DM.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: September 14, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Patent number: 6791200
    Abstract: An SRAM includes a plurality of memory cells which are arranged in an extension direction of bit lines, each of which has a long edge and a short edge, an extension direction of the short edge being equal to the extension direction of the bit lines. A distance between polysilicon wirings which are formed in one of the memory cells and which become gates of NMOS transistors arranged in the extension direction of the bit lines, respectively, differs from a distance between the polysilicon wiring and the polysilicon wiring which becomes a gate of an NMOS transistor formed in the other memory cell.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 14, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Koji Nii
  • Patent number: 6791201
    Abstract: In a starter, a pinion is fitted on a pinion shaft such that a rear end surface of the pinion is pressed against a thrust receiving wall provided on the pinion shaft, while a front end surface of the pinion is pressed backward by a detent ring. The detent ring has a tapered surface and fitted in a recess provided on a pinion shaft. A front rising wall defining the recess has a tapered wall so as to correspond to the tapered surface. Since resiliency of the detent ring constricting radially inward is applied to the tapered wall, a component force of the resiliency pressing the pinion axially backward is generated. Thus, the pinion is restricted from moving axially backward by pressing a rear end surface against a thrust receiving wall of the pinion shaft, while the front side surface of the pinion is pressed axially backward through the detent ring.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: September 14, 2004
    Assignee: Denso Corporation
    Inventors: Mituhiro Murata, Toyohisa Yamada, Shinji Usami
  • Patent number: 6791202
    Abstract: A remote starting system shutoff system and method for a vehicle includes a vehicle power plant and a remote starting system that is connected to the vehicle power plant. A transmitter actuates the remote starting system to start the vehicle power plant. A vehicle hazard switch in the passenger compartment of the vehicle has first and second positions. When the hazard switch is in the first position, the vehicle power plant can be started using the transmitter. After the vehicle power plant is started, the remote starting system turns the vehicle power plant off if the hazard switch transitions from the first position to the second position. Remote starting is disabled anytime that the switch is in the second position. The transmitter is preferably a radio frequency transmitter. The vehicle power plant is selected from the group of internal combustion engines, diesel engines, hybrids and fuel cells.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: September 14, 2004
    Assignee: General Motors Corporation
    Inventor: Scott A. McCullough
  • Patent number: 6791203
    Abstract: This invention relates to an assistance controlling apparatus for a hybrid vehicle which assists an outputs of the engine by an output of the motor. The assistance controlling apparatus for a hybrid vehicle according to this invention, comprises: an engine which outputs propulsive power for the vehicle; a motor which assists the output of the engine; a remaining quantity detector which detects whether the remaining quantity of the fuel is under a fixed value or not; and an assistance-restricting unit which restricts the assistance of the output of the engine by the motor when the remaining quantity detector detects that the remaining quantity of the fuel is under the fixed value.
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: September 14, 2004
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Atsushi Matsubara, Atsushi Izumiura, Hideyuki Takahashi, Takashi Kiyomiya, Hironao Fukuchi, Katsuhiro Kumagai
  • Patent number: 6791204
    Abstract: A system and method to provide an improved power electronics starting system (100) in which starting torque is delivered by a salient pole synchronous machine (102), while associated power electronics (110) and (118) utilization is maximized by adjusting the Park vector of the armature (102A) phase current to remain in-phase with the Park vector of the armature (102A) terminal voltage, regardless of the level of saturation of the pole synchronous machine (102).
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: September 14, 2004
    Assignee: Honeywell International Inc.
    Inventors: Bulent Sarlioqlu, Colin E. Huggett
  • Patent number: 6791205
    Abstract: A Reciprocating Generator Wave Power Buoy consists of a reciprocating generator rigidly attached to the underside of an ocean buoy and creates electric power from the surface ocean swells. The generator coil maintains a stable position beneath the ocean surface while the magnetic field housing reciprocates with the vertical motion of the buoy in response to interaction with swell and waves on the surface of the ocean. Damping plates attached to the generator coil inhibit the motion of the generator coil, thus keeping it in a stable position relative to the motion of the magnetic housing. The magnetic housing focuses the magnetic field through the generator coil and the relative motion between the magnetic housing and generator coil creates an electromotive force in the coil. The design of the generator provides a uniform field of single magnetic orientation throughout the entire stroke of the generator.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: September 14, 2004
    Assignee: Aqua Magnetics, Inc.
    Inventor: Thomas C. Woodbridge
  • Patent number: 6791206
    Abstract: A floating ocean swell electric generator system includes a floating platform having a deck and an engine for propelling a floating platform. A plurality of ocean electric generators are mounted on the floating platform. Each floating generator has an elongated stator tube extending from the floating platform below the deck into the surface of the water and a floating linear rotor in the stator tube for movement with ocean swells passing beneath the floating platform. Electric energy is generated by the movement of the linear rotor in the stator tube responsive to ocean swells.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: September 14, 2004
    Inventor: David D. Woodbridge
  • Patent number: 6791207
    Abstract: An electric power supply system for a vehicle has an electric power line wired in a loop configuration. From the electric power line power is supplied to a load, and to another system which supplies control system power supply. One shutdown circuit is provided in a module connected to the loop configured power supply line. When the electric power line and the load are short circuited, the shutdown can isolate and shut down only the failure point. Further, when the car is not in use, by stopping the power supply to the load, current consumption can be restrained. In response to detection of a ground short and a failure of a connection of a connector, an over-current prevention of an electric power line, a simple construction can be provided and a low current consumption can be realized.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: September 14, 2004
    Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.
    Inventors: Tatsuya Yoshida, Hiroyuki Saito, Shinichi Sakamoto, Mitsuru Kon-i, Yuichi Kuramochi, Kaneyuki Okamoto, Ichiro Ohsaka, Kiyoshi Horibe
  • Patent number: 6791208
    Abstract: An electrical power controller controls the selection of power sources, backup generator and normal utility line, to an automatically controlled load and other loads during and at the end of a power failure in a system. As long as the automatic load needs to be on, the power controller will connect the automatic load directly to a backup generator bypassing the transfer switch and disable a stop generator signal. When utility power returns, the transfer switch switches all other loads to operate from utility power and the transfer switch sends the stop signal to the backup generator. However, only when the power controller determines that the automatic load is no longer turned on will it re-enable the stop signal and return the automatic load to normal utility power selected by the transfer switch.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: September 14, 2004
    Inventor: Mark Pfeiffer
  • Patent number: 6791209
    Abstract: A device is presented having at least one power supply. The power supply is connected to a power supply fan. A first power source terminal is connected to the at least one power supply. A second power source terminal is connected to the at least one power supply. The power supply fan is powered from a source external to the at least one power supply.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: Tomm V. Aldridge, Casey R. Winkel
  • Patent number: 6791210
    Abstract: A power delivery apparatus, system may include a series-connected plurality of energy storage devices, a voltage sensor to sense a supply voltage across a load coupled to a selected one of the plurality of storage devices, and a switch to couple and decouple various ones of the series-connected plurality of energy storage devices from the load when the supply voltage is less than or equal to a reference voltage. An article, including a machine-accessible medium, capable of directing a machine to carry out a method of delivering power may include data which directs the machine to couple each one of a series-connected plurality of energy storage elements to a power source, couple a selected one of the plurality of storage elements to a load, discharge a selected amount of energy from the selected one of the series-connected plurality of storage elements into the load, and decouple the selected one of the series-connected plurality of storage elements from the load.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: Paul E. Stevenson, Jon E. Tourville
  • Patent number: 6791211
    Abstract: A transfer switch for selectively connecting an auxiliary power source, such as a standby generator, to selected circuits of a building, includes double pole circuit protection as well as a unique circuit breaker and switch arrangement which can be used in either a double pole circuit or a pair of single pole circuits. The transfer switch includes a main double pole circuit breaker downstream of the power inlet, for providing double pole overcurrent protection for all circuits interconnected with the transfer switch. The transfer switch also includes a series of single pole switches and associated single pole circuit breakers, for controlling the supply of power to single pole electrical circuits. At least one additional pair of single pole switches can either be tied together for use as a double pole switch or used as two separate single pole switches.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: September 14, 2004
    Assignee: Reliance Controls Corporation
    Inventor: Michael O Flegel
  • Patent number: 6791212
    Abstract: A regulated voltage-boosting device provides a charge-pump circuit, which has an input terminal receiving a first voltage and an output terminal supplying a second voltage higher than the first voltage. The regulated voltage-boosting device provides a plurality of voltage-boosting stages that can be selectively activated and deactivated. The regulated voltage-boosting device provides an automatic-selection circuit for activating a number of voltage-boosting stages which is correlated to the first voltage and to the second voltage.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: September 14, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Francesco Pulvirenti, Gregorio Bontempo
  • Patent number: 6791213
    Abstract: The invention provides a modular distribution system having central distribution panel for receiving a plurality of services at an input and having a plurality of outputs each connected to an outlet at a remote location. A central region is provided in the central distribution panel having a plurality of module receiving connectors each having a first portion connected to the input and a second portion connected to one of the plurality of outlets. A plurality of modules are each separately connectable to a respective module receiving connector and configured to bridge a selected service from the first portion of the module receiving connector to the second portion of the module receiving connector.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: September 14, 2004
    Assignee: Yazaki North America, Inc.
    Inventors: Matthew T. Miller, Larry E. Dittmann, Jeffrey J. Fegley, William H. Bair
  • Patent number: 6791214
    Abstract: A moving-magnet, linear motor which substantially produces no cogging force is provided. The moving-magnet, linear motor has a mover and a stator. The mover has a plurality of permanent magnets orderly disposed along the traveling direction of the mover. The stator has a toothed iron-core having a plurality of teeth and a plurality of coils wound around the teeth thereof. The permanent magnets are disposed such that the two longitudinal ends of each permanent magnet are skewed with respect to each other by a tooth pitch of the toothed iron-core.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: September 14, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobushige Korenaga
  • Patent number: 6791215
    Abstract: In varying embodiments, the fault tolerant linear actuator of the present invention is a new and improved linear actuator with fault tolerance and positional control that may incorporate velocity summing, force summing, or a combination of the two. In one embodiment, the invention offers a velocity summing arrangement with a differential gear between two prime movers driving a cage, which then drives a linear spindle screw transmission. Other embodiments feature two prime movers driving separate linear spindle screw transmissions, one internal and one external, in a totally concentric and compact integrated module.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: September 14, 2004
    Assignee: Board of Regents The University of Texas System
    Inventor: Delbert Tesar
  • Patent number: 6791216
    Abstract: An exciter assembly for supplying power to a superconducting load, such as a superconducting field coil, disposed within a cryogenic region of a rotating machine. The exciter assembly provides an efficient and reliable approach for transferring the electrical power energy across a rotating interface. The exciter assembly includes a transformer having a primary winding and a secondary winding, and a rotatable enclosure including a wall having an intermediate core formed of a high permeability material. The intermediate core is positioned between the primary of a transformer and the secondary of the transformer. In essence, the intermediate core acts as a flux “window” or “shunt” between the primary winding and the secondary winding. One of the primary and secondary windings is generally positioned in a rotational reference frame relative to the other of the primary and secondary windings.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: September 14, 2004
    Assignee: American Superconductor Corporation
    Inventor: Swarn S. Kalsi
  • Patent number: 6791217
    Abstract: A method and system for determining the velocity of a rotating device is described herein. The system includes an apparatus with a set of sense magnets affixed to a rotating shaft of the rotating device and a circuit assembly. The circuit assembly includes a circuit interconnection having a plurality of sense coils and sensors affixed thereto. The circuit assembly is adapted be in proximity to the set of sense magnets on the rotating part. A controller is coupled to the circuit assembly, where the controller executes an adaptive algorithm that determines the velocity of the rotating device. The algorithm is a method of combining a derived velocity with a velocity from the tachometer.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: September 14, 2004
    Assignee: Delphi Technologies, Inc.
    Inventors: Steven James Collier-Hallman, William J Bressette
  • Patent number: 6791218
    Abstract: A system and method for protecting a motor from a stall condition includes a brush motor 11 having power brushes 14 and 16 that convey power to windings of the motor, and one sensing brush 20 constructed and arranged to sense a speed of rotation of an armature motor. A controller 23 is constructed and arranged to compare a sensed speed of rotation with a minimum speed value that is indicative of a stall condition. A relay 28 is constructed and arranged to disconnect power to the motor if the sensed speed is below the minimum speed value.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: September 14, 2004
    Assignee: Siemens VDO Automotive Inc.
    Inventors: Corneliu Dragoi, Attila Simofi-Ilyes, Andrew Lakerdas, Dragan Radakovic