Abstract: According to an aspect of the present invention, a nitride semiconductor laser device includes a nitride semiconductor active layer (106), and a stripe-shaped waveguide for guiding light generated in the active layer. At least one pair of light-absorbing films (112) are provided in at least local regions on the opposite sides of the stripe-shaped waveguide, to reach a distance within 0.3 &mgr;m from the waveguide. According to another aspect of the present invention, a GaN-based semiconductor laser device includes first conductivity type semiconductor layers (103-105), a semiconductor active layer (106) and second conductivity type semiconductor layers (107-110) stacked sequentially. The laser device further includes a ridge stripe (111) provided to cause a refractive index difference for confinement of light in a lateral direction crossing a longitudinal direction of a cavity, and a current-introducing window portion (114) provided on the ridge stripe.

Abstract: A single integrated wafer may be formed with optical components on one side and electronic components on the opposite side. Communication between the sides may be by way of optical signals that may be transmitted through the semiconductor wafer.

Abstract: A light-emitting diode light string includes a plurality of lighting modules serially connected to an electric wire. Each lighting module includes a dual-color light emitting diode that serves as a light source of the light string and is removably covered with a facetted shade providing enhanced diffusion and refraction capacity. The light module may be quickly detachably connected to the electric wire through engagement of two corresponding terminals with each other. The dual-color light emitting diode and the facetted shade enable production of changeful and colorful flashes and creation of a unique decorating effect.

Abstract: A semiconductor device capable of stabilizing operations thereof is provided. This semiconductor device comprises a substrate provided with a region having concentrated dislocations at least on part of the back surface thereof, a semiconductor element layer formed on the front surface of the substrate, an insulator film formed on the region of the back surface of the substrate having concentrated dislocations and a back electrode formed to be in contact with a region of the back surface of the substrate other than the region having concentrated dislocations.

Abstract: In a sealing method of a top-emission organic light emitting element, in the case of using a method of filling with a sealing agent between a substrate mounted with pixels and an opposed substrate, the organic light-emitting element is degraded by ultraviolet rays when irradiation of the ultraviolet rays is performed toward the pixels in order to achieve ultraviolet curing of the sealing agent filling on the pixels. It is an object of the present invention to propose a method for avoiding this phenomenon to provide an organic light-emitting device with superior stability. In order for a sealing agent 13 filling on a pixel portion 14 to have a larger absorbance to ultraviolet rays, an ultraviolet-absorbent material is dispersed in a sealing agent to make an adjustment so that the absorbance of ultraviolet absorption wavelength of 400 nm or less becomes 1 or more.

Abstract: An organic light-emitting device (OLED) having high luminescent efficiency in which most electrons and holes are combined within a light-emitting layer of the OLED is disclosed. The OLED comprises a first electrode formed on a substrate, at least one organic layer including an organic light-emitting layer, a second electrode formed on the organic layer, a hole inducing layer including a material having an ionization potential higher than that of the organic light-emitting layer and formed between the first electrode and the organic light-emitting layer and/or an electron blocking layer including a material having an electron affinity higher than that of the organic light-emitting layer and formed between the second electrode and the organic light-emitting layer.

Abstract: A method of fabricating a vertical structure opto-electronic device includes fabricating a plurality of vertical structure opto-electronic devices on a crystal substrate, and then removing the substrate using a laser lift-off process. The method then fabricates a metal support structure in place of the substrate. In one aspect, the step of fabricating a metal support structure in place of the substrate includes the step of plating the metal support structure using at least one of electroplating and electro-less plating. In one aspect, the vertical structure is a GaN-based vertical structure, the crystal substrate includes sapphire and the metal support structure includes copper. Advantages of the invention include fabricating vertical structure LEDs suitable for mass production with high reliability and high yield.

Abstract: A memory system, including a first electrode, a memory storage element, and a control element. The control element having a breakdown voltage. The breakdown voltage is increased by partially-processing the control element. In one aspect, the partial-processing results by processing the control element for a briefer duration than the memory storage element. In another aspect, the partial-processing results by forming the control element from a plurality of layers, some of the plurality of layers are unprocessed while other ones of the plurality of layers are fully processed.

Abstract: An apparatus is constituted with an integrated circuit and a flex tape coupled-to the integrated circuit. The flex tape is employed to facilitate ingress/egress of signals to/from the integrated circuit. In one embodiment, the flex tape includes a plurality of signal traces. In another embodiment, the apparatus also includes a silicon interposer coupled to the flex tape and a substrate coupled to the silicon interposer.

Abstract: An ESD protection circuit has a VDD bus, a VSS bus, an IC pad, a PMOS transistor coupled to the IC pad and the VDD bus, and an NMOS transistor coupled to the IC pad and the VSS bus. The pitch of the PMOS can smaller than the pitch of the NMOS, and the drain-contact-to-gate-spacing (DCGS) for the PMOS can be smaller than the DCGS for the NMOS.

Abstract: A three-dimensional solid-state memory is formed from a plurality of bit lines, a plurality of layers, a plurality of tree structures and a plurality of plate lines. Bit lines extend in a first direction in a first plane. Each layer includes an array of memory cells, such as ferroelectric or hysteretic-resistor memory cells. Each tree structure corresponds to a bit line, has a trunk portion and at least one branch portion. The trunk portion of each tree structure extends from a corresponding bit line, and each tree structure corresponds to a plurality of layers. Each branch portion corresponds to at least one layer and extends from the trunk portion of a tree structure. Plate lines correspond to at least one layer and overlap the branch portion of each tree structure in at least one row of tree structures at a plurality of intersection regions.

Abstract: A power semiconductor module has a base plate comprising a framelike housing, a cap, and at least one electrically insulated substrate disposed inside the housing. The substrate comprises an insulation body with a plurality of metal connection tracks located thereon and insulated from one another, power semiconductor components located on the connection tracks, and terminal elements leading to the outside of the power semiconductor module for load and auxiliary contacts. Some of these terminal elements in the interior of the power semiconductor module comprise contact springs, which are disposed between the connection tracks and contact points on a printed circuit board. The printed circuit board has conductor tracks, which connect the contact points to contact elements that lead to the outside of the power semiconductor module.

Abstract: A thin film transistor (TFT) with a self-aligned lightly-doped region and a fabrication method thereof. An active layer has a channel region, a first doped region and a second doped region, in which the first doped region is disposed between the channel region and the second doped region. A gate insulating layer formed overlying the active layer has a central region, a shielding region and an extending region. The shielding region is disposed between the central region and the extending region, the central region covers the channel region, the shielding region covers the first doped region, and the extending region covers the second doped region. The shielding region is thicker than the extending region. A gate layer is formed overlying the gate insulating layer, covers the central region and exposes the shielding region and the extending region.

Abstract: An organic field-effect transistor and a method of making the same include a self-assembled monolayer (SAM) of bifunctional molecules disposed between a pair of electrodes as a channel material. The pair of electrodes and the SAM of bifunctional molecules are formed above an insulating layer, in which each of the bifunctional molecules comprises a functionality at a first end that covalently bonds to the insulating layer, and an end-cap functionality at a second end that includes a conjugated bond. The SAM of bifunctional molecules may be polymerized SAM to form a conjugated polymer strand extending between the pair of electrodes.

Abstract: The invention provides an electro-optic device that includes a frame (i.e., frame-shaped pattern) disposed on a frame area in a TFT array substrate. The frame area is disposed between an image display area and a peripheral area. The frame is formed of the same film as capacitor electrodes, and is disposed at at least a part of the frame area. The frame is formed of the same film as wiring connected to an external circuit-connecting terminal. Accordingly, the electro-optic device can prevent the generation of an image caused by light leakage at the periphery of the image as much as possible, and thereby improve image quality.

Abstract: The present invention relates to a semiconductor substrate production method, field effect transistor production method, semiconductor substrate and field effect transistor which, together with having low penetrating dislocation density and low surface roughness, prevent worsening of surface and interface roughness during heat treatment of a device production process and so forth. A production method of a semiconductor substrate W, in which SiGe layers 2 and 3 are formed on an Si substrate 1, is comprised of a heat treatment step in which heat treatment is performed either during or after the formation of the SiGe layers by epitaxial growth, at a temperature that exceeds the temperature of the epitaxial growth, and a polishing step in which irregularities in the surface formed during the heat treatment are removed by polishing following formation of the SiGe layers.

Abstract: Write characteristics and read characteristics can be improved at the same time by applying novel materials to ferromagnetic layers. In a magneto resistive effect element having a pair of ferromagnetic layers being opposed to each other through an intermediate layer to cause a current to flow in the direction perpendicular to the film plane to obtain a magnetoresistive change, at least one of the ferromagnetic layers contains a ferromagnetic material containing Fe, Co and B. The ferromagnetic material should preferably contain FeaCobNicBd (in the chemical formula, a, b, c and d represent atomic %. 5≦a≦45, 35≦b≦85, 0≦c≦35, 10≦d≦30. a+b+C+d=100).

Abstract: A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

Abstract: The semiconductor storage device of the present invention is provided with a first cell unit including a first memory cell selection transistor, a first and a second compare transistors and a first capacitor; and a second cell unit including a second memory cell selection transistor, a third and a fourth compare transistors and a second capacitor; the cell units being disposed side by side along a boundary to constitute a memory cell, in which the second compare transistor controlled by a first compare line is connected to a match line, and the fourth compare transistor controlled by a second compare line is connected to a ground line.

Abstract: An interposer, located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, that includes an oxide layer formed on a polished surface of a silicon substrate, a thin film dielectric capacitor formed on the oxide layer, a plurality of metallized that electrically connect to either of the electrodes of the thin film dielectric capacitor, and vias than conduct power, ground and signals between a the ceramic substrate and the integrated circuit. The interposer connects the metallized vias to the integrated circuit by solder connections and also connects the vias conducting power, ground and signals from the ceramic substrate to the interposer by solder connections.

Abstract: A nonvolatile memory device including one transistor and one resistant material and a method of manufacturing the nonvolatile memory device are provided. The nonvolatile memory device includes a substrate, a transistor formed on the substrate, and a data storage unit connected to a drain of the transistor. The data storage unit includes a data storage material layer having different resistance characteristics in different voltage ranges.

Abstract: The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first region (1a), provided in the substrate (1), as first capacitor electrode, a dielectric layer (10) on the trench wall as capacitor dielectric and a metallic filler material (30″) provided in the trench (2) as second electrode. Above the conducting metallic filling material (30″) a dielectric filling material (35) is provided in the trench (2) with a cavity (40) provided for mechanical tensions. The invention further relates to a corresponding method of production.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: A thin-film capacitor (2) in which a lower electrode (6), a dielectric thin-film (8), and an upper electrode (10) are formed in order on a substrate (4). The dielectric thin-film (8) is made of a composition for thin-film capacitance devices. The composition includes a bismuth layer-structured compound whose c-axis is oriented vertically to the substrate and which is expressed by a formula: (Bi2O2)2+(Am−1BmO3m+1)2−, or Bi2Am−1BmO3m+3 wherein “m” is an even number, “A” is at least one element selected from Na, K, Pb, Ba, Sr, Ca and Bi, and “B” is at least one element selected from Fe, Co, Cr, Ga, Ti, Nb, Ta Sb, V, Mo and W. The temperature characteristics of the dielectric constant are excellent. Even if the dielectric thin-film is made more thinner, the dielectric constant is relatively high, and the loss is small. The leak characteristics are excellent, the break-down voltage is improved and the surface smoothness is excellent.

Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

Abstract: Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will provide an indication of the stored data at this location in the memory array within the EEPROM or will act as the absence of a transistor at this location in the logic array within the FPLA.

Abstract: A semiconductor storage device includes a field effect transistor having a gate insulator, a gate electrode and a pair of source/drain diffusion regions which are formed on a semiconductor substrate. Recesses are formed so as to increasingly widening sideways in cross section between opposite side portions of the gate electrode and the semiconductor substrate surface, respectively. Memory function bodies each of which is composed of a charge retention part made of a material having a function of storing electric charge, and an anti-dissipation dielectric having a function of preventing dissipation of stored electric charge, are formed on opposite sides of the gate electrode in such a fashion that the recesses are thereby buried. Thus, the semiconductor storage device is capable of solving the issues of overerase and read failures due to the overerase and enhancing the reliability.

Abstract: Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and the at least one polysilicon structure. The at least one polysilicon structure is formed adjacent to vertical edges of the at least one floating gate layer and above the oxide layer. The polysilicon structure, which includes polysilicon wings and ears, is used to increase the capacitive coupling of memory cells in memory devices, thereby allowing for further reduction or scaling in the size of memory cells and devices.

Abstract: Provided are a semiconductor integrated circuit including a unit which detects soft defects in a pull-up circuit of a static memory cell, and a soft defect detection method and a testing method thereof. The semiconductor integrated circuit includes a static memory cell, a bit line connected to a first node of the static memory cell and a complementary bit line connected to a second node of the static memory cell, and an equalization circuit connected to the bit line and the complementary bit line to equalize the bit line and the complementary bit line in response to a test signal during a test mode. The semiconductor integrated circuit and the soft defect detection method can rapidly detect soft defects in the pull-up circuit of the static memory cell without a retention test. Furthermore, the testing method can rapidly detect soft defects in the pull-up circuit of the static memory cell, allowing the test time to be drastically reduced.

Abstract: In a memory cell, the substrate contact region of an NMOS transistor and the well contact region of a PMOS transistor are arranged perpendicularly to a floating gate. In a cell array, the memory cell and another memory cell arranged axisymmetrically with respect to the memory cell are alternately arranged in the column direction to constitute a sub array, and the sub arrays arranged in the column direction are arranged in parallel or axisymmetically in the row direction. With this arrangement, the substrate contact region, the well contact region, and the diffusion region of the PMOS transistor can be shared between the adjacent memory cells, thereby reducing the area of the cell array.

Abstract: A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region.

Abstract: An array process diagnosis test structure for an integrated circuit including a transistor array composed of vertical FET memory cell access transistors, which are formed into the depth of a substrate in the form of active webs which run parallel in the lateral direction of the circuit is disclosed. Memory cell storage capacitors in the array test structure are formed in deep trenches on the end faces of those sections of the active webs which form the vertical FET transistors. Word lines are arranged along the webs and along parallel intersecting bit lines of the array, outside of which, and on two mutually opposite edges, are located a first and second word line comb. The wordline combs are offset and connected alternately to different word lines. In addition, a first and a second bit line comb are formed on the two other opposing edges of the transistor array mutually offset and each connected to different bit lines.

Abstract: A semiconductor device includes a first conductivity type semiconductor substrate. A first conductivity type drift layer is formed on a surface of the first conductivity type semiconductor substrate, and a second conductivity type base region is produced in the first conductivity type drift layer. The second conductivity type base region has a trench formed in a surface thereof. A trench-stuffed layer is formed by stuffing the trench with a suitable material, and a second conductivity type column region formed in the first conductivity type drift layer and sited beneath the trench-stuffed layer.

Abstract: A semiconductor structure includes a substrate. A first semiconductor layer is formed on the substrate and being converted into a porous layer. The porous layer is further oxidized to form a buried oxide layer.

Abstract: In a semiconductor integrated circuit device, a first control signal outputted from the power voltage evaluation circuit (12) controls power voltage of the power voltage generation circuit (11) so that the power voltage becomes lower within a range over which the internal circuit normally operates, while a second control signal outputted from the specified voltage detection circuit (13) controls the power voltage of the power voltage generation circuit (11) so that the power voltage generated by the power voltage generation circuit (11) does not become equal to or higher than a specified voltage. This makes the power voltage as low as possible within the normally operational range of the internal circuit (14) and suppresses increase of the gate current, so that unstable operations and current consumption increase of the MOS transistor can be prevented.

Abstract: The protecting element includes an NPN transistor having an emitter connected to an input/output terminal and a collector and a base connected to a ground terminal. The input/output terminal has the possibility of receiving a surge voltage. The input/output terminal, which may be referred to as a pad, is connected to a semiconductor integrated circuit IC to be protected against the surge voltage. The arrangement of the semiconductor integrated circuit IC is not limited to a specific one.

Abstract: An ESD protection device with thicker polysilicon film, an electronic apparatus having the same, and a method for manufacturing the same are provided. The ESD protection device can be a diode or a MOS transistor with a thicker polysilicon film employed in an ESD protection circuit to protect an electronic apparatus. The electronic apparatus includes a substrate having a device area and an ESD protection circuit area. A first polysilicon film of a first thickness is formed on the device area of the substrate, so as to form an electronic device. A second polysilicon film of a second thickness is formed on the ESD protection circuit area, so as to form an ESD protection device. The second thickness, which is preferably about in the range of 100 to 500 nanometers, is thicker than the first thickness.

Abstract: A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.

Abstract: A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a channel region formed in the semiconductor substrate, wherein the source region is connected to a source terminal electrode and the drain region is connected to a drain terminal electrode, wherein the channel region comprises a first narrow width channel region and a second narrow width channel region connected in parallel regarding the source terminal electrode and the drain terminal electrode, and wherein the first narrow width channel region and/or the second narrow width channel region comprise lateral edges narrowing the width of the narrow width channel region is such a way that a channel formation in the narrow width channel region is influenced by a mutually influencing effect of the lateral edges, and a gate electrode arranged above the first and second narrow width channel regions.

Abstract: The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystalline layer, and in particular aspects an entirety of the active region within the crystalline layer is within a single crystal of the crystalline layer. The SRAM constructions can be formed in semiconductor on insulator assemblies, and such assemblies can be supported by a diverse range of substrates, including, for example, glass, semiconductor substrates, metal, insulative materials, and plastics. The invention also includes electronic systems comprising SRAM constructions.

Abstract: A method of constructing a dual metal gate CMOS structure that uses an ultra thin aluminum nitride (AINx) buffer layer between the metal gate and gate dielectric during processing for preventing the gate dielectric from being exposed in the metal etching process. After the unwanted gate metal is etched away, the CMOS structure is annealed. During the annealing, the buffer layer is completely consumed through reaction with the metal gate and a new metal alloy is formed, resulting in only a minimal increase in the equivalent oxide thickness. The buffer layer and gate metals play a key role in determining the work functions of the metal/dielectric interface, since the work functions of the original gate metals are modified as a result of the annealing process.

Abstract: A CMOS device includes a p-channel MOS transistor and an n-channel MOS transistor having a structure formed on a (100) surface of a silicon substrate and having a different crystal surface, a high-quality gate insulation film formed on such a structure by a microwave plasma process, and a gate electrode formed thereon, wherein the size and the shape of the foregoing structure is set such that the carrier mobility is balanced between the p-channel MOS transistor and the n-channel MOS transistor.

Abstract: The present invention provides a method for forming a chip structure with a resistor. A semiconductor substrate is provided and has a surface. A plurality of electronic devices and a resistor is formed on the surface of the semiconductor substrate. A plurality of dielectric layers and a plurality of circuit layers are formed over the semiconductor substrate. The dielectric layers are stacked over the semiconductor substrate and have a plurality of via holes. Each of the circuit layers is disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. A passivation layer is formed over the dielectric layers and the circuit layers. A circuit line is formed over the passivation layer, wherein the circuit line passes through the passivation layer and is electrically connected to the resistor.

Abstract: A semiconductor device has a SALICIDE structure with low leakage currents, while maintaining shallow source and drain regions. A method of manufacturing the semiconductor device includes forming source and drain regions in a first semiconductor layer, the source region and the drain region being separated from each other, forming a gate insulating film between the source region and the drain region on the first semiconductor layer; and forming a gate electrode on the gate insulating film. The method also includes forming a metal silicide layer showing a first compound phase on the source region, the drain region and the gate electrode, and forming a second semiconductor layer on the metal silicide layer showing the first compound phase where the second semiconductor layer is adapted to react with the metal silicide layer.

Abstract: Provided is a field effect transistor. The field effect transistor includes an insulating vanadium dioxide (VO2) thin film used as a channel material, a source electrode and a drain electrode disposed on the insulating VO2 thin film to be spaced apart from each other by a channel length, a dielectric layer disposed on the source electrode, the drain electrode, and the insulating VO2 thin film, and a gate electrode for applying a predetermined voltage to the dielectric layer.

Abstract: Source and drain diffusion layers by an extremely shallower box shaped highly doped impurity distribution that was not obtainable so far by the existent solid phase growing is attained by liquid phase growing with no effects on the gate electrode thereby attaining low consumption power and operation at large current and higher speed in a micro-refined semiconductor device. Contact with inter-connection layer over the entire region of the source and drain diffusion layers is enabled overstriding the gate electrode and without short circuit with the gate electrode by utilizing that the etching selectivity of an insulation film comprising Al as a main constituent atom is extremely higher with respect to an Si oxide film.

Abstract: A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

Abstract: A sensor chip has a piezo-resistive bridge, a temperature resistive bridge, and a multifunctional resistor network that can be used to provide span compensation when operating the piezo-resistive bridge in a constant current mode. In the constant current mode, the multifunctional resistor network can also be used to provide a bias potential to an epitaxial layer of the sensor chip. In a constant voltage mode, the multifunctional resistor network can be used to provide three different gains for a temperature channel that includes the temperature resistive bridge in order to customize the output of the temperature channel for specific operating temperature ranges.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging and a contact area disposed at least partially outside the chamber. The contact area is electrically isolated from nearby electrically conducting regions by way of dielectric isolation trench that is disposed around the contact area. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits.