Abstract: A micromachine for a high-frequency filter which has a high Q value and a higher frequency band is provided.

Abstract: A method of forming a MEMS device includes providing a substructure including a base material and at least one conductive layer formed on a first side of the base material, forming a dielectric layer over the at least one conductive layer of the substructure, forming a protective layer over the dielectric layer, defining an electrical contact area for the MEMS device on the protective layer, and forming an opening within the electrical contact area through the protective layer and the dielectric layer to the at least one conductive layer of the substructure.

Abstract: A substrate structure for a photosensitive chip package includes a plurality of leadframes, which are arranged in a matrix, and a molded resin. Each of the leadframes have a first board and a second board located on a height different from that of the first board, and a chamber is defined upper a central of the plurality of leadframes. And the molded resin is for encapsulating the leadframes, and forming an upper surface and a lower surface, wherein the first boards of the leadframes are exposed from the upper surface of the molded resin.

Abstract: An image sensor package includes a plurality of leadframes, a molded resin, a photosensitive, a plurality of wires and a transparent layer. Each of the leadframes have a first board and a second board located on a height different from that of the first board, and a chamber is defined upper a central of the plurality of leadframes. The molded resin is for encapsulating the leadframes, and is forming an upper surface and a lower surface, wherein the first boards of the leadframes are exposed from the upper surface of the molded resin. The photosensitive chip is mounted onto the upper surface of the molded resin and arranged within the chamber. Each of wires are electrically connected the photosensitive chip to the each second board of the plurality of leadframes. And the transparent resin is covered onto the each first board of the plurality of leadframes.

Abstract: A package structure of a light emitting diode includes a substrate structure, a connection layer, and at least one conductive passage. The substrate structure sequentially includes a conduction board, an insulation layer, and a conductive layer. The insulation layer is configured to electrically insulate the conduction board from the conductive layer, and also to insulate a first portion from a second portion of the conduction board. The substrate structure has an opening to expose the conduction board. The connection layer configured to support and electrically couple to a first electrode of a light emitting diode (LED) is disposed in the opening. The connection layer is also configured to electrically couple to the conduction board and to be electrically insulated from at least one portion of the conductive layer, which is coupled to a second electrode of the LED.

Abstract: A solid state microchannel plate is disclosed comprising a multiplicity of photodetector elements, each using limited gain from a small Geiger mode avalanche and summing the contributions thereof. An array of such multiplicities operates as a pixelated linear or area photodetector. In the preferred embodiment, a multiplicity of passively quenched photodetector elements connect to a common anode, and each photodetector element is passively quenched by its own current-limiting resistor in series with its cathode.

Abstract: Backthinning in an area selective manner is applied to imaging sensors 12 for use in electron bombarded devices. A further arrangement results in an array of collimators 51 aligned with pixels 42 or groups of pixels providing improved image contrast of such image sensor. Provision of a thin P-doped layer 52 on the illuminated rear surface provides both a diffusion barrier resulting in improved resolution and a functional shield for reference pixels. A gradient in concentration of P-doped layer 52 optimizes electron collection at the pixel array.

Abstract: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the creation of a new class of solide state chemical sensors. Detection of the following chemical species was established: hydrogen, deuterium, carbon monoxide, molecular oxygen. The detector (1b) consists of a Schottky diode between an Si layer and an ultrathin metal layer with zero force electrical contacts.

Abstract: A semiconductor device is provided which has high reliability and which can reduce electrical power consumption. The semiconductor device has an element isolation region formed in a semiconductor substrate, and a depth X of the element isolation region and a width Y thereof isolating adjacent doped layers from each other satisfy an equation represented by X/Y=1.33 to 1.67.

Abstract: A semiconductor device having a trench isolation includes a trench formed in a surface of a semiconductor substrate and a buried insulating layer which fills the inside of the trench and has its top surface entirely located above the surface of the semiconductor substrate. A part of the buried insulating layer that protrudes from the surface of the semiconductor substrate has a projecting portion which is located on the surface of the semiconductor substrate and projects outward from a region directly above the trench. The projecting portion has a structure formed of at least two stacked insulating layers. Accordingly, the semiconductor device having the trench isolation can be provided by which a reverse narrow-channel effect can be suppressed and a reliable gate insulating layer can be obtained.

Abstract: The present invention relates to a semiconductor component. The component includes a semiconductor body with a first semiconductor layer of a first conduction type and a second semiconductor layer of a second conduction type. The component includes, in the second semiconductor layer, a first terminal zone of the second conduction type, a drift zone of the second conduction type, a channel zone of the first conduction type, which is formed between the first terminal zone and the drift zone, and a second terminal zone of the second conduction type, which is arranged at a distance from the channel zone in the lateral direction of the semiconductor body. The component also includes a first drive electrode and at least one second drive electrode.

Abstract: Via-shaped copper interconnect lines (2) buried in an interlayer insulating film (8) are connected to gate interconnect lines (1) in the lowermost layer. A copper interconnect line (6) of a shield ring (5) is buried in the interlayer insulating film (8), closer to outside than the copper interconnect lines (2). A silicon nitride film (9) is provided on the via-shaped copper interconnect lines (2), on the copper interconnect line (6) of the shield ring (5), and on the interlayer insulating film (8). Provided on the silicon nitride film (9) is a silicon oxide film (10) which holds therein a fuse line (3) for connecting different ones of copper interconnect lines (2). The silicon oxide film (10) is also provided on the upper surfaces of the fuse line (3) and the aluminum interconnect line (7). A silicon nitride film (11) is provided on the silicon oxide film (10). The silicon nitride film (11) defined over the fuse line (3) is removed, thereby creating an opening (4).

Abstract: The present invention prevents electrostatic discharge damage which may occur when a device chip which has a circuit with fuses mounted thereon is packaged by COG packaging, without increasing an area occupied on the device chip. The height from the chip substrate surface to the top face 138b of the chip terminal 103b formed on the chip substrate surface 136 is formed to be higher than the height from the chip substrate surface to the top face 138a of the fuse terminal 103a. By this, an electrostatic discharge occurs at the chip terminal side when packaged in a COG packaging, so an electrostatic discharge does not occur to the fuse terminal side.

Abstract: A semiconductor device is provided including a first protection film and a second protection film which are stacked in layers in this order on an upper surface of a fuse that includes an upper layer wiring layer. An opening section is formed in the first and second protection films. The opening section exposes an entire portion of the first protection film located directly above the fuse.

Abstract: A semiconductor device is disclosed, which comprises a metal fuse formed in a fuse region defined above an element isolation region of a semiconductor substrate; and an interconnection provided under the metal fuse along the metal fuse in plane pattern, and made of a material hard to be blowout by a laser beam irradiated for blowing the metal fuse.

Abstract: Briefly, a preferred embodiment of the present invention includes a metal-insulator-metal (MIM) capacitor including a bottom layer of conductive material formed by depositing this conductive material on a substrate. A dielectric material is then formed on the bottom conductive layer, wherein the dielectric material is preferably an HfO2 dielectric doped with lanthamide material, more preferably Th doped HfO2 with a Th concentration in the range of 0 to 6% and more particularly substantially 4%. A top conductive layer is formed on top of the dielectric.

Abstract: A method of making an electrically programmable memory element, comprising: providing a first dielectric layer; forming a conductive material over the first dielectric layer; forming a second dielectric layer over the conductive material; and forming a programmable resistance material in electrical contact with a peripheral surface of the conductive material.

Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

Abstract: A composite SOI semiconductor wafer (1) comprises a device layer (2) and a handle layer (3) with a buried oxide layer (4) located between the device and handle layers (2,3). The device and handle layers (2,3) are formed from device and handle wafers (9,10), respectively. A peripheral ridge (14) extending around a first major surface (12) of the device wafer (9) adjacent the peripheral edge (16) thereof is removed by etching a peripheral recess (25) to a depth (d) into the device wafer (9) prior to bonding the device and handle wafers (9,10), in order to avoid an unbonded peripheral portion extending around the composite wafer (1). The depth d to which the peripheral recess (25) is etched is greater than the final finished thickness t of the device layer (2). An oxide layer (22) is grown on the device wafer (9) and a photoresist layer (23) on the oxide layer (22) is patterned to define the peripheral recess (25).

Abstract: An interconnect structure for microelectronic devices includes a plurality of patterned, spaced apart, substantially co-planar, conductive lines, a first portion of the plurality of conductive lines having a first intralayer dielectric of a first dielectric constant therebetween, and a second portion of the plurality of conductive lines having a second intralayer dielectric of a second dielectric constant therebetween. By providing in-plane selectability of dielectric constant, in-plane decoupling capacitance, as between power supply nodes, can be increased, while in-plane parasitic capacitance between signal lines can be reduced.

Abstract: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 &mgr;m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.

Abstract: A semiconductor package having conductive bumps on a chip and a fabrication method thereof are provided. A plurality of the conductive bumps are deposited respectively on bond pads of the chip. An encapsulation body encapsulates the chip and conductive bumps while exposing ends of the conductive bumps. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the exposed ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings for exposing predetermined portions of the conductive traces. The exposed portions of the conductive traces are connected to a plurality of solder balls respectively. The conductive bumps on the bond pads of the chip allow easy positional recognition of the bond pads, making the conductive traces well electrically connected to the bond pads through the conductive bumps and assuring the quality and reliability of the semiconductor package.

Abstract: A package structure includes a substrate, a spacer layer, an integrated circuit, a plurality of wires, and a glue layer. The substrate has an upper surface formed with first connection points, and a lower surface formed with second connection points. The spacer layer is adhered to the upper surface of the substrate by a first adhesive. The integrated circuit has a plurality of bonding pads and is adhered to the spacer layer by a second adhesive. The integrated circuit has an area larger than that of the spacer layer such that a gap is formed between the integrated circuit and the substrate. The wires electrically connect the bonding pads of the integrated circuit to the first connection points of the substrate, respectively. The glue layer is formed on the upper surface of the substrate to encapsulate the integrated circuit and the wires.

Abstract: In an integrated circuit design, flex tape is used to provide signal ingress/egress to/from the integrated circuit design. Various architectures for the signal ingress/egress via flex tape is provided. In one embodiment, coaxial design is provided. In another embodiment, a coplanar waveguide design is provided.

Abstract: Pre-formed underfill compositions utilized in the application of surface mount components, most commonly chip scale packages (CSP's), in electronic devices. The pre-formed underfill of the invention is applied directly to the top of the CSP before the reflow process and softens during reflow to flow across the circuit/board gap. One underfill composition utilized for this method comprises a thermoplastic film system that provides a coating on the component that is smooth and non-tacky. The film may be applied selectively to parts of the CSP such that it overhangs the top of the component and upon reflow flows over the edge of the CSP to form a connection with the substrate. In an alternative embodiment, the underfill coats all or portions of multiple surface mount components.

Abstract: A semiconductor device including: a semiconductor substrate in which an integrated circuit is formed; an insulating layer formed on the semiconductor substrate and having a first surface and a second surface which is higher than the first surface; a first electrode formed to avoid the second surface and electrically connected to the inside of the semiconductor substrate; and a second electrode formed on the second surface and electrically connected to the inside of the semiconductor substrate.

Abstract: A method of fabricating a semiconductor package includes: forming a circuit pattern on a frame; attaching a semiconductor chip onto the circuit pattern; connecting the semiconductor chip and the circuit pattern electrically; forming a molding wrapping the semiconductor chip and the circuit pattern; removing the frame; forming a photoresist film having a through hole on the circuit pattern, the through hole exposing a portion of the circuit pattern; and forming a solder ball on the photoresist film, the solder ball being connected to the portion of the circuit pattern through the through hole.

Abstract: A semiconductor package includes a base plate, at least one semiconductor constructing body which is formed on one surface of the base plate and has a plurality of external connection electrodes formed on a semiconductor substrate, an insulating layer which is formed on one surface of the base plate around the semiconductor constructing body, upper interconnections which are formed on the insulating layer and each includes at least one interconnection layer, at least some of the upper interconnections are connected to the external connection electrodes of the semiconductor constructing body, lower interconnections which are formed on the other surface of the base plate and each includes at least one interconnection layer, and at least some of the lower interconnections which are electrically connected to the upper interconnections.

Abstract: With the use of stacked modules, a system and method for point to point addressing of multiple integrated memory circuits is provided. A single memory expansion board is populated with stacked modules of integrated circuits. The single memory expansion board is located at the terminus of a transmission line, thus, effectively placing at a relative single point in the addressing system, added memory capacity that would otherwise have required multiple memory expansion boards and, consequently, a longer bus. Therefore, signal degradation issues are mitigated and the system has improved tolerance for higher signal speeds with added memory capacity. In a preferred embodiment, a four DIMM socket memory access bus that does not employ stacking is replaced with a single DIMM socket bus that supports stacking up to four high on a single DIMM.

Abstract: Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming one or more layers of compliant material on at least a portion of the top surface of a substrate, said substrate, curing at least a portion of the semiconductor device, selectively removing a portion of the one or more layers of compliant material, and assembling the substrate into a stacked semiconductor device.

Abstract: A memory chip module includes multiple stacks of memory chips arranged on a base panel. The chip stacks desirably are arranged in rows symmetrical about a central plane and define a channel in a central region of the base panel. Control chips such as a register chip associated with the memory chips in the stacks can be provided in this central region of the base panel. Desirably, the base panel is surface-mountable on a circuit board. The module provides high memory chip packing density, effective cooling and short, balanced signal lines between the control chip and the memory chip stacks.

Abstract: In an integrated circuit having a first circuit part and at least one second circuit part, which is assigned to a specific functionality of the first circuit part, on one and the same silicon wafer, of which the first circuit part and the at least one circuit part are arranged in non-overlapping, mutually separate regions of the silicon wafer and are connected to one another via connecting elements or lines, during the fabrication, for each exposure plane, with the exception of the exposure plane used for the fabrication of the connecting elements or lines, use is made in each case of a first exposure mask intended for the first circuit part and a second exposure mask intended for the second circuit part. These first and second exposure masks may be arranged on a common reticle for a respective exposure plane.

Abstract: A wired circuit board that can control characteristic impedance at connection points between wires of a suspension board with circuit and terminal portions of the wired circuit board connected thereto with a simple structure, to improve signal transmission efficiency even for fine pitch wiring or for high frequency signal. To provide this wired circuit board, a relay flexible wiring circuit board 1 is formed by a first wired circuit board 14 comprising a first metal substrate 16, a first insulating base layer 17, a first conductor layer 18 and a first insulating cover layer 19 which is substantially identical in layer structure with the suspension board with circuit 3 and a second wired circuit board 15 connected with the first wired circuit board 14 for connecting with a control circuit board 4.

Abstract: A memory card for being electrically connected to an electrical device. The memory card includes a substrate, and at least one memory chip. The substrate is formed with a plurality of contact leads, which is electrically connected to the electrical device when the substrate is inserted into the electrical device. The plurality of contact leads includes a long contact lead and a short contact lead to indicate an inserting direction of the substrate into the electrical device. The memory chip is mounted to the substrate and electrically connected to the plurality of contact leads.

Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a wiring layer on a semiconductor substrate having an integrated circuit and a pad electrically connected to the integrated circuit, the wiring layer being electrically connected to the pad, (b) forming a resin layer covering the wiring layer, (c) forming a first concave portion at an area of the resin layer, the area overlapping the wiring layer, by a first process, (d) forming a through-hole in the resin layer by removing a bottom of the first concave portion by a second process, the second process differing from the first process, and forming a second concave portion in the wiring layer in such a way that an angle between an osculating plane at any point of a surface of the second concave portion and a top surface of the wiring layer, with the angle being defined outside the second concave portion is 90° or more and (e) providing an external terminal in the second concave portion of the wiring layer.

Abstract: A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.

Abstract: A semiconductor device includes a semiconductor substrate with a through hole formed therein, a first insulating film formed inside the through hole, and an electrode formed on an inner side of the first insulating film inside the through hole. The first insulating film at the rear surface side of the semiconductor substrate protrudes beyond the rear surface, and the electrode protrudes on both the active surface side and the rear surface side of the semiconductor substrate. An outer diameter of a protruding portion on the active surface side is larger than an outer diameter of the first insulating film inside the through hole, and a protruding portion on the rear surface side protrudes further beyond the first insulating film to have a side surface thereof exposed. The semiconductor device has improved connectivity and connection strength and, in particular, has excellent resistance to shearing force when used in three-dimensional packaging technology.

Abstract: In one embodiment, solder balls of multiple sizes may be used to couple one or more semiconductor structures to an electrical device. For example, a printed circuit board structure may support one or more integrated circuit packages includes at least one package with a substrate having a bottom surface. The structure may also include a printed circuit board that includes: (1) one or more first regions each having a top surface opposite the bottom surface of the substrate and separated from the bottom surface by a first distance; and (2) one or more second regions each having a top surface opposite the bottom surface of the substrate and separated from the bottom surface of the substrate by a second distance, the top surface of the second region being closer to the bottom surface of the substrate than the top surface of the first region such that the second distance is smaller than the first distance.

Abstract: A method for manufacturing a semiconductor device includes (a) forming electrical interconnections over a surface of a semiconductor substrate having integrated circuits, (b) providing a plurality of bonding pads disposed on the surface of the semiconductor substrate, (c) electrically connecting the electrical connections to respective bonding pads of the plurality of bonding pads, (d) electrically connecting the plurality of bonding pads to each of the integrated circuits, (e) forming resin layers so as to cover the electrical interconnections, (f) forming concave portions by a first process, each of the concave portions being disposed in a corresponding portion of the resin layers that cover the electrical interconnections, (g) curing the resin layers having the concave portion, (h) forming through-holes by removing bottoms of the concave portions by a second process that differs from the first process and (i) forming external connection terminals, each being disposed on a corresponding area of the electric

Abstract: To reduce the size and the power consumption of a semiconductor device.

Abstract: An improved die stacking scheme is provided. In accordance with one embodiment of the present invention, a multiple die semiconductor assembly is provided comprising a substrate, first and second semiconductor dies, and at least one decoupling capacitor. The first semiconductor die defines a first active surface. The first active surface includes at least one conductive bond pad. The second semiconductor die defines a second active surface, the second active surface includes at least one conductive bond pad. The first semiconductor die is interposed between the substrate and the second semiconductor die such that a surface of the second semiconductor die defines an uppermost die surface of the multiple die semiconductor assembly and such that a surface of the first semiconductor die defines a lowermost die surface of the multiple die semiconductor assembly. The decoupling capacitor is secured to the uppermost die surface and is conductively coupled to at least one of the first and second semiconductor dies.

Abstract: A tape package in which a test pad is formed on a reverse surface is provided. The test pad is disposed on a reverse surface of a base film through a through hole of the base film. Accordingly, shapes of the test pads are standardized so that a universal probe card can be used. A pitch between the test pads is wide so that the accuracy in an electric test of the tape package is increased. A total length of the tape package is reduced.

Abstract: A semiconductor device includes a semiconductor substrate including an integrated circuit and an electrode. A resin layer is provided on a side of the semiconductor substrate where the electrode is formed and a wiring layer is formed on an area reaching from the electrode to a top of the resin layer. The electrode has a first rim part facing a periphery of the semiconductor substrate and a second rim part facing a center region of the semiconductor substrate. The resin layer is formed so as to overlap the second rim part, leaving out an area from the periphery of the semiconductor substrate to the first rim part of the electrode.

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract: Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described.

Abstract: A package substrate that is adapted to receive at least one subject integrated circuit having a subject contact pattern, where the subject integrated circuit is selected from a design set of integrated circuits. The package substrate has an upper surface with electrically conductive bump contacts in a bump array. The bump array is configured to provide electrical connections to all possible integrated circuit contact patterns in the design set of integrated circuits. A lower surface of the package substrate has electrically conductive ball contacts in a ball array. One each of the bump contacts is electrically connected to one each of the ball contacts through the package substrate. An electrically conductive ground plane is disposed between the upper surface and the lower surface. Grounding contacts are disposed adjacent the ball contacts, where the grounding contacts are electrically connected to the ground plane.

Abstract: Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary embodiment illustrated the use of chip-scale processes for interconnecting discrete integrated circuits.

Abstract: Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming one or more layers of compliant material on at least a portion of the top surface of a substrate, said substrate, curing at least a portion of the semiconductor device, selectively removing a portion of the one or more layers of compliant material, and assembling the substrate into a stacked semiconductor device.

Abstract: Semiconductor devices and methods of forming a contact in semiconductor devices are provided. A semiconductor substrate is provided with a cell array region and a peripheral circuit region. A polysilicon layer is formed on the semiconductor substrate in the peripheral circuit region. A metal layer is formed on the polysilicon layer. A metal pattern is formed by removing a portion of the metal layer. The metal pattern is annealed to form a local silicide region in the polysilicon layer. A capacitor is formed on the semiconductor substrate in the cell array region after the local silicide region is formed in the polysilicon layer.

Abstract: A method and structure for semiconductor structure includes a plurality of adjacent wiring levels, conductors within each of the wiring levels, and liners at least partially surrounding each of the conductors. The liners of adjacent wiring levels are made of different materials which have different etching characteristics and are selectively etchable with respect to one another. The liners can be tantalum, tungsten, etc. The liners surround at least three sides of the conductors. Each of the wiring levels has a first insulator layer which has a first dielectric material. The liners and the conductors are positioned within the first dielectric material. A second insulator layer has a second dielectric material over the first insulator layer. The first dielectric material has a lower dielectric constant than the second dielectric material. The first dielectric material can be silicon dioxide, fluorinated silicon dioxide (FSD), microporous glasses, etc.