Abstract: a method for separating particulate matter from a fluid, using apparatus which includes a container and cover, a filter assembly positioned in a housing atop the cover and suitable for collecting particulate matter in the fluid on a collection surface, and a dispersing element fixed relative to the cover. The cover has a portion that is fixed in a first position and freely rotatable in a second position. The specimen is placed in the container, and a mixer apparatus rotates the container in relation to the cover to disperse the particulate matter throughout the fluid. Upon deactivation of the mixer apparatus, a fluid sample including dispersed particulate matter is drawn through the filter assembly to capture a substantially uniform layer of particulate matter on the collection surface. The housing is then opened to expose the layer of particulate matter, which is then transferred to a microscope slide.

Abstract: The present invention provides a miniaturized integrated nucleic acid diagnostic device and system. The or more sample acquisition and preparation operations, in combination with one or more sample analysis operations. For example, the device can integrate several or all of the operations involved in sample acquisition and storage, sample preparation and sample analysis, within a single integrated unit. The device is useful in a variety of applications, and most notably, nucleic acid based diagnostic applications and de novo sequencing applications.

Abstract: The invention provides a method for generating and identifying antibodies directed against a B7 antigen having SEQ ID NO. 8 or a fragment of SEQ ID NO. 8, which antibodies inhibit B cells from binding CD28, comprising immunizing an animal with the B7 antigen so as to produce the antibodies; and screening the antibodies for antibodies that bind B7 and inhibit CD28 binding to B cells.

Abstract: The present invention can improve and/or modify data retention lifetimes for ferroelectric devices by baking them prior to or during packaging. A ferroelectric device is programmed to a particular state and then baked for a selected period of time at a selected temperature. This pre-baking or imprinting causes the device to be imprinted or have a preference for the particular state and reduces loss of signal margin over time, thereby at least partially preserving data retention capabilities.

Abstract: The present invention is directed to a system, method and software product for creating a predictive model of the endpoint of etch processes using Partial Least Squares Discriminant Analysis (PLS-DA). Calibration data is collected from a calibration wafer using optical emission spectroscopy (OES). The data may be non-periodic or periodic with time and periodic signals may be sampled synchronously or non-synchronously. The OES data is arranged in a spectra matrix X having one row for each data sample. The OES data is processed depending upon whether or not it is synchronous. Synchronous data is arranged in an unfolded spectra matrix X having one row for each period of data samples. A previewed endpoint signal is plotted using wavelengths known to exhibit good endpoint characteristics. Regions of stable intensity values in the endpoint plot that are associated with either the etch region or the post-etch region are identified by sample number.

Abstract: A method and apparatus for burning in a semiconductor wafer having a plurality of active devices utilizes temporary conductive interconnect layers to separately couple at least a portion of the anodes of the active devices together as well as at least a portion of the cathodes of the devices together. A simplified probed pad, having a reduced number of contacts may then be utilized to apply a substantially constant voltage or current to the devices. The temporary conductive interconnect layer may be patterned to include device level resistors or array level resistors that may be used to mitigate the effects of short circuits or open circuits on the processing of the devices.

Abstract: A method and apparatus for identifying individual semiconductor die that originate from a semiconductor substrate containing a plurality of die is disclosed. Aspects of the invention include physically associating a respective die ID with at least a portion of individual die on the wafer, and storing the die ID and wafer fabrication information in a database. During subsequent testing of the die, the die ID is used to retrieve the wafer fabrication information from the database, thereby aiding a determination as to a cause of a failure of the die.

Abstract: A method is disclosed for processing a silicon workpiece including a hybrid thermometer system for measuring and controlling the processing temperature where fabrication materials have been or are being applied to the workpiece. The hybrid thermometer system uses optical reflectance and another thermometer technique, such as a thermocouple and/or a pyrometer. Real-time spectral data are compared to values in a spectrum library to determine the “surface conditions”. A decision is then made based on the surface conditions as to how the temperature is measured, e.g., with optical reflectance, a pyrometer, or a thermocouple, and the temperature is measured using the appropriately selected technique. Utilizing the hybrid thermometer system, the temperature of a silicon workpiece may be accurately measured at low temperatures while accounting for the presence of fabrication materials.

Abstract: Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and protective layer are each formed to precise tolerances. The invention also includes methods for forming a calibration standard for semiconductor metrology tools.

Abstract: A plurality of MEMS devices that can be easily configured to impart extended ranges of rotational and/or translational motion. The MEMS devices comprise a micro-electromechanical building block including a bendable member having a first end connectable to a support structure, and a straight rigid member having a first end connected to a second end of the bendable member. In the event the bendable member is in a straight condition, the rigid member extends from the second end of the bendable member toward the support structure. Further, the bendable member has a predetermined length, and the rigid member has a length at least within a range from one half to the full predetermined length of the bendable member to allow a free end of the rigid member to undergo extended rotational and/or translational motion in response to a displacement of the bendable member.

Abstract: A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.

Abstract: A device transfer method includes the steps of: covering a plurality of devices, which have been formed on a substrate, with a resin layer; forming electrodes in the resin layer in such a manner that the electrodes are connected to the devices; cutting the resin layer, to obtain resin buried devices each containing at least one of the devices; and peeling the resin buried devices from the substrate and transferring them to a device transfer body. This device transfer method is advantageous in easily, smoothly separating devices from each other, and facilitating handling of the devices in a transfer step and ensuring good electric connection between the devices and external wiring, even if the devices are fine devices.

Abstract: A broad crystal display panel having a color filter substrate is supported by supporting nails and the middle portion of a supporting span is pressed by a loading bar. From this state, the supporting nails are removed to release the supporting, and subsequently the supporting nails are also removed to release the supporting the color filter substrate. While preventing the displacement between the color filter substrate and a TFT array substrate, the color filter substrate and the TFT array substrate can be stacked with a specified distance.

Abstract: By using a mask 4, a first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, striped-shaped, or grid-like structure, so as to provide a trench/post. Thus, without removing the mask 4 formed on a top surface of the upper layer of the post, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, with a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. The second Group III nitride compound layer 32 does not grow epitaxially on the mask 4. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth and a region having less threading dislocations can be formed in the buried portion of the trench.

Abstract: A preferred condition for forming a Group III nitride compound semiconductor layer on a substrate by a sputtering method is proposed. When a first Group III nitride compound semiconductor layer is formed on a substrate by a sputtering method, an initial voltage of a sputtering apparatus is selected to be not higher than 110% of a sputtering voltage.

Abstract: Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises pretreating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures.

Abstract: The invention relates to a process for manufacturing a light sensor device in a standard CMOS process, including at least the following phases: implanting active areas on a semiconductor substrate to obtain at least a first, a second and a third integrated region of corresponding photosensors; forming a stack of layers of different thickness and refractive index layers over the photosensors to provide an interferential filter for said photosensors. The stack is obtained by a deposition of a first oxide stack including a first, a second and a third oxide layer over at least one photosensor; moreover, this third oxide layer is obtained by a deposition step of an protecting undoped premetal dielectric layer.

Abstract: The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: A method for forming a MOSFET having greatly reduced leakage current between the gate electrode and the channel, source and drain regions. The method requires the use of gate electrode materials having lower electron affinities than the channel, source and drain regions. Gate electrode materials with negative electron affinities will also achieve the objectives of the invention. The use of these gate electrode materials enables the band structures of the gate electrode and the other regions to be aligned in a manner that eliminates tunneling states for carriers tunneling between the gate and the body of the device.

Abstract: A method and apparatus for reducing or eliminating the formation of air pockets or voids in a flowable material provided in contact with at least one substrate. The flowable material is provided in a non-horizontal direction and flows from a lower portion to an upper portion. As a result, the flowable material is provided uniformly with a single, uniform flow front due to gravity acting thereon and gravity thereby substantially preventing voids and air pockets from forming in the flowable material. In one embodiment, the at least one substrate is provided in the cavity of a transfer mold in which the cavity is filled from a gate at a lower portion of the cavity to a vent at an upper portion of the cavity. In another embodiment, a bumped semiconductor device is attached to a substrate having a gap therebetween, in which the gap is oriented longitudinally perpendicular to a horizontal plane so that the flowable material may fill the gap in a vertical direction.

Abstract: A semiconductor package and method for manufacturing the same is disclosed. The semiconductor package comprises a semiconductor chip, a circuit board, an electrical connection means, an encapsulation material and a plurality of conductive balls. The semiconductor chip has a first surface and a second surface. A plurality of input and output pads are formed on one of the first and second surfaces. The circuit board comprises a thin film having a first surface and a second surface and being provided with a center hole in which the semiconductor chip is positioned, a plurality of circuit patterns being formed on the first surface of the thin film and including a plurality of bond fingers and ball lands, and a cover coat covering the circuit board except for the bond fingers and the ball lands. The electric connection means electrically connects the input and output pads of the semiconductor chip with the bond fingers of the circuit board.

Abstract: A method to realize low-profile semiconductor devices by grinding a resin sealed block and realize level grinding by eliminating warpage of the resin sealed block. Semiconductor devices 10 are produced by step (B) in which multiple semiconductor chips 11 are mounted face down onto the surface of substrate 12, step (C) in which molding resin 13 is injected onto substrate 12 in order to form resin sealed block 18 in which multiple semiconductor chips 11 are sealed, step (E) in which resin sealed block 18 is cut halfway from the side of substrate 12, and step (F) in which resin sealed block 18 is ground from the side of molding resin 13 in order to separate it into individual semiconductor devices 10.

Abstract: A method of fabricating BGA (Ball Grid Array) packages is proposed, which utilizes a specially-designed carrier to serve as an auxiliary tool to package semiconductor chips on substrates. The carrier is formed with a plurality of cavities respective for receiving a substrate and in communication with an injection gate, such that no injection gate is required on the substrate, thereby not restricting the trace routability on the substrate. Moreover, a two-piece type of mold is allowed being used to form a number of encapsulation bodies at one time, making the fabrication more productive and cost-effective. Furthermore, the proposed BGA fabrication method can be implemented without having to provide an air outlet in the substrate but allows the resulted encapsulation body to be free of voids to assure the quality of the packages. The proposed BGA fabrication method is therefore more advantageous to use than the prior art.

Abstract: A semiconductor wafer and a substrate are positioned facing each other, and electrode pads of individual semiconductor chips and connecting electrode pads of package bases are bonded simultaneously. The semiconductor wafer and the substrate are cut at the same time and divided into semiconductor chips. After expanding spaces between the divided semiconductor chips a predetermined width in an expanding process, a sealing resin is applied so that the large number of semiconductor chips and package bases are sealed with the resin at the same time. Then the semiconductor chips are cut and divided into separate pieces. Thus, semiconductor devices sealed with a resin are formed.

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package includes a circuit substrate including a conductive region. A semiconductor die is on the circuit substrate. The semiconductor die includes an edge and a recess at the edge. A solder joint couples the semiconductor die and the conductive region through the recess.

Abstract: A stress-relieving heatsink structure and method of forming thereof for an electronic package, for instance, that including a semiconductor chip package which is mounted on a wired carrier, such as a circuitized substrate. The heatsink structure is constituted from a plurality of base structures which are joined along slits so as to impart a degree of flexibility to the electronic package inhibiting the forming of stresses tending to cause delamination of the package components.

Abstract: A semiconductor device assembly including a semiconductor device having a plurality of bond pads on the active surface thereof and a lead frame having a portion of the plurality of lead fingers of the lead frame located below the semiconductor device in a substantially horizontal plane and another portion of the plurality of lead fingers of the lead frame located substantially in the same horizontal plane as the active surface of the semiconductor device. Both pluralities of lead fingers of the lead frame having their ends being located substantially adjacent the peripheral sides of the semiconductor device, rather than at the ends thereof.

Abstract: The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.

Abstract: A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.

Abstract: A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.

Abstract: A metal induced crystallization process is provided which employs an amorphous silicon film precursor deposited by physical vapor deposition, wherein the precursor film does not readily undergo crystallization by partial solid phase crystallization. Using this physical vapor deposition amorphous silicon precursor film, the amorphous silicon film is transformed to polysilicon by metal induced crystallization wherein the crystalline growth occurs fastest at regions that have been augmented with a metal catalyst and proceeds extremely slowly, practically zero, at regions which bear no metal catalyst. Accordingly, by use of the physical vapor deposition amorphous silicon precursor film in the process of the present invention, the metal induced crystallization process may take place at higher annealing temperatures and shorter annealing times without solid phase crystallization taking place.

Abstract: A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.

Abstract: According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited over the substrate and the transistor gate. The conformal layer may, for example, be silicon nitride. An opening is then etched in the conformal layer. Next, a base layer is deposited on the conformal layer and in the opening. The base layer may, for example, be silicon-germanium. According to this exemplary embodiment, an emitter may be formed on the base layer in the opening. Next, the base layer is removed from the conformal layer. The conformal layer is then etched back to form a spacer adjacent to the transistor gate. In one embodiment, a structure is fabricated according to the above described exemplary method.

Abstract: An improved TOL process with a partial lithography-assisted sacrifcial oxide strip to prevent arsenic out-diffusion from polysilicon studs during gate oxidation. The invention prevents arsenic out-diffusion during gate oxidation from polysilicon studs by completely covering polysilicon studs with an oxide layer during gate oxidation, therby mantaining nitrogen amounts in the thin gate oxide regions, and hence, maintaining gate oxide thickness and avoiding any increase in Vt's for thin gate devices.

Abstract: The present invention relates to a method of manufacturing a semiconductor device.

Abstract: A method for manufacturing, in a monolithic circuit including a substrate, an inductance and a through via, including the step of forming, from a first surface of the substrate, at least one trench according to the contour of the inductance to be formed; forming by laser in the substrate a through hole at the location desired for the via; simultaneously insulating the surface of the trench and of the hole; and depositing a conductive material in the trench and at least on the hole walls.

Abstract: A process of fabricating high dielectric constant MIM capacitors. The high dielectric constant MIM capacitors are for both RF and analog circuit applications. For the high dielectric constant MIM capacitors, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of artificial layers. Dielectric constants near 900 can be achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques are employed for the layer growth processes.

Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.

Abstract: Using a rapid thermal oxidation device, the top and side surfaces of a floating gate electrode are oxidized by In Situ Steam Generation (ISSG), wherein oxygen to which about 0.5 to 33% hydrogen has been added is introduced directly into a chamber with a temperature of approximately 900 to 1100° C. and a pressure of approximately 1,000 to 2,000 Pa, in order to generate water vapor from the introduced hydrogen and oxygen on a heated semiconductor substrate. Thus, an insulating film made of silicon oxide is formed on the surface of the floating gate electrode.

Abstract: A method of fabricating a semiconductor device includes the steps of forming a first film of silicon nitride or silicon oxynitride on a polysilicon layer, forming a second film of silicon oxide on the first film by chemical vapor deposition, and oxygen-annealing the second film to form a tunnel oxide film. The presence of the silicon nitride or silicon oxynitride film enables an annealing process with a high oxidation capability to be used without oxidizing the polysilicon layer. The leakage of unwanted current through the tunnel oxide film can thereby be reduced, improving the data retention characteristics of devices such as flash memories.

Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Abstract: A method of forming an isolation trench in a semiconductor includes forming a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. The method also includes forming a second isolation trench portion within and extending below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.

Abstract: On a semiconductor substrate having a gate electrode and an LDD layer formed thereon, an SiN film to be a silicide block is formed. An opening communicating with the LDD layer is provided for the SiN film. Impurities are introduced into the LDD layer through the opening to form a source/drain layer, and the surface thereof is silicided to form a silicide film. Next, an interlayer insulation film of SiO2 is formed and then etched under a condition of an etching rate of SiO2 higher than that of SiN to form a contact hole reaching the LDD layer from the upper surface of the interlayer insulation film via the opening.

Abstract: There is provided a method for fabricating a semiconductor device involving the formation of two or more oxide films having different etching properties. A multilayer-film sidewall including a first oxide film such as an NSG film, a TEOS film, or a HTO film and a second oxide film such as a BPSG film or a PSG film is formed over the side surfaces of a gate electrode. After the multilayer-film sidewall is used as an implantation mask for forming the source and drain of a MIS transistor, wet etching is performed by using an aqueous solution mixture containing a hydrofluoric acid and an inorganic acid (a hydrochloric acid, a sulfuric acid, or the like) in selectively removing the second oxide film. This increases the etching selectivity between the individual oxide films and allows the removal of only the upper-layer second oxide film.

Abstract: Semiconductor device fabrication methods are provided in which a carbon-containing region is formed in a wafer to inhibit diffusion of dopants during fabrication. Front-end thermal processing operations, such as oxidation and/or anneal processes, are performed at high temperatures for short durations in order to mitigate out-diffusion of carbon from the carbon-containing region, such that carbon remains to inhibit or mitigate dopant diffusion.

Abstract: A vertical nanotube transistor and a process for fabricating the same. First, a source layer and a catalyst layer are successively formed on a substrate. A dielectric layer is formed on the catalyst layer and the substrate. Next, the dielectric layer is selectively removed to form a first dielectric mesa, a gate dielectric layer spaced apart from the first dielectric mesa by a first opening, and a second dielectric mesa spaced apart from the gate dielectric layer by a second opening. Next, a nanotube layer is formed in the first opening. Finally, a drain layer is formed on the nanotube layer and the first dielectric mesa, and a gate layer is formed in the second opening. The formation position of the nanotubes can be precisely controlled.

Abstract: According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.

Abstract: The present invention provides techniques to fabricate high dielectric MIM storage cell capacitors. In one embodiment, this is accomplished by forming a silicon contact is then formed to electrically connect the formed bottom electrode layer in the container with the at least one associated transistor device. A titanium nitride barrier layer is then formed over the silicon contact. An oxygen barrier layer including platinum stuffed with silicon oxide is then formed over the titanium nitride layer and below the bottom electrode layer. A bottom electrode layer is then formed using platinum over interior surfaces of a container formed relative to at lest one associated transistor device on a silicon substrate. Further, a high dielectric insulator layer is formed over the bottom electrode layer. A top electrode layer is then formed over the high dielectric insulator layer.

Abstract: Multiple damascene layers in integrated circuits can form several advantageous designs or components that may lower cost or increase performance of certain designs. In embodiments for power bus signals, multiple damascene layers may be used to form traces with increased power capacity and lower cost. In other embodiments, multiple damascene layers may be used to form components such as capacitors and inductors with increased performance.