Patents Issued in December 14, 2004
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Patent number: 6830985Abstract: The present invention provides a method for producing a bonded dielectric separation wafer in which an auto-alignment can be carried out with reference to the orientation flat of a supporting substrate wafer after the wafer bonding step, and also an apparatus to be used for bonding wafers. When wafers are placed one upon another, the silicon wafers 10, 20 are irradiated with transmission light in order to capture the transmission images thereof. The positions of the pattern of dielectric isolation grooves 13 in the silicon wafer 10 and the orientation flat 20a of the silicon wafer 20 are determined from the images and the bonding position of the wafers 10, 20 is determined based on the determined positions. Auto-alignment of the bonded dielectric separation wafer can thereby be carried out with reference to the orientation flat 20a of the silicon wafer 20 after the wafer bonding step.Type: GrantFiled: October 24, 2002Date of Patent: December 14, 2004Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Hiroyuki Oi, Hitoshi Okuda
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Patent number: 6830986Abstract: An SOI semiconductor device includes at least an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; and an active semiconductor element formed on the semiconductor layer. The active semiconductor element is formed in an element formation region surrounded by an isolating region for isolating the semiconductor layer in a form of an island. A gettering layer containing a high concentration impurity is formed in a portion of the semiconductor layer excluding the element formation region in which the active semiconductor element is formed, and the gettering layer is not formed in the element formation region in which the active semiconductor element is formed.Type: GrantFiled: January 17, 2003Date of Patent: December 14, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsushige Yamashita, Hisaji Nisimura, Hiromu Yamazaki, Masaki Inoue, Yoshinobu Satoh
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Patent number: 6830987Abstract: An SOI semiconductor and method for making the same includes a substrate and dielectric support structures that support a silicon body above the substrate. This creates a void underneath the silicon body and thereby reduces the capacitance between the source/drain regions on body and the substrate.Type: GrantFiled: June 13, 2003Date of Patent: December 14, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Mario P. Pelella, Srinath Krishnan, William G. En, Witold P. Maszara
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Patent number: 6830988Abstract: An isolation structure having both deep and shallow components is formed in a semiconductor workpiece by etching the workpiece to define raised precursor active device regions separated by sunken precursor isolation regions. An oxidation mask is patterned to expose the precursor isolation regions, and the unmasked precursor isolation regions are exposed to oxidizing conditions to grow field oxides as the deep isolation component. Thermal growth of these field oxides creates topography which includes shallow recesses adjacent to the raised precursor active device regions. Deposition of conformal dielectric material such as high density plasma (HDP) deposited silicon oxide over the entire surface and within the recesses creates the shallow isolation component. Following planarization of the conformal dielectric material, fabrication of the device is completed by introducing conductivity-altering dopant into raised precursor active device regions.Type: GrantFiled: August 27, 2002Date of Patent: December 14, 2004Assignee: National Semiconductor CorporationInventor: Albert Bergemont
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Patent number: 6830989Abstract: Handling of each arrayed component is implemented in pickup operation within a movement range of a supporting body against the size of a supporting region of the arrayed component smaller than that in the prior art. Each component supported on a supporting body in array is moved to a pickup position with a movement of the supporting body in X and Y two component array directions, and is fed to pickup operation by a tool with push-up operation by a push-up pin involved, in which after each unit region (D1 to D4) dividedly set around the pickup position of the supporting body is positioned at a pickup standby position by rotation of the supporting body in a switching manner, the component in the positioned unit region is moved in each component array direction of the supporting body and fed to pickup operation in sequence.Type: GrantFiled: February 26, 2002Date of Patent: December 14, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Shida, Shinji Kanayama, Takashi Shimizu, Kenji Takahashi, Ryoji Inutsuka, Hiroyuki Yoshida
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Patent number: 6830990Abstract: Various embodiments are methods and apparatuses for different steps in separating wafers into multiple wafer die. Some embodiments are adapted for dicing wafers having a front side and a back side, where the front side has processed devices, such as MEMS devices.Type: GrantFiled: August 7, 2002Date of Patent: December 14, 2004Assignee: LightConnect, Inc.Inventors: Kenneth Honer, Aaron Parker, Daniel G. Parker
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Patent number: 6830991Abstract: A gettering layer for capturing heavy metal impurities is formed on a wafer back surface. Immediately before formation of a metal wiring layer, a semiconductor device is subjected to first heat treatment at a predetermined temperature so that the heavy metal impurities are heat-diffused and captured in the gettering layer. The gettering layer with the heavy metal impurities captured therein is removed before second heat treatment following the first heat treatment. After removing the gettering layer, a first amorphous silicon layer as a filler for filling a contact hole is deposited on a wafer device surface including a device active region while a second amorphous silicon layer having an impurity concentration equal to that of the first amorphous silicon layer is simultaneously deposited on the wafer back surface.Type: GrantFiled: July 2, 2002Date of Patent: December 14, 2004Assignees: NEC Corporation, Hitachi, Ltd., NEC Electronics CorporationInventor: Kanta Saino
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Patent number: 6830992Abstract: Disclosed herein are (1) a light-emitting semiconductor device that uses a gallium nitride compound semiconductor (AlxGa1−xN) in which the n-layer of n-type gallium nitride compound semiconductor (AlxGa1−xN) is of double-layer structure including an n-layer of low carrier concentration and an n+-layer of high carrier concentration, the former being adjacent to the i-layer of insulating gallium nitride compound semiconductor (AlxGa1−xN); (2) a light-emitting semiconductor device of similar structure as above in which the i-layer is of double-layer structure including an iL-layer of low impurity concentration containing p-type impurities in comparatively low concentration and an iH-layer of high impurity concentration containing p-type impurities in comparatively high concentration, the former being adjacent to the n-layer; (3) a light-emitting semiconductor device having both of the above-mentioned features and (4) a method of producing a layer of an n-type gallium nitride compound semicType: GrantFiled: October 2, 2000Date of Patent: December 14, 2004Assignees: Toyoda Gosei Co., Ltd., Nagoya University, Japan Science and Technology CorporationInventors: Katsuhide Manabe, Akira Mabuchi, Hisaki Kato, Michinari Sassa, Norikatsu Koide, Shiro Yamazaki, Masafumi Hashimoto, Isamu Akasaki
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Patent number: 6830993Abstract: Systems and methods for reducing a surface roughness of a polycrystalline or single crystal thin film produced by the sequential lateral solidification process are disclosed.Type: GrantFiled: February 4, 2002Date of Patent: December 14, 2004Assignee: The Trustees of Columbia University in the City of New YorkInventors: James S. Im, Robert S. Sposili, Mark A. Crowder
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Patent number: 6830994Abstract: The number of grains in active regions of devices can be made uniform by making the grains of crystalline semiconductor films, obtained by thermal crystallization using a metal element, smaller. The present invention is characterized in that a semiconductor film is exposed within an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma, and then thermal crystallization using a metal element is performed. The concentration of crystal nuclei1 generated is thus increased, making the grain size smaller, by performing these processes. Heat treatment may also be performed, of course, after exposing the semiconductor film, to which the metal element is added, to an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma.Type: GrantFiled: March 6, 2002Date of Patent: December 14, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Mitsuki, Takeshi Shichi, Shinji Maekawa, Hiroshi Shibata, Akiharu Miyanaga
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Patent number: 6830995Abstract: Provided is a method of heating a semiconductor substrate having a surface of a III-V compound semiconductor containing phosphorus as a group V constituent element. The method comprises the steps of: (a) providing an alloy in a heating furnace, the alloy including tin, indium, and phosphorus as main constituents; and (b) raising a temperature of the article in an atmosphere containing vapor of phosphorus supplied from the alloy.Type: GrantFiled: February 26, 2003Date of Patent: December 14, 2004Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yasuhiro Iguchi, Takashi Ishizuka
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Patent number: 6830996Abstract: The present disclosure provides a method is provided for fabricating a metal oxide semiconductor (MOS) gate stack on a semiconductor substrate. The method includes generating moisture on a surface of the semiconductor substrate to form an oxide layer less than 10 nanometers thin and performing a nitridation process on the thin oxide layer. After the nitridation process, the method includes performing a polysilicon deposition process on the surface of the semiconductor substrate, doping the polysilicon deposition to a level of 5×1015 at/cm3, and cleaning the doped polysilicon with a light ammonia solution.Type: GrantFiled: March 24, 2003Date of Patent: December 14, 2004Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Lin Chen, Tze Liang Lee, Shih-Chang Chen
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Patent number: 6830997Abstract: Semiconductor devices and methods for forming semiconductor devices are disclosed. In a disclosed method, a gate of a semiconductor device is formed by separately forming a lower gate and an upper gate electrode on a semiconductor substrate. A lower gate polysilicon layer is first formed on the semiconductor substrate and selectively removed to form the lower gate electrode. LDD regions are formed on opposite sides of the lower gate electrode. A nitride film is formed and etched to form sidewalls of the lower gate electrode. Source and drain regions are formed by implanting impurity ions into the LDD regions on the opposite sides of the lower gate electrode. An upper gate polysilicon layer is formed. Then, the upper gate polysilicon layer is selectively removed to form an upper gate electrode. A silicide layer is then formed on the top and side surfaces of the upper gate electrode.Type: GrantFiled: September 16, 2003Date of Patent: December 14, 2004Assignee: ANAM Semiconductor, Inc.Inventor: Kwan Ju Koh
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Patent number: 6830998Abstract: Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.Type: GrantFiled: June 17, 2003Date of Patent: December 14, 2004Assignee: Advanced Micro Devices, Inc.Inventors: James Pan, Paul Besser, Christy Mei-Chu Woo, Minh Van Ngo, Jinsong Yin
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Patent number: 6830999Abstract: An improved flip chip assembly is disclosed of the type where a semiconductor chip having a certain thermal expansion coefficient is directly mounted via solder bumps on the metallization pattern of a circuit substrate having a different thermal expansion coefficient. A base layer comprised of a polymer material is disposed over the surface of the chip, between the chip and the substrate, and the solder bumps are placed over the base layer; the base layer modifies the effective thermal expansion coefficient of the solder bumps to approximate that of the substrate, thus reducing the thermal expansion coefficient differential at the junction of the chip and the substrate.Type: GrantFiled: June 17, 2002Date of Patent: December 14, 2004Assignee: Agere Systems Inc.Inventor: Rajan D. Deshmukh
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Patent number: 6831000Abstract: The present invention comprises the steps of forming a bump metal film as a pattern having an opening portion on an area of a seed metal film that corresponds to a connecting pad of a semiconductor substrate, forming a through hole by etching the seed metal film, the connecting pad, and the semiconductor substrate located under the opening portion of the bump metal film while using the bump metal film as a mask, grinding a back surface of the semiconductor substrate, forming an insulating film on a side surface of the through hole, forming a through wiring in the through hole by an electroplating, and forming a metal bump by etching the seed metal film.Type: GrantFiled: January 5, 2004Date of Patent: December 14, 2004Assignee: Shinko Electric Industries Co., Ltd.Inventor: Kei Murayama
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Patent number: 6831001Abstract: A method is provided for forming stacked local interconnects that do not extend into higher levels within a multilevel IC device for economizing space available within the IC device and increasing design flexibility. In one embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.Type: GrantFiled: April 4, 2003Date of Patent: December 14, 2004Assignee: Micron Technology, Inc.Inventor: Jigish D. Trivedi
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Patent number: 6831002Abstract: A manufacturing method of a semiconductor device for providing wires on a front surface of a semiconductor wafer by providing a plating layer, in which conductive layers provided on the front and back surfaces of the semiconductor wafer are electrically conducted by solder filled in its through-holes, and electrolytic plating is carried out by electrically connecting cathode terminals of an electrolytic plating apparatus and the conductive layer provided on the back surface of the semiconductor wafer which is provided with a mask on the conductive layer provided on its front surface.Type: GrantFiled: September 13, 2002Date of Patent: December 14, 2004Assignee: Sharp Kabushiki KaishaInventors: Yoshihide Iwazaki, Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Takamasa Tanaka, Katsunobu Mori
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Patent number: 6831003Abstract: For filling an interconnect opening within a porous dielectric material, a diffusion barrier material is deposited onto at least one sidewall of the interconnect opening. A thickness of the diffusion barrier material is equal to or greater than a radius of a pore opened at the sidewall to substantially fill the opened pore. The thickness of the diffusion barrier material is equal to or greater than a mean radius of pores opened at the sidewall to substantially fill a majority of the opened pores. Or, the thickness of the diffusion barrier material is equal to or greater than a radius of a largest pore opened at the sidewall to substantially fill all opened pores. The interconnect opening is then filled with a conductive fill material.Type: GrantFiled: May 31, 2002Date of Patent: December 14, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Richard J. Huang, Pin-Chin C. Wang, Darrell M. Erb
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Patent number: 6831004Abstract: A method of forming a boride layer for integrated circuit fabrication is disclosed. In one embodiment, the boride layer is formed by chemisorbing monolayers of a boron-containing compound and one refractory metal compound onto a substrate. In an alternate embodiment, the boride layer has a composite structure. The composite boride layer structure comprises two or more refractory metals. The composite boride layer is formed by sequentially chemisorbing monolayers of a boron compound and two or more refractory metal compounds on a substrate.Type: GrantFiled: March 13, 2003Date of Patent: December 14, 2004Assignee: Applied Materials, Inc.Inventors: Jeong Soo Byun, Alfred Mak
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Patent number: 6831005Abstract: A process for the formation of structures in microelectronic devices such as integrated circuit devices. Vias, interconnect metallization and wiring lines are formed using single and dual damascene techniques wherein dielectric layers are treated with a wide electron beam exposure.Type: GrantFiled: October 17, 2000Date of Patent: December 14, 2004Assignee: Allied Signal, Inc.Inventor: Matthew F. Ross
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Patent number: 6831006Abstract: A short or high leakage path from a metal contact to a P-well can occur when a contact via mask is misaligned with an active area mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the contact junction depletion region or even a P-well on the active area sidewall. This problem is prevented by using an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant from the poly liner forms an N+ halo extension in the active area silicon, providing a reverse biased junction between the metal contact stud and the P-well. The complementary structure and method of an N-well and P+ dopant are also disclosed.Type: GrantFiled: January 15, 2003Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Ramachandra Divakaruni, Jack Mandelman, Haining Yang
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Patent number: 6831007Abstract: A method for forming a metal line of an Al/Cu structure is disclosed. In a state where a first Ti/TiN layer, an Al layer, and a second Ti/TiN layer are layered, the grooves are formed by etching the upper half the Al layer using a photoresist film, which is formed on the second Ti/TiN layer by a negative patterning process, as a mask. After a third Ti/TiN layer and a Cu layer are formed in the grooves, the third Ti/TiN (buffer) layer, the second Ti/TiN layer, the Al layer, and the first Ti/TiN layer are etched using the Cu layer as a mask. Thus, the metal line having a layered structure of the first Ti/TiN layer, the Al layer, the third Ti/TiN layer, and the Cu layer is formed. In such case, since thickness of the photoresist film has decreased by half the thickness of the Al layer, the photoresist film can finely be patterned.Type: GrantFiled: March 14, 2002Date of Patent: December 14, 2004Assignee: Hynix Semiconductor Inc.Inventor: Kil Ho Kim
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Patent number: 6831008Abstract: A process for forming nickel silicide and silicon nitride structure in a semiconductor integrated circuit device is described. Good adhesion between the nickel silicide and the silicon nitride is accomplished by passivating the nickel suicide surface with nitrogen. The passivation may be performed by treating the nickel silicide surface with plasma activated nitrogen species. An alternative passivation method is to cover the nickel silicide with a film of metal nitride and heat the substrate to about 500° C. Another alternative method is to sputter deposit silicon nitride on top of nickel silicide.Type: GrantFiled: September 30, 2002Date of Patent: December 14, 2004Assignee: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Glenn J. Tessmer, Melissa M. Hewson, Donald S. Miles, Ralf B. Willecke, Andrew J. McKerrow, Brian K. Kirkpatrick, Clinton L. Montgomery
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Patent number: 6831009Abstract: A multilayer wiring substrate which is high in connection reliability is provided through process steps of forming more than one opening, such as a via-hole in a dielectric layer laminated on a substrate, and then applying uniform copper plating to a surface portion of the dielectric layer including the opening to thereby form a wiring layer. An electroless copper plating solution with at least one of mandelonitrile and triethyltetramine mixed therein is used to perform the intended electroless copper plating. An alternative process makes use of a electroless copper plating solution with chosen additive agents or “admixtures” containing at least one of mandelonitrile and triethyltetramine plus eriochrome black T along with at least one of 2,2′-bipyridyl, 1,10-phenanthroline, and 2,9-dimethyl-1,10-phenanthroline.Type: GrantFiled: September 26, 2001Date of Patent: December 14, 2004Assignee: Hitachi, Ltd.Inventors: Takeyuki Itabashi, Haruo Akahoshi, Eiji Takai, Naoki Nishimura, Tadashi Iida, Yoshinori Ueda
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Patent number: 6831010Abstract: This invention relates to a method of depositing a layer on an exposed surface of an insulating layer of material. The method includes treating the exposed surface with hydrogen or a gaseous source of hydrogen in the presence of a plasma, prior to or during deposition of a metallic layer.Type: GrantFiled: April 12, 2000Date of Patent: December 14, 2004Assignee: Trikon Technologies LimitedInventors: Knut Beekman, Paul Rich, Claire Louise Wiggins
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Patent number: 6831012Abstract: After a silicidation blocking pattern is formed on a substrate including silicon, the silicidation blocking pattern is hardened by a thermal annealing process. The substrate is rinsed to remove a native oxide film formed on the substrate, and then a silicide film is formed on a portion of the substrate exposed by the silicidation blocking pattern. The silicide film can thus be formed in an exact portion of the substrate, and the substrate is not damaged during rinsing.Type: GrantFiled: May 28, 2003Date of Patent: December 14, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Keun Kang, Yong-Sun Ko, In-Seak Hwang, Byoung-Moon Yoon
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Patent number: 6831013Abstract: This invention relates to a method of forming a dual damascene via, in particular to a method of forming a dual damascene via by using a metal hard mask layer. The present invention uses a metal layer to be a hard mask layer to make the surface of the isolation layer become a level and smooth surface and not become a rounding convex and to prevent the via being connected with others vias to cause the leakage defects after forming the shape of the via.Type: GrantFiled: November 13, 2001Date of Patent: December 14, 2004Assignee: United Microelectronics Corp.Inventors: Teng-Chun Tsai, Chia-Lin Hsu
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Patent number: 6831014Abstract: A method of manufacturing a semiconductor apparatus includes the step (a) to the step (f). In the step (a), an insulation film is formed on a semiconductor substrate. In the step (b), a wiring trench is formed which extends to the insulation film. In the step (c), a first conductive film is formed which covers an inner surface of the wiring trench and covers the insulation film. In the step (d), a second conductive film is formed which fills the wiring trench and covers the first conductive film. In the step (e), the second conductive film is removed by chemical mechanical polishing (CMP) until a surface of the first conductive film is exposed. In the step (f), a surface of the second conductive film is polished by using a first solution such that a first protective film for protecting the second conductive film is formed. In the step (g), the first conductive film and the second conductive film is removed by CMP until a surface of the insulation film is exposed.Type: GrantFiled: August 30, 2002Date of Patent: December 14, 2004Assignee: NEC Electronics CorporationInventor: Yasuaki Tsuchiya
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Patent number: 6831015Abstract: A fabrication method of a semiconductor device improved in the polishing rate of an insulation film and less likely to generate a defect during polishing is obtained. In this fabrication of a semiconductor device, impurities are introduced into a first insulation film, and then planarization is effected by polishing the surface of the first insulation film. Thus, the polishing rate of the portion of the first insulation film in which impurities are introduced is improved. Also a defect is not easily generated therein.Type: GrantFiled: August 29, 1997Date of Patent: December 14, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Yasunori Inoue, Yoshio Okayama
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Patent number: 6831016Abstract: A method to prevent electrical shorts between adjacent metal lines on a semiconductor substrate having an insulating layer with a pair of damascene structures connecting to the semiconductor substrate and a scratch on the upper surface of the insulating layer, between the damascene structures, is provided. A diffusion barrier layer is deposited on the damascene structures and the scratch. Then, a metal layer is formed to fill the damascene structures. Next, the metal is chemical-mechanically polished to form a metal line. Finally, the diffusion barrier layer disposed on the surface of the scratch is removed by etching process.Type: GrantFiled: May 21, 2002Date of Patent: December 14, 2004Assignee: Nanya Technology CorporationInventors: Tzu-Ching Tsai, Ping Hsu
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Patent number: 6831017Abstract: Nanowire devices may be provided that are based on carbon nanotubes or single-crystal semiconductor nanowires. The nanowire devices may be formed on a substrate. Catalyst sites may be formed on the substrate. The catalyst sites may be formed using lithography, thin metal layers that form individual catalyst sites when heated, collapsible porous catalyst-filled microscopic spheres, microscopic spheres that serve as masks for catalyst deposition, electrochemical deposition techniques, and catalyst inks. Nanowires may be grown from the catalyst sites.Type: GrantFiled: April 5, 2002Date of Patent: December 14, 2004Assignee: Integrated Nanosystems, Inc.Inventors: Jun Li, Alan M. Cassell, Jie Han
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Patent number: 6831018Abstract: After forming a resist pattern on an insulating film deposited on a semiconductor substrate, the insulating film is subjected to plasma etching using an etching gas including carbon and fluorine with the resist pattern used as a mask. A polymer film having been deposited on the resist pattern during the plasma etching is subjected to a first stage of ashing with a relatively low chamber pressure and relatively low plasma generation power by using an oxygen gas or a gas including oxygen as a principal constituent. A residual polymer present on the insulating film in completing the first stage of the ashing is subjected to a second stage of the ashing with a relatively high chamber pressure and relatively high plasma generation power by using an oxygen gas or a gas including oxygen as a principal constituent.Type: GrantFiled: April 24, 2002Date of Patent: December 14, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kenshi Kanegae
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Patent number: 6831019Abstract: In one implementation, a plasma etching method comprises forming a GexSey chalcogenide comprising layer over a substrate. A mask comprising an organic masking material is formed over the GexSey chalcogenide comprising layer. The mask comprises a sidewall. At least prior to plasma etching the GexSey comprising layer, the sidewall of the mask is exposed to a fluorine comprising material. After exposing, the GexSey chalcogenide comprising layer is plasma etched using the mask and a hydrogen containing etching gas. The plasma etching forms a substantially vertical sidewall of the GexSey chalcogenide comprising layer which is aligned with a lateral outermost extent of the sidewall of the mask.Type: GrantFiled: August 29, 2002Date of Patent: December 14, 2004Assignee: Micron Technology, Inc.Inventors: Li Li, Terry L. Gilton, Kei-Yu Ko, John T. Moore, Karen Signorini
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Patent number: 6831020Abstract: After a first gate insulating film is formed on each of first to third active regions, the first gate insulating film on the second active region is removed therefrom and a second gate insulating film thinner than the first gate insulating film is formed on the second active region. Then, the first gate insulating film on the third active region is removed therefrom and a third gate insulating film thinner than the second gate insulating film is formed on the third active region. Otherwise, a pad oxide film on the first active region is removed therefrom and the first gate insulating film is formed on the first active region. Then, the pad oxide film on the second active region is removed therefrom and a second gate insulating film thinner than the first gate insulating film is formed on the second active region. Thereafter, the pad oxide film on the third active region is removed therefrom and a third gate insulating film thinner than the second gate insulating film is formed on the third active region.Type: GrantFiled: November 1, 2002Date of Patent: December 14, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takayuki Yamada, Hiroaki Nakaoka
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Patent number: 6831021Abstract: Embodiments of the invention generally provide a method of forming a nitride gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via introduction of a nitrogen-containing processing gas into the processing chamber and the application of an ionizing energy to the processing gas, and pulsing the ionizing energy to maintain a mean temperature of electrons in the nitrogen-containing plasma of less than about 0.7 eV.Type: GrantFiled: June 12, 2003Date of Patent: December 14, 2004Assignee: Applied Materials, Inc.Inventors: Tal Cheng Chua, Philip Allan Kraus, John Holland
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Patent number: 6831022Abstract: A system, apparatus and/or method is provided for removing water vapor from a wafer processing chamber generated as a byproduct of wafer processing. A water vapor trap is used to collect the water vapor byproduct from the processing chamber interior. The water vapor trap has at least a portion thereof in communication with an interior of the processing chamber for collection of the water vapor and another portion thereof in communication with an exterior of the processing chamber. The portions are movable with respect to the interior and exterior of the processing chamber such that the portions may switch places. This allows the processing chamber to be in at least a substantially continuous mode of operation while still providing for the removal of water vapor byproduct via the water vapor trap. The “used” portion of the water vapor trap is regenerated while the “clean” portion is collecting water vapor.Type: GrantFiled: June 26, 2003Date of Patent: December 14, 2004Assignee: LSI Logic CorporationInventors: Robert D. Broyles, Michael J. Berman
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Patent number: 6831023Abstract: The invention relates to an electrically conductive floor covering based on linoleum, comprising a wear layer and a sub-layer, whereby the floor covering has an electrical volume resistivity R1 according to EN 1081, of a maximum 107 &OHgr;. The invention also relates to a method for producing said floor covering.Type: GrantFiled: June 4, 2002Date of Patent: December 14, 2004Assignee: DLW AktiengesellschaftInventors: Uta Szerreiks, Markus Baum
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Patent number: 6831024Abstract: The conductive fabric is fabricated by preparing a base fibrous fabric substrate having the form of a woven, non-woven, or mesh sheet, forming a first layer formed on the fibrous fabric substrate in accordance with an electroless plating process, the first layer being made of copper, and forming a second layer as an externally exposed layer, on the first layer continuously, the second layer being made of gold or platinum.Type: GrantFiled: January 2, 2003Date of Patent: December 14, 2004Assignees: AMIC Co., Ltd.Inventor: Sun-Ki Kim
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Patent number: 6831025Abstract: A spunbond nonwoven fabric is provided which is formed from continuous multiple component filaments which include a polyester component and a polyethylene component. The polyethylene component is a blend of high density polyethylene and a first linear low density polyethylene. The spunbond filaments are preferably formed in a sheath-core configuration with the polyester component in the core and the polyethylene component in the sheath. Composite sheets are provided which include the multiple component spunbond layer and a meltblown layer, wherein the meltblown fibers include a second linear low density polyethylene. The linear low density polyethylenes are preferably formed by polymerization of ethylene with an alpha-olefin co-monomer, where the same co-monomer is used in each of the first and second linear low density polyethylenes.Type: GrantFiled: June 18, 2001Date of Patent: December 14, 2004Assignee: E. I. du Pont de Nemours and CompanyInventors: Edgar N. Rudisill, Vishal Bansal, Michael C. Davis
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Patent number: 6831026Abstract: The invention relates to an essentially lead free glass. The lead free glass is suitable for making glass tubes and glass tubes for electric lamps in particular. The essentially lead free glass is characterized by having the lead oxide of a lead glass replaced by 1.0-3.0% by weight of lithium oxide. The ultraviolet radiation absorption of the glass is improved for wavelengths shorter than 320 nm. by the presence of 0.1-0.3% by weight of cerium oxide (CeO2) and 0.05-0.15% by weight of titanium dioxide (TiO2). With such an essentially lead free glass the transmittance of visible radiation may also be improved.Type: GrantFiled: January 10, 2003Date of Patent: December 14, 2004Assignee: L. Electric Glass Co. Ltd.Inventor: Somchai Ovuthitham
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Patent number: 6831027Abstract: The present invention provides a composition for use in forming a porcelain enamel coating having a metallic appearance. The composition according to the invention preferably includes a low shear blend of a glass component and metal particles such as aluminum, nickel, copper and stainless steel. The glass component includes at least one glass frit that fuses at a temperature of less than about 600° C. Upon firing at a temperature of from about 535° C. to about 600° C., the composition forms a vitreous porcelain enamel coating that has a metallic appearance, which through the incorporation of various optional pigments and/or mill additions, can range from a bright brushed nickel or stainless steel appearance to a matte dark metallic finish.Type: GrantFiled: October 21, 2002Date of Patent: December 14, 2004Assignee: Ferro CorporationInventor: Louis J. Gazo
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Patent number: 6831028Abstract: This invention provides an antimicrobial glass which exhibits excellent dispersing ability into a resin and excellent transparency besides generating small yellowing and a method for manufacturing the antimicrobial glass. In the antimicrobial glass capable of releasing an Ag ion, a shape of the antimicrobial glass is formed into a polyhedron and, at the same time, an average particle size of the antimicrobial glass is set to a value within a range of 0.1 to 300 &mgr;m.Type: GrantFiled: October 23, 2002Date of Patent: December 14, 2004Assignee: KOA Glass Co., Ltd.Inventors: Masao Ishii, Kenichi Tanaka
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Patent number: 6831029Abstract: Glasses are disclosed which are used to produce substrates in flat panel display devices. The glasses exhibit a density less than about 2.45 gm/cm3 and a liquidus viscosity greater than about 200,000 poises, the glass consisting essentially of the following composition, expressed in terms of mol percent on an oxide basis: 65-75 SiO2, 7-13 Al2O3, 5-15 B2O3, 0-3 MgO, 5-15 CaO, 0-5 SrO, and essentially free of BaO. The glasses also exhibit a strain point exceeding 650° C.Type: GrantFiled: November 16, 2001Date of Patent: December 14, 2004Assignee: Corning IncorporatedInventors: Lisa C. Chacon, Adam J. G. Ellison, George B. Hares, Jeffrey T. Kohli, Josef C. Lapp, Robert Morena
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Patent number: 6831030Abstract: A high transmittance glass sheet is provided that is formed of a soda-lime-silica glass composition containing, expressed in wt. %, less than 0.020% of total iron oxide in terms of Fe2O3 and 0.006 to 2.0% of zinc oxide. The glass sheet allows the formation of nickel sulfide particles to be suppressed by the addition of a zinc compound to a glass raw material.Type: GrantFiled: September 5, 2002Date of Patent: December 14, 2004Assignee: Nippon Sheet Glass Company, Ltd.Inventors: Akihiro Koyama, Isamu Kuroda, Nobuyuki Yamamoto, Yasunori Seto
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Patent number: 6831031Abstract: A thermally conductive sheet comprising boron nitride powder as a first thermally conductive filler dispersed into an organic matrix, wherein the boron nitride powder is hexagonal boron nitride (h-BN), and comprises primary particles and secondary aggregates formed by aggregation of the primary particles, wherein at least part of the secondary aggregates being 50 &mgr;m or more in size. The boron nitride powder preferably includes 1 to 20 percent by weight of secondary aggregates of 50 &mgr;m or more in size. The organic matrix material is preferably silicone rubber.Type: GrantFiled: August 12, 2002Date of Patent: December 14, 2004Assignee: Polymatech Co., Ltd.Inventor: Natsuko Ishihara
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Patent number: 6831032Abstract: A method for making a solid catalyst component for use in a Ziegler-Natta catalyst includes combining a porous particulate support with a magnesium source in a hydrocarbon solvent to form a mixture, the magnesium source including a hydrocarbon soluble organomagnesium compound and a hydrocarbon insoluble anhydrous inorganic magnesium-halogen compound. The organomagnesium compound is halogenated and the mixture is reacted with a titanium compound or vanadium compound to form the solid catalyst component. The solid catalyst component is then recovered and combined with an organoaluminum cocatalyst to form a Ziegler-Natta catalyst which is advantageously used for the polymerization of olefins, particularly alk-1-enes such as ethylene, propylene, 1-butene, and the like. The catalyst can optionally include internal and external electron donors.Type: GrantFiled: August 19, 2002Date of Patent: December 14, 2004Assignee: Novolen Technology Holdings C.V.Inventor: Wolf Spaether
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Patent number: 6831033Abstract: A solid titanium complex catalyst for polymerization and copolymerization of ethylene is prepared by the process that includes: (1) preparing a magnesium solution by reacting a halogenated magnesium compound with an alcohol; (2) reacting the magnesium solution with an ester compound having at least one hydroxyl group and a silicon compound having an alkoxy group to produce a magnesium composition; and (3) producing a solid titanium catalyst by reacting the magnesium composition solution with a mixture of a titanium compound and a haloalkane compound; and optionally reacting the solid titanium catalyst with an additional titanium compound.Type: GrantFiled: June 12, 2002Date of Patent: December 14, 2004Assignee: Samsung General Chemicals Co., Ltd.Inventors: Chun-Byung Yang, Sang-Yull Kim, Weon Lee
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Patent number: 6831034Abstract: Catalytic composition for the (co)polymerization of ethylene and other &agr;-olefins, including a metallocene complex of a metal M of group 4 of the periodic table or the product obtainable from the same combined with a suitable activator, wherein said metallocene complex includes at least one cyclopentadienyl group and at least one unsaturated hydrocarbyl organic group bonded to the metal M, having the following formula (I): -(AxDyUz)RI (I) wherein: A represents any monomeric unit deriving from a vinylaromatic group polymerizable by means of anionic polymerization, having from 6 to 20 carbon atoms; D represents any monomeric unit deriving from a conjugated diolefin polymerizable by means of anionic polymerization, having from 4 to 20 carbon atoms; U represents any generic optional monomeric unit deriving from an unsaturated compound co-polymerizable with any of the above conjugated diolefins D or vinylaromatic compounds A; RI represents hydrogen or a hydrocarbyl group having from 1 to 20 carType: GrantFiled: September 26, 2003Date of Patent: December 14, 2004Assignee: Polimeri Europa S.p.A.Inventors: Francesco Masi, Anna Sommazzi, Roberto Santi
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Patent number: 6831035Abstract: Disclosed are novel catalyst systems comprising (1) a diorgano fluorophosphite ligand; (2) rhodium, wherein the ratio of gram moles fluorophosphite ligand (1) to gram atoms of rhodium is at least 1:1; and (3) a Group VIII metal, other than rhodium, or Group VIII metal-containing compound, in an amount effective to reduce the formation of HF during the use of the catalyst system. The presence of the other Group VIII metal decreases the amount of hydrogen fluoride produced during the use of the catalyst system. The hydrogen fluoride originates from very low level degradation of the ligand. Also disclosed are novel catalyst solutions of the aforesaid catalyst system and the use of the catalyst system in the hydroformylation of olefins to produce aldehydes.Type: GrantFiled: January 22, 2002Date of Patent: December 14, 2004Assignee: Eastman Kodak CompanyInventors: Thomas Allen Puckette, Ginette Struck Tolleson