Patents Issued in December 14, 2004
  • Patent number: 6831437
    Abstract: A walking platform that achieves automatic self-stabilization includes a motor within the mid-region of the platform that is in communication with a crankshaft. The crankshaft has a connecting rod that is rotatably attached to it. The connecting rod, in turn, has a pole that is rotatably attached to it. There is a foot attached that is capable of supporting the weight of the platform. The motor is powered by a battery that causes the components of the platform to simulate a walking motion. This battery is attached to the lower portion of the platform in order to lower the center of gravity of the platform. The platform also includes at least one levered component that is rotatably attached to the platform, allowing it to pivot freely and dampen oscillations produced by the walking platform.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: December 14, 2004
    Inventor: Andrew S. Filo
  • Patent number: 6831438
    Abstract: Controlling a direct current motor driving an object by determining, if the object does not reach a target position, a reference velocity corresponding to a point of time from a predetermined velocity trajectory, obtaining a position of the object, calculating a current velocity of the object, and calculating a difference between the reference velocity and the current velocity. If the calculated difference is greater than a velocity error limit value, informing a user that an error has occurred.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: December 14, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-do Jung
  • Patent number: 6831439
    Abstract: Disclosed are a flux observer and a sensorless control system of a synchronous reluctance motor. The flux observer includes an estimated flux output unit, a measured flux output unit, and a fixed/rotational coordinate converter. The flux observer estimates a flux of a synchronous reluctance motor by removing higher harmonic components of a current in a rotational coordinate system which flows into the motor. The measured flux output unit measures a flux in a fixed coordinate system by combining a voltage in the fixed coordinate system, which is applied to the motor, and a current in the fixed coordinate system, from which higher harmonic components are removed, with the estimated flux outputted from the estimated flux output unit. The fixed/rotational coordinate converter converts the measured flux outputted from the measured flux output unit to a measured flux in the rotational coordinate system.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: December 14, 2004
    Assignee: Electronics, Inc.
    Inventors: June Hee Won, Jae Yoon Oh, Kyung Hoon Lee, Dal Ho Cheong
  • Patent number: 6831440
    Abstract: A method and apparatus for use with a controller that uses a flux angle position value to control a three phase induction machine, the method for determining an instantaneous flux angle position value in the machine where the machine is characterized by a system specific dominant harmonic frequency number DH that is at least two, the method comprising the steps of injecting a high frequency voltage signal having a high frequency value into the machine thereby generating a high frequency current within the stator windings, obtaining a high frequency feedback signal from the machine, mathematically combining the high frequency value and the dominant harmonic number DH to provide an instantaneous modified angle, using the feedback signal to identify X consecutive calculating instances during each Y consecutive feedback signal cycles where Y is at least two, at each of the X different calculating instances, identifying an instantaneous flux angle position value by mathematically combining a shift angle with the i
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: December 14, 2004
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Semyon Royak, Mark M. Harbaugh
  • Patent number: 6831441
    Abstract: Disclosed is an electronic pulse width modulation (PWM) regulator of a low frequency rectangular wave signal serving to control the speed of a direct current motor. The invention aims at simplifying the design of said regulator by eliminating the classical inductive element so that the motor continuously operates as a filter of the output signal provided by the switching component. The invention also aims at preventing noises caused by switching. To this end, subsonic switching frequencies of less than 50 Hz are used.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: December 14, 2004
    Assignee: Nagares, S.A.
    Inventor: Herminio Navalon Carretero
  • Patent number: 6831442
    Abstract: A method for providing additional dc inputs or outputs (49, 59) from a dc-to-ac inverter (10) for controlling motor loads (60) comprises deriving zero-sequence components (Vao, Vbo, and Vco) from the inverter (10) through additional circuit branches with power switching devices (23, 44, 46), transforming the voltage between a high voltage and a low voltage using a transformer or motor (42, 50), converting the low voltage between ac and dc using a rectifier (41, 51) or an H-bridge (61), and providing at least one low voltage dc input or output (49, 59). The transformation of the ac voltage may be either single phase or three phase. Where less than a 100% duty cycle is acceptable, a two-phase modulation of the switching signals controlling the inverter (10) reduces switching losses in the inverter (10). A plurality of circuits for carrying out the invention are also disclosed.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: December 14, 2004
    Assignees: General Motors Corporation, UT-Battelle, LLC
    Inventors: John S. Hsu, Gui-Jia Su, Donald J. Adams, James M. Nagashima, Constantin Stancu, Douglas S. Carlson, Gregory S. Smith
  • Patent number: 6831443
    Abstract: A power adapter assembly for use between a portable electrical device and a power source is disclosed. The power adapter assembly includes a power connecting device having a first joint at one end thereof for electrically connecting to the portable electrical device and a second joint at the other end thereof, a data storage unit electrically connected with the second joint of the power connecting device and storing the power supply data corresponding to the portable electrical device, and a power adapter having a socket for electrically connecting to the second joint of the power connecting device. The power adapter reads the power supply data stored in the data storage unit, converts the power from the power source into a required power form according to the power supply data, and transfers the required power to the portable electrical device through the power connecting device.
    Type: Grant
    Filed: July 5, 2002
    Date of Patent: December 14, 2004
    Assignee: Primax Electronics, Ltd.
    Inventor: Chien-Te Liu
  • Patent number: 6831444
    Abstract: This invention relates to a portable external storage device including a battery which supplies power to a communication section which communicates with a plurality of information processing apparatuses, a detection unit which detects a remaining amount of the battery, a storage unit which stores setting information representing a notifying method for information about a remaining amount of the battery transmitted from the information processing apparatus serving as a host device, and a remaining amount of the battery at which a warning is generated, and a notifying unit which notifies the host device of information about the remaining amount of the battery detected by the detection unit on the basis of the setting information stored in the storage unit.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: December 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Kobayashi, Kazunari Tanzawa
  • Patent number: 6831445
    Abstract: An automotive alternator is provided which includes a rectifier, a circulating circuit, and a controller. The circulating circuit is connected in parallel to a field winding to circulate the field current in the event that supply of the field current to a field winding is cut. The circulating circuit consists of a first circuit formed by a diode and a second circuit working to enhance attenuation of the field current. The controller works to select the second circuit when a voltage of the output of the rectifier exceeds a reference value and select the first circuit when the voltage of the output of the rectifier is less than the reference value.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: December 14, 2004
    Assignee: Denso Corporation
    Inventor: Makoto Taniguchi
  • Patent number: 6831446
    Abstract: Protrusions (260) for adjusting the cogging torque of a rotor (21) are formed on a stator (22) in a small-size power generator (20). Since the protrusions (260) are formed on an inner periphery of a rotor accommodation hole (230) within an angular range of ±45° around a magnetic flux direction of a first magnetic circuit (100) having a smaller magnetic reluctance at a rotation center of the rotor (21), the cogging torque can be effectively reduced. Accordingly, even when the size of components such as an oscillating weight and a power spring is reduced for making a thin timepiece, rotation startability of the rotor can be improved, thus improving power generation efficiency of the small-size power generator.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: December 14, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Kinya Matsuzawa
  • Patent number: 6831447
    Abstract: A method and apparatus for protecting circuit components from inrush current. A field effect transistor (FET) is controlled to provide a source of dynamic impedance, placed in series with a circuit component to be protected. The circuit uses a current limiting circuit to limit current flow into a small capacitor across the gate of the FET, thus controlling the rate at which the small capacitor charges, and hence, the rate at which the FET transitions from an “off” state with high in-series impedance to an “on” state with low in-series impedance. The current limiting circuit can be supplemented with a short circuit detection circuit that terminates current flow into the current limiting circuit upon a short circuit in the protected component. The surge limiting circuit, with optional short circuit detection, can be integrated within larger integrated circuits or produced as a discrete device with or without an imbedded protected component.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: December 14, 2004
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventor: John W. Wittenberg
  • Patent number: 6831448
    Abstract: In order to increase the transient response speed of a DC-to-DC converter capable of voltage step-up and voltage step-down, to which a DC voltage is input from a battery or the like and from which a controlled DC voltage is supplied to a load, a first voltage E1 lower than an output setting voltage Eset by a predetermined voltage is defined and is compared with a DC output voltage Eo by a first comparator, and the result of the comparison is output. @a A second voltage E2 lower than a DC input voltage Ei by a predetermined voltage is defined and is compared with the DC output voltage Eo by a second comparator 133, and the result of the comparison is also output. When the results of the comparisons are represented by Eo<E1 and Eo<E2, a switch connected between the input and the output is turned ON. This configuration greatly increases the response speed at the time when the DC output voltage Eo reaches the output setting voltage Eset.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: December 14, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takuya Ishii, Hiroshi Saito, Hironori Kamiya, Takashi Ryu
  • Patent number: 6831449
    Abstract: A power supply device which converts a voltage by a switching method is connected to a load. Whether a current supplied from the power supply device to the load falls within a proper range is determined. At this time, while preventing an increase in cost in current detection and reducing Joule loss caused by an unwanted resistance component, it is determined that the current falls within the proper range. In order to determine a current supplied from a DC/DC converter to the load, a current determination unit (1) is arranged. The current determination unit (1) compares, with a preset voltage, a voltage obtained by DC-detecting a gate driving pulse signal used to turn on/off a switching MOS transistor (3), thereby determining whether the current flowing from the DC/DC converter to the load exceeds a predetermined current (proper range). In current detection, Joule loss by an unwanted resistance component can be reduced.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: December 14, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideyuki Nishida, Kazunori Masuda
  • Patent number: 6831450
    Abstract: Apparatus and methods are provided for measuring a selected optical behavior of a tunable opto-electric device by using the electrical characteristics of the opto-electronic device. The benefit of the present invention is the elimination or reduction in complexity of optical wavelength reference hardware that is currently required for wavelength referencing and locking. Accordingly, the present invention reduces the cost and complexity of the optical packaging of tunable opto-electronic telecommunication components. Furthermore, the present invention also significantly simplifies optical and electronic design of system level products with tunable opto-electronic devices.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: December 14, 2004
    Assignee: Nortel Networks, Ltd.
    Inventor: Yakov Kogan
  • Patent number: 6831451
    Abstract: According to one exemplary embodiment, a method for determining a Weibull slope at a specified temperature utilizing a test structure comprises a step of performing a number of groups of failure tests on the test structure to determine a number of groups of test data, where each of the groups of failure tests is performed at a respective one of a number of test temperatures, and where each group of failure tests corresponds to a respective group of test data. The method further comprises utilizing the number of groups of test data to determine a scaling line. The method further comprises determining a scaling factor at the specified temperature utilizing the scaling line. The method further comprises utilizing the scaling factor to determine the Weibull slope. The method may further comprise utilizing the Weibull slope to determine a lifetime of the semiconductor die.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: December 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hyeon-Seag Kim, Jongwook Kye
  • Patent number: 6831452
    Abstract: Systems and methods for wideband single-end probing of variably spaced probe points are provided. One such embodiment includes a probe housing. The probe housing at least partially surrounds a probe barrel. A probe barrel end cap extends from the probe barrel and at least partially surrounds a probe tip. The longitudinal axis of the probe tip is offset from the longitudinal axis of the probe barrel. A ground tip is adjacent to the probe tip and electrically connected to the probe barrel. Methods are also provided.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: December 14, 2004
    Assignee: Agilent Technologies, Inc.
    Inventor: Michael T. McTigue
  • Patent number: 6831453
    Abstract: The magnitude of a pulse in a signal having both positive and negative polarity pulses (for example, a ternary PDH signal) is determined by measuring the magnitude of multiple samples of the signal. A reference level for the signal is determined from a plurality of these sample magnitudes, and the magnitude of a pulse in the signal is determined from the sample magnitudes and the reference level.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: December 14, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Colin Johnstone, Alexander John Stephen
  • Patent number: 6831454
    Abstract: An indexing device in a semiconductor device handler, and a method for operating the same, utilizes a plurality of pairs of loading shuttles and unloading shuttles located on both sides of test sockets. Index heads move over and across the test sockets and the loading/unloading shuttles. While one of the index heads holds devices that are being tested, the other index head unloads tested semiconductor devices on one of the unloading shuttles, receives semiconductor devices to be tested from a loading shuttle, and stands by in the vicinity of the test sockets. This allows the semiconductor devices held by the index head at the stand by position to be immediately inserted into the test socket for testing when the other index head moves for unloading the tested semiconductor devices from the test sockets. As a result, an indexing time period is minimized, a size of the device can be reduced, and easy maintenance can be carried out.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: December 14, 2004
    Assignee: Mirae Corporation
    Inventors: Gil Ho Bae, Seung Hwan Kim, Yon Choul Baek
  • Patent number: 6831455
    Abstract: In a mechanism for fixing a probe card, the probe card and a support frame are joined to each other about the axis of each of the probe card and the support frame by a plurality of first fastening members. Also, the outer circumferential edge portion of the support frame is fixed by a plurality of second fastening members to a holder fixed to a probe unit. The probe card is held by the mechanism such that the central region of the probe card is restricted by the first fastening members and the outer circumferential portion of the probe card is not restricted so as to be rendered free. It follows that the probe card is expanded toward the outer circumferential edge portion by thermal expansion under a high-temperature. However, the probe card is prevented from being deformed in the shape of a dome.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: December 14, 2004
    Assignee: Tokyo Electron Limited
    Inventor: Toshihiro Yonezawa
  • Patent number: 6831456
    Abstract: The invention relates to an angle sensor comprising at least two angle-offset anisotropic magnetoresistive sensor units comprising anisotropic magnetoresistive elements, in which the angle sensor comprises at least a device for increasing the anisotropic field strength of the sensor units. The invention also relates to a method of increasing the anisotropic field strength of a sensor unit of an angle sensor comprising magnetoresistive elements, in which a magnetic supporting field present in a preferred direction of the magnetoresistive elements is generated.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: December 14, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Michael Doescher
  • Patent number: 6831457
    Abstract: The present invention is a two-dimensional magnetic sensor having a first magneto-impedance sensor element including a first magneto-sensitive element and a first electro-magnetic coil which is wound around said first magneto-sensitive element; a second magneto-impedance sensor element including a second magneto-sensitive element and a second electro-magnetic coil which is wound around said second magneto-sensitive element; and an integrated circuit including an oscillator, a current switching element, a voltage detector, and an amplifier.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: December 14, 2004
    Assignee: Aichi Micro Intelligent Corporation
    Inventors: Yoshinobu Honkura, Masaki Mori, Michiharu Yamamoto, Yoshiaki Koutani
  • Patent number: 6831458
    Abstract: A method and system for detecting a magnetic field utilizing a magnetoresistor of a magnetic sensor is disclosed. A normalized magnetoresistance associated with the magnetoresistor can be calculated such that the magnetoresistor comprises an initial magnetization direction thereof. The magnetic field is generally permitted to exceed an ability of the magnetoresistor to remain pointed in the initial magnetization direction, thereby enabling the magnetoresistor to experience a magnetization reversal thereof. The normalized resistance can be placed into a new state in response to the magnetization reversal thereof, thereby permitting the normalized resistance to be utilized as a switch thereof and allowing the magnetic sensor to detect changes in the magnetic field associated with the magnetoresistor.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: December 14, 2004
    Assignee: Honeywell International Inc.
    Inventors: Michael J. Haji-Sheikh, Ronald W. Chandler
  • Patent number: 6831459
    Abstract: The present invention presents a new approach to rapidly obtaining precise high-dimensional NMR spectral information, named “GFT NMR spectroscopy”, which is based on the phase sensitive joint sampling of the indirect dimensions spanning a subspace of a conventional NMR experiment. The phase-sensitive joint sampling of several indirect dimensions of a high-dimensional NMR experiment leads to largely reduced minimum measurement times when compared to FT NMR. This allows one to avoid the “sampling limited” data collection regime. Concomitantly, the analysis of the resulting chemical shift multiplets, which are edited by the G-matrix transformation, yields increased precision for the measurement of the chemical shifts. Additionally, methods of conducting specific GFT NMR experiments as well as methods of conducting a combination of GFT NMR experiments for rapidly obtaining precise chemical shift assignment and determining the structure of proteins or other molecules are disclosed.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: December 14, 2004
    Assignee: The Research Foundation of State University of New York
    Inventors: Thomas A. Szyperski, Seho Kim, Hanudatta S. Atreya
  • Patent number: 6831460
    Abstract: A coil for creating improved homogeneity in magnetic flux density in a radio frequency resonator for magnetic resonance imaging and spectroscopy of the human head. The coil has a plurality of conductive members. Each of the conductive members has a linear portion and a tapered portion. The conductive members are arranged to form a first opening having a first diameter and a second opening having a second diameter, with the second diameter being different from the first diameter. The tapered portions of the conductive members provide the coil with a substantially homogeneous pattern of magnetic flux density in at least one of three orthogonal imaging planes of the coil.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: December 14, 2004
    Inventors: Theodore J. Reisker, William J. Monski, Eric D. Reid, George J. Misic
  • Patent number: 6831461
    Abstract: In an MR tomography apparatus damping laminated sheets are provided for reducing vibrations The MR tomography apparatus has a magnet body which is surrounded by a magnet housing which surrounds and delimits an interior volume. A gradient coil system is located in this interior volume. On an inner side of the magnet housing that delimits the interior volume, a damping laminated sheet structure is provided for absorbing acoustic vibrations which are produced on switching of the gradient coil system.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: December 14, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventors: Winfried Arz, Franz Boemmel, Peter Dietz, Matthias Weber
  • Patent number: 6831462
    Abstract: It is an object to provide an MR system and a floor cover capable of being attached and detached by one operator. In the invention, the floor cover covers a front face of a lower part of an open type MR system, and a cradle on which an object is mounted swiftly moves thereon. The floor cover is provided with a slide capable of moving on the lower part.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: December 14, 2004
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventors: Seiichi Kitagawa, Yusuke Ikebe
  • Patent number: 6831463
    Abstract: A planar MRI system is disclosed. The system has an open magnet configuration that produces a magnetic field having a remote region of substantial magnetic field homogeneity. Spatial encoding gradient coils and a rf coil provide MRI data for image reconstruction. A first magnet system having a first ferromagnetic core and a first longitudinal axis with a first pair of coils around the first ferromagnetic core and spaced apart along the first longitudinal axis is located orthogonal to and in substantially the same plane as a second magnet system having a second ferromagnetic core and a second longitudinal axis with a second pair of coils around the second ferromagnetic core and spaced apart along the second longitudinal axis. The open magnet configuration preferably has a ferromagnetic core with a substantially planar core surface layer and a longitudinal axis, and a unipolar current wire pair on a side of the ferromagnetic core adjacent the planar core surface layer.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: December 14, 2004
    Assignee: Brigham and Women's Hospital
    Inventor: Yuly M. Pulyer
  • Patent number: 6831464
    Abstract: Automatic Surveillant Revolving Storage Battery Auxiliary Charging System, to compare the value as controlled by an artificial control or the value as set in a central control unit, with a testing signal produced by a battery charge level detector circuit, operating in line with said artificial control or CCU, so as to drive, in a controlled manner, an auxiliary power supply in the form of a D.C. charge converted from an A.C. line feeder, or to drive the engine generator straight, equipped with a variety of operative functions as optional.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: December 14, 2004
    Inventor: Tai-Her Yang
  • Patent number: 6831465
    Abstract: An electrical measurement device is described, with a measurement input, an integrated sensor, a measurement and evaluation circuit, and a measured value display, and several measured value outputs. The electrical measurement device enables not only one measured value or several measured values to be determined, but makes it possible to display and process the determined measured values depending on other values such as comparison values and setpoints. An influencing input acts on the measurement and evaluation circuit and is the connecting point for the electrical measurement device to which or via which an influencing value can be applied or input. Therefore, a value with which the measured value can be influenced in the broadest sense is applied.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: December 14, 2004
    Assignee: i f m electronic GmbH
    Inventors: Benno Kathan, Alfred Wagner
  • Patent number: 6831466
    Abstract: A system and method for controlling operation of a component include using at least two sensors arranged to sense an operating condition of the component. The system further includes a controller that controls the component in response to feedback signals output by one or more of the sensors. The controller also determines how the sensor feedback signals are to be used in controlling the component. To this end, the controller includes a model-based statistical filter for each one of the second sensors.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: December 14, 2004
    Assignee: General Electric Company
    Inventors: John Harry Down, Harry Kirk Mathews
  • Patent number: 6831467
    Abstract: Apparatuses and methods for testing a system having a transient response that is longer than the intervals between stimulations, using a sequence of stimuli containing a small jitter. The timing sequence (called a q-sequence) is constrained by time-domain and frequency-domain rules. The system-response can be recovered from noise, despite response superposition, using deconvolution with a recovery sequence. The acronym QSD means “q-sequence deconvolution”. The invention is especially applicable to signal processing of evoked-responses, including those used for disease screening.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: December 14, 2004
    Assignee: Abratech Corporation
    Inventor: Don Lee Jewett
  • Patent number: 6831468
    Abstract: Methods and apparatuses are described for detecting volumetric moisture content and conductivity in various media based on a time-domain reflectometry (TDR) system wherein successive fast transitions are injected into a transmission line immersed in a medium of interest, and a characteristic received waveform is digitized and analyzed by continuously sampling multiple received waveforms at short time intervals. One method transmits a timing signal along a shielded transmission line while a coincident signal is transmitted through the medium of interest. Another method propagates the waveform along a transmission line, that may be either shorted or open-ended, and observes a reflected, rather than transmitted, waveform with a receiver connected to the same end of the transmission line as the transmitter.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: December 14, 2004
    Assignee: Technical Development Consultants, Inc.
    Inventors: Scott K. Anderson, Hyrum S. Anderson
  • Patent number: 6831469
    Abstract: A micropower apparatus and method for milliohm resistance detection includes a drive circuit and a monitoring circuit. The drive circuit includes a step up current transformer that is driven by a square wave oscillator via a low pass filter and voltage-driven current source. The drive circuit drives a series arranged test coupon and reference coupon, the latter being exposed to the elements. The coupons are Kelvin connected to the monitoring circuit, which includes a pair of low noise, low offset pre-amplifiers, a pair of post amplifiers connected to outputs of the pair of pre-amplifiers, a pair of full wave rectifiers connected to outputs of the pair of post amplifiers, and a pair of low pass filters connected to the outputs of the pair of full-wave rectifiers. Resistance values of the test and reference coupons can accordingly be monitored ratiometrically to determine a state of a selected environment by, for example, detecting changes in electrical resistance due to corrosion of the test coupon.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: December 14, 2004
    Assignee: Honeywell International Inc.
    Inventors: Donald S. Foreman, Russell D. Braunling, Darryl J. Wrest
  • Patent number: 6831470
    Abstract: A method and apparatus is disclosed for estimating brine water conductivity in a multiphase mixture of brine water and other substances by combining measured mixture permittivity and conductivity with a known or derived relationship between brine water conductivity and brine water permittivity. The mixture permittivity and conductivity are measured using an open-ended coaxial probe or other probes at microwave frequencies. A number of applications for the brine water conductivity estimate are disclosed including making salinity corrections of a dual energy flow meter.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: December 14, 2004
    Assignee: Schlumberger Technology Corporation
    Inventors: Cheng-Gang Xie, Gerard Segeral, Gilles Roux, Paul Hammond
  • Patent number: 6831471
    Abstract: An oxygen sensor interface circuit is configurable on the fly by an electronic controller such as an engine controller to support oxygen sensors having unique interface requirements, to reliably identify various oxygen sensor faults, and to enable rapid detection of a warmed up sensor. The interface circuit is configurable in a first respect to enable operation with any of a number of different sensors, and in a second respect to enable more reliable fault detection, including measurement of leakage to ground or battery.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: December 14, 2004
    Assignee: Delphi Technologies, Inc.
    Inventors: Kevin M. Gertiser, James A. Kinley, Ashraf K. Kamel, Gregory J. Manlove
  • Patent number: 6831472
    Abstract: In a test system, a silicon interconnect is provided that can accommodate a packaged part, such as a Land Grid Array (LGA) package. The interconnect can be made by etching a silicon substrate to form projections therefrom; forming an insulation or passivation layer through deposition or growth; depositing a seed layer over the insulation layer; depositing a metal layer over the seed layer; and etching contact members from the seed and metal layers using a single mask step. In a preferred embodiment, the metal layer is coated with another metal layer that matches the metal of the packaged part's electrical communication nodes. In one embodiment, the contact surfaces of the silicon contact are plated in gold and are planar. Included within the scope of the current invention are at least one method of testing an LGA package and at least one method of allowing electrical communication with a packaged part.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6831473
    Abstract: A calibration circuit for use in automatic test equipment is disclosed. The calibration circuit includes a calibration signal driver having an output and a closed-loop transmission line coupled to the output of the calibration signal driver. A plurality of comparators having respective reference inputs, test signal inputs, and calibration inputs are coupled to the closed-loop transmission line. The plurality of comparators are adapted to selectively receive calibration signals generated by the driver in parallel along the closed-loop transmission line.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: December 14, 2004
    Assignee: Teradyne, Inc.
    Inventor: Cosmin Iorga
  • Patent number: 6831474
    Abstract: An apparatus and method for testing a plurality of electrical components that are coupled to one another. Further, an electrical selection unit, coupled to the electrical components to be tested, is provided for selecting at least one electrical component to be tested. A parasitic voltage drop in the testing circuit can be at least partially compensated using a control element coupled to the electrical components to be tested. The invention makes it possible, for testing of electrical components on a wafer over a large distance, i.e., several millimeters, to permit automated compensation of interference influences which occur as a result of the lines coupling or connecting the components to be tested.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: December 14, 2004
    Assignee: Infineon Technologies AG
    Inventors: Ute Kollmer, Carsten Linnenbank, Ulrich Schaper, Roland Thewes
  • Patent number: 6831475
    Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud
  • Patent number: 6831476
    Abstract: The speed of on-chip ADC testing of image sensors is increased by testing multiple chips in parallel. A wafer typically contains many individual image sensor chips. In a parallel on-chip test procedure, power is applied to a plurality of the image sensor chips and the chips are then tested in parallel. Additional power lines may need to be added to the wafer to allow power to be supplied to a plurality of the image sensor chips at once. These power lines may be etched directly on the wafer, or a wafer master may be used to overlay the wafer with the power lines for testing purposes. Additionally, test engines may be added to the wafer map to control the overall test procedures.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Kwang-Bo Cho
  • Patent number: 6831477
    Abstract: An identification is made of an abnormal condition in a motor due to an influence of a disturbance voltage, without addition of hardware, by estimating the disturbance voltage based on a target voltage and actual current flowing in the motor.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: December 14, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kouji Fukusumi, Masahiko Kurishige, Noriyuki Inoue, Seiji Sakanishi, Kenichi Kawakami, Takayuki Kifuku
  • Patent number: 6831478
    Abstract: The open-drain type output buffer includes a first driver and at east one of (1) at least one secondary driver and (2) at least one tertiary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary and tertiary drivers have first and second states. Each secondary and tertiary driver pulls the output node towards the low voltage when in the first state, and pulls the output node towards the low voltage in the second state. A control circuit, when a secondary driver is included, controls the secondary driver such that the secondary driver is in the second state when it has been determined that at least two consecutive low voltage output data have been generated. The control circuit, when a tertiary driver is included, controls the tertiary driver such that the tertiary driver is in the first state when a transition from a steady high voltage output data to a low voltage output data is determined.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: December 14, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Hwan Choi
  • Patent number: 6831479
    Abstract: A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: December 14, 2004
    Assignee: Marvell International Ltd.
    Inventor: William Lo
  • Patent number: 6831480
    Abstract: Programmable logic device integrated circuitry having I/O circuitry portions having different maximum speed capabilities and different amounts of programmability for supporting various I/O signaling standards is provided. High-speed I/O circuitry and low-speed I/O circuitry may be provided. The high-speed I/O circuitry may have differential I/O drivers and may not be programmable. Relatively few I/O lines may be connected to the high-speed I/O circuitry. The low-speed I/O circuitry may be programmable so that a user may configure the low-speed I/O circuitry to support different I/O signaling standards. Intermediate-speed I/O circuitry may be provided that is more flexible than the high-speed circuitry and operates at higher maximum I/O data rates than the low-speed I/O circuitry.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: December 14, 2004
    Assignee: Altera Corporation
    Inventors: Sergey Y. Shumarayev, Rakesh H. Patel
  • Patent number: 6831481
    Abstract: Area-efficient power-up and enable control circuits useful in PLD interconnection arrays. A control circuit can include a driver circuit, first and second pull-ups, and first and second pull-downs. The driver circuit has an output terminal coupled to a control circuit output terminal. The first and second pull-ups are coupled in series between the control circuit output terminal and power high. The first pull-up has a gate terminal coupled to an enable terminal. The second pull-up has a gate terminal coupled to a pull-up control terminal. The first and second pull-downs are coupled in parallel between the control circuit output terminal and ground. The first pull-down has a gate terminal coupled to the enable terminal. The second pull-down has a gate terminal coupled to a pull-down control terminal. In other embodiments, the first and second pull-ups are coupled in parallel, and the first and second pull-downs are coupled in series.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: December 14, 2004
    Assignee: Xilinx, Inc.
    Inventors: Andy T. Nguyen, Shankar Lakkapragada
  • Patent number: 6831482
    Abstract: A latch is provided which includes: a transparent catch latch having a data input, a data output and a control node arranged to receive a catch signal; a transparent pass latch having a data input connected to the data output of the transparent catch latch at an internal storage node, a data output, and a control node arranged to receive a pass signal; and logic circuitry having an enable input and a clock input connected to provide a gated clock signal to provide one of said catch signal and said pass signal. In another aspect an integrated circuit is provided with input and output guard flops, each including a transparent catch latch and a transparent pass latch, and further including a logic gate with an enable input and a clock input connected to provide a gated clock signal to at least one of the transparent pass latch of the input guard-flop and transparent catch latch of the output guard flop.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: December 14, 2004
    Assignee: Azuro (UK) Limited
    Inventors: Paul Alexander Cunningham, Stephen Paul Wilcox
  • Patent number: 6831483
    Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: December 14, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhisa Shimazaki, Motoi Ichihashi
  • Patent number: 6831484
    Abstract: A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: December 14, 2004
    Assignee: NEC Electronics Corporation
    Inventors: Susumu Takano, Hiroyuki Takahashi, Minoru Nizaka, Tomohiro Kitano
  • Patent number: 6831485
    Abstract: A phase frequency detector with a narrow control pulse comprises mainly two substantially equivalent phase latches with a narrow control pulse, and a reset signal generating unit. Each phase latch of a narrow control pulse has a clock pulse input end and a signal output end. Both latches also are connected to the reset signal generating unit. The logic value of each signal output end is decided by which clock pulse input appears first. The reset signal generating unit decides whether or not to generate a reset signal according to the logic values of both signal output ends. The reset signal is then sent to both phase latches of a narrow control pulse, if generated. The present invention can be implemented by a simple circuit. Comparing with the RS NAND PFD or master-slave D PFD, the PFD of the invention has the advantages of faster speed, saving more power and smaller IC chip area.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: December 14, 2004
    Assignee: National Chiao Tung University
    Inventors: Chen-Yi Lee, Pao-Lung Chen
  • Patent number: 6831486
    Abstract: The Floating Diffusion charge detection system has incorporated a signal feedback directly into the charge-detection node. The feedback is coupled to the node from the output of the standard buffer amplifier A1 through a feedback amplifier A3, switching transistors S2 and S3, and capacitors Cf and Ch. The feedback significantly reduces kTC noise, has good linearity, and improves DR.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: December 14, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Jaroslav Hynecek