Abstract: A driver stage uses a primary driver and a secondary driver to balance drive current when transmitting a new data bit different than bits consecutively transmitted immediately previous to the new data bit. The primary driver activates one of a pull-down device and a pull-up device whenever transmitting a data bit. The secondary driver activates one of its pull-down device and a pull-up device when two or more consecutive are detected to be transmitted. In this case, current flow of the driver stage induced by the first of the consecutive bits is reduced by the secondary driver.

Abstract: One end of a control signal line having a buffer is connected to a control terminal. The other end of the control signal line is connected to a third terminal of an input/output logic changing circuit, a gate of a PMOSFET, and a gate of an NMOSFET. An input terminal is connected to a first terminal of the logic changing circuit. A second terminal of the logic changing circuit is connected to an output terminal. These elements are provided on a semiconductor chip. When the input terminal is in an open state, the PMOSFET and the NMOSFET functioning as pull-up and pull-down MOS transistors, respectively, are controlled by a control signal on the control signal line. When an input signal is applied to the input terminal, the logic changing circuit determines a logic level of an output signal based on the input signal and the control signal to thereby output the output signal to the output terminal.

Abstract: A frequency divider circuit is disclosed that generates output signals having a frequency substantially half of the frequency of the input signal. The circuit comprises two D-Flip-Flop circuits wherein one employs the said input signal and the other one employs the complement of the said input signal, and each of the two D-Flip-Flop circuits consists of a pair of loading transistors, two regenerative pairs coupled with each others, and two common-gate switches.

Abstract: A clock synchronization circuit for generating an output clock signal that is in synchronization with a reference clock signal and a method embodying the principle of operation of the circuit are disclosed. The circuit has a programmable delay element and a phase detector. Synchronization is reached when the phase difference between the two clock signals is less than a predetermined value. The programmable delay element is coupled to the reference clock signal for introducing an adjustable delay in the reference clock signal to produce the output clock signal. By increasing the adjustable delay, the output clock signal becomes increasingly closer to being in synchronization with the reference clock signal. The phase detector is coupled to the reference clock signal and the output clock signal for detecting the phase difference between the two clock signals. The adjustable delay is increased until synchronization is obtained.

Abstract: Tracking error in phase locked loop (PLL) devices is addressed utilizing feed-forward phase modulation. Specifically, the phase difference of the reference signal and said oscillator signal of a PLL may be determined utilizing a phase detector. The output of the phase detector may be provided to a loop filter to provide feedback to the VCO of the PLL. Additionally, the filtered phase difference may be provided to a suitably calibrated phase modulator to add an amount of phase modulation to the oscillator signal that is approximately equal and opposite to said phase difference to generate a corrected phase output signal.

Abstract: A delay-locked loop for outputting a precisely signal relative to an input reference signal includes a plurality of selectively controlled delay elements and a delay element control circuit, including a phase detector for detecting a phase shift between the input reference signal and the delayed output signal and producing an error signal. Each of the delay elements includes a first input associated with a negative output and a second input associated with a positive output, whereby the positive and negative outputs are selectively coupled to a constant voltage source responsive to a first bias voltage and to a ground. The positive and negative outputs are responsive to a second bias voltage and the first and second voltage inputs. The constant voltage source and the positive output are coupled via a first transistor and the constant voltage source and negative output are coupled via being a second transistor.

Abstract: A duty cycle regulator derives from an input clock of arbitrary duty cycle, an output clock having an adjustable duty cycle of similar frequency. The duty cycle regulator includes a bistable circuit for receiving an input clock pulse and providing the output clock, coupled through a feedback loop to an adjustable delay unit having a delay interval equal to an adjustable fraction of the input clock period. When an input clock pulse is received, the bistable circuit is set, providing a high signal to the delay unit, after which the delay interval resets the bistable circuit to provide a low signal. The delay unit includes two charge pumps alternately feeding and draining electric charges into and from a low-pass filter. The delay interval can be adjusted to a desired duty cycle independent of the input clock frequency, by setting the ratio of electric currents through the two charge pumps.

Abstract: A method and system of voltage compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of voltage compensation.

Abstract: A flip-flop is disclosed. The flip-flop includes a first latch for receiving at least one bit and a second latch coupled to the first latch for storing the at least one bit from the first latch. The size of the second latch is minimized to reduce power consumption. The flip-flop also includes a multiplexor coupled to the first latch and to the second latch for outputting the at least one bit from the first latch, when a clock to the multiplexor is active and for outputting the at least one bit from the second latch when the clock is inactive. A system and method in accordance with the present invention optimize power consumption in a flip-flop through the use of a multiplexor for the output function. As a result, the size of the slave latch can be minimized, which reduces the overall power consumption of the device.

Abstract: An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

Abstract: An active quadrature signal generator produces poly-phase quadrature signals necessary in high frequency transmit and receive elements of a communication system. The quadrature signals are produced using the phase difference between a load representing a low-pass filter characteristic and a load representing a high-pass filter characteristic and the quadrature signal is then used in the differential structure to produce amplified signal having 4 quadrature phases. The device can reduce a loss characteristic of the signal and additional power consumption for compensating for it in a common poly-phase quadrature filter having only conventional resistors and capacitor.

Abstract: A means of high speed switching of a current source is accomplished by switching the source of the output current source transistor while employing circuitry to limit the movement of the source. The primary capacitance is the source diode, and the charge for this comes from a power rail. This results in both a reduction of and a good match of transients coupling to the output. Circuitry is also added to compensate for any current remaining when the current source is switched off.

Abstract: An n-channel MOS transistor negative-voltage charge pump is disclosed in which the bulks of the n-channel MOS transistors are biased in such a manner as to prevent turning on the parasitic bipolar transistor inherent in the CMOS environment of the charge pump structure.

Abstract: A voltage boosting circuit in which a changing rate of current is limited to reduce noise. An oscillator circuit sends a plurality of oscillating signals differing in edge timing from each other. An enable circuit counts the number of the edges of at least one of the oscillating signals from a start of a boosting operation, and generates an enable signal for instructing a boosting power control circuit to reduce the boosting power of the corresponding one of pumping circuits until the count value becomes a set value. The boosting power control circuit controls the boosting power of each pumping circuit in response to the enable signal. Each pumping circuit performs a boosting operation by charging and discharging a pumping capacitor by using the corresponding one of the oscillated signals. The pumping circuits generate a boosted voltage by combining their outputs signals.

Abstract: A current source circuit with common-mode differential gain boosting is provided. The current source circuit differentially provides first and second currents. The first current is produced by a first cascoded current source, and the second current is produced by a second cascoded current source. Each of the cascoded current sources comprises a current source transistor and a cascode transistor. The current source circuit has high output impedance utilizing gain-boosting techniques. A three-input differential amplifier forces a gate of the cascode transistor of each of the current source circuits to an approximately constant voltage. The three-input differential amplifier is configured to receive a bias signal. The current source circuit is arranged to servo both the gate and source of the cascode transistors in response to the bias signal.

Abstract: An internal power-source potential supply circuit for supplying an internal power-source potential with high accuracy is disclosed. An external power-source potential (VCE) is connected to the source of a PMOS transistor (Q1) having a drain for applying an internal power-source potential (VCI) to a load (11) and a gate receiving a control signal (S1) from a comparator (1). The comparator (1) outputs the control signal (S1) on the basis of a comparison result between a reference potential (Vref) and a divided internal power-source potential (DCI). The drain of the PMOS transistor (Q1) is connected to a first end of a resistor (R1), and a current source (2) is connected between a second end of the resistor (R1) and ground. A voltage provided at a node (N1) serving as the second end of the resistor (R1) is applied to a positive input of the comparator (1) as the divided internal power-source potential (DCI).

Abstract: A current or voltage generator is integrated onto a silicon wafer and may include a first element including a first NMOS transistor having its source connected to ground through an electrical resistance, a second element including a second NMOS transistor having its source connected to ground, and a bias circuit for the first and second elements. The second element may include a voltage divider. The gate of the second NMOS transistor may be connected to a dividing node of the voltage divider, and the anode of the voltage divider may be connected to the gate of the first NMOS transistor. Both elements may be biased at an operating point corresponding to an identical temperature stability point for both elements.

Abstract: A current source includes a first circuit branch of a pair of diode-connected transistors with a resistor connected at the drain terminal and a second circuit branch of an inverter pair of transistors. Both of the circuit branches are supplied by a first current source powered by a supply voltage. The transistors are biased in the subthreshold region and have non-nominal size ratios. A first voltage and a second voltage are established across the resistor and the voltage difference causes a current proportional to absolute temperature to flow in the resistor. The second circuit branch functions as an error amplifier providing an “error signal” to facilitate voltage regulation. The regulation is realized in a third circuit branch which receives the “error signal” and draws excess current from the first current source so that the first voltage and the second voltage remain at the ideal regulated operation point.

Abstract: A reference voltage circuit includes three PMOS transistors and two NMOS transistors. The three PMOS transistors constitute a current mirror circuit and the two NMOS transistors constitute a load circuit. A dummy NMOS transistor is added to the load circuit so as to make three NMOS transistors correspond to the three PMOS transistors and a ratio of currents leaking through PN junctions of diffusion layers on the side of the current mirror circuit is set equal to a ratio of currents leaking through PN junctions of diffusion layers on the side of the load circuit. This allows the reference voltage circuit to output a reference voltage that does not change with temperature even at high temperatures.

Abstract: The present invention provides a reconfigurable filter having a bandwidth and frequency offset that are independently configured, thereby allowing the filter to realize any filter pole. In general, the filter includes a filtering stage and a reverse gain stage. The filtering stage has a bandwidth configured by a bandwidth control signal from control logic and a frequency offset configured by an offset control signal. The reverse gain stage provides the offset control signal to the filtering stage based a reverse gain control signal from the control logic and the output signal. Based on the bandwidth control signal and the reverse gain control signal, the bandwidth of the filter is configured independently from the frequency offset of the filter and the frequency offset is configured independently from the bandwidth.

Abstract: A transconductance difference amplifier (300) is described, for providing an output current dependent upon a difference between a first input voltage (302) and a second input voltage (304). The difference amplifier comprises an input sampling capacitor (306) having two conductors; a transconductance amplifier (312) having an input (318) coupled to a first conductor of said input sampling capacitor and a current output (314) for generating said output current; and an input switch (308, 310) for selectively coupling a second conductor of said input sampling capacitor to a first input of said difference amplifier for receiving said first input voltage and to a second input of said difference amplifier for receiving said second input voltage.

Abstract: A reduction is made in signal distortion that occurs in an output signal of a PWM switching power amplifier due to noise disturbances from a switching power supply. In a switching power amplifier that has a switching power supply unit, a clock signal for controlling the switching of the switching power supply unit is generated based on a clock signal that is used to synchronize switching operations. The clock signal has a clock period that is an integer multiple of a period t of the clock signal and matches a timing at which a signal level of a PWM power signal that is generated by the switching power amplifier is at ground level. The switching of the switching power supply unit is synchronized using the clock signal.

Abstract: To provide a new switching amplifier in which power supply switching noise is reduced to improve the quality. The switching amplifier is provided with a power amplifier (1) that has a modulator which modulates an analog signal or a multi bit digital signal into a two-level signal, and supplies an output pulse signal from this modulator to a power switching element (3); and a &Dgr;&Sgr; power supply (5) which is provided with a &Dgr;&Sgr; modulating device, and the construction is such that the output pulse signal from the modulator of the power amplifier (1) is supplied to the &Dgr;&Sgr; power supply (5), and also the construction is such that the &Dgr;&Sgr; power supply (5) receives the pulse signal as an operating clock, &Dgr;&Sgr; modulates the received pulse signal, and supplies the &Dgr;&Sgr; modulated pulse signal to the power switching element (3).

Abstract: A signal processing module provides high-gain amplification of received signals, while canceling some or all low-frequency error in the received signal. The signal processing module includes a multi-stage amplification series and a low-frequency error cancellation feedback loop.

Abstract: An apparatus for improving linearity of an RF signal comprising: (a) a splitter configured to receive an input RF signal, and configured to split the input RF signal into two RF signals comprising a first input RF signal, and a second input RF signal; (b) an over-biased non-linear RF power amplifier configured to receive the first input RF signal and configured to generate an over-biased non-linear output signal having an over-biased non-linear distortion component; (c) an under-biased non-linear RF power amplifier configured to receive the second input RF signal and configured to generate an under-biased non-linear output signal having an under-biased non-linear distortion component; and (d) a combiner configured to combine the over-biased non-linear output signal and the under-biased non-linear output signal, and configured to output the RF signal having substantially cancelled over-biased and under-biased distortion components.

Abstract: An amplifier linearizer includes a signal adjuster having an internal signal, and an adaptation controller for monitoring the signal adjuster. The internal signal at an input to the adaptation controller is deemed a monitor signal. The adaptation controller generates a control signal for the signal adjuster by accounting for a difference between the internal and monitor signals.

Abstract: A differential amplifier includes a first diode having a first terminal and a second terminal wherein the first terminal is coupled to a voltage node and the second terminal is coupled to a first node, a second diode having a first terminal and a second terminal wherein the first terminal of the second diode is coupled to the voltage node and the second terminal of the second diode is coupled to a second node, a first transistor coupled to the first node in series with the first diode and having a control terminal coupled to a first input terminal, a second transistor coupled to the second node in series with the second diode and having a control terminal coupled to a second input terminal, and a bias current supply coupled to the first and second nodes to bias the first and second diodes.

Abstract: A high output current negative feedback power amplifier amplifies an input signal by use of a monolithic operated amplifier with a current limiting resistor in its output path. The output current of the amplifier is automatically increased when the voltage drop across the current limiting resistor increases beyond a predetermined point and global current limiting automatically occurs when the output current of the monolithic amplifier exceeds a predetermined point.

Abstract: An improved circuit and method is provided that can increase the slew rate of an operational amplifier without adversely affecting its response time. An operational amplifier comprises a large signal detector, a bias circuit having a bias override component, and a bias decay circuit. As a result, the operational amplifier provides the ability to control the increase in current supplied to its compensation capacitors while also providing a smooth transition to the decay phase. In accordance with an exemplary embodiment of the present invention, an exponential decay to the increased bias condition is provided.

Abstract: A differential amplifier (10, 60) is formed to have a propagation delay that varied responsively to a control signal received on a differential control signal input. The propagation delay is varied by changing the bias current of a pair of differential input transistor (11, 13).

Abstract: A system (100) and method (200) for adaptively managing bias of an RF power amplifier (102) is provided. The system (100) incorporates a controller (116) configured to select a radio operating mode. A current-mirror circuit (114) is coupled to the controller (116) and configured to produce a reference current (IRef) as a function of the radio operating mode. A bias regulator (104) is coupled to the controller (116) and the current-mirror circuit (114) and configured to produce a driver-stage bias current (Ib1) and an output-stage bias current (Ib2) for the power amplifier (102) in response to the reference current (IRef). The system (100) also incorporates a DC-to-DC converter (118) coupled to the controller (116) and configured to provide a supply voltage (Vcc) for the power amplifier (102) in response to the radio operating mode. The system (100) also incorporates an envelope detector (120) configured to produce an envelope current (IEnv) in response to an RF input signal (126).

Abstract: The present invention provides improved techniques for controlling current flow in an amplifier circuit. Specific embodiments provide steering of analog outputs of digital to analog converters in order to drive columns of an LCD display. Embodiments can provide a full range of voltage output to drive an LCD display without necessitating a full range amplifier configuration. Further, many specific embodiments can be realized in smaller space on an IC chip than in conventional technologies.

Abstract: Circuitry for allowing efficient pulse-type enhancement of the voltage supplied to a power amplifier fed by a power supply that is connected to the power amplifier at a first feeding point through a main supply path that is connected via a component having high impedance to an enhancement pulse at the feeding point, and to a second feeding point.

Abstract: An amplifier circuit apparatus for driving a laser device, the apparatus comprising a multistage amplifier including an output stage, wherein at least one device for band limiting a signal is coupled to the multistage amplifier prior to the output stage.

Abstract: An input branch of a loss-of-signal (LOS) detector is coupled to a first input of a comparator. A threshold branch of the LOS detector is coupled to a second input of the comparator. An operational amplifier is connected between the input branch and the threshold branch to couple an offset level from the input branch to the threshold branch. The offset level is then cancelled at the comparator.

Abstract: A method is provided for optimizing the performance of laser-pumped atomic frequency references with respect to the laser detuning and other operating parameters. This method is based on the new understanding that the frequency references short-term instability is minimized when (a) the laser frequency is tuned nominally a few tens of MHz away from the center of the atomic absorption line, and (b) the external oscillator lock modulation frequency is set either far below or far above the inverse of the optical pumping time of the atoms.

Abstract: An internal frequency reference, such as a VCO used in a PLL, having a free-running frequency fairly well controlled within a predictable range, is used to determine which of two possible modes of operation, a referenceless or reference clock mode of operation, is used based on a detected frequency of an externally-provided frequency reference signal. The frequency is detected without any additional externally provided signal to indicate the mode of operation or the frequency of the reference clock. If the frequency detection circuit detects a frequency below a predetermined threshold, referenceless mode of operation is indicated. Otherwise, reference clock mode of operation is indicated. In referenceless mode of operation such operations as frequency acquisition and lock detect are performed without the use of a reference clock. In reference clock mode the reference clock is used for such operations as frequency acquisition and lock detect.

Abstract: According to one embodiment of the invention, a ring oscillator is provided that includes a number of stages, each of the stages being coupled to an output of at least two previous stages. This architecture is referred to hereinafter as a “feed forward” architecture, as signals are fed forward to further stages beyond a consecutive stage. Any number of stages may be used. This architecture represents a new topology for ring oscillator design, as ring oscillators generally include consecutive stages that each have an input from the previous stage only. In general, such an architecture achieves higher frequencies than oscillators without feed forward paths.

Abstract: Two oscillators produce respective signals at two different frequencies each dependent upon a parameter such as temperature in accordance with a polynomial with coefficients which are different for the two oscillators. A ratio of the frequencies is inverse to a ratio of a selected one of the coefficients of the polynomials. A mixer produces, at a sum or difference frequency of the two signals, an output signal for which a corresponding coefficient of a respective polynomial is substantially zero. The arrangement can be cascaded to produce zero coefficients for a plurality of terms in the polynomial.

Abstract: A method and a circuit for modulating a carrier signal (Se) with a signal (SCj) having at least a modulation cell (CMi) by phase shift for receiving two digital control signals (Scji, SCji2) representing at least part of the digital modulation signal (SCj). For at least a value of the digital modulation signal (SCj), the method consists in applying on at least a common modulation cell (CMi), two digital control signals (SCji1, SCji2) of identical value, the modulation cell (CMi) delivering a signal, called a modulated elementary signal (Ssi), which is null for the digital modulation signal value (SCj).

Abstract: An insertion box provides a plurality of input and output ports. Each input port corresponds with a predefined and unchanging set of output ports. Insertion of a signal into a particular input port results in that signal being delivered to each of the corresponding output ports. The dissemination functionality is performed by RF circuitry that is typically housed within the insertion box, and is interposed between the input ports and the output ports. The RF circuitry is composed of combiner circuits and splitter circuits. The RF circuitry is designed so that when a combiner is used as an input stage for a splitter, a transformer, usually used to convert an input or output impedance to match a characteristic line impedance, is eliminated. Elimination of such a transformer results in a concomitant reduction in signal loss.

Abstract: In a high-frequency switching module for use mainly in a communications apparatus and a high-frequency apparatus equipped with the same, the high-frequency switching module has a group of high-frequency terminals provided on the mounting side surface of a multi-layer assembly of which the lateral sides are formed as no-electrode provided sides excluding the high-frequency terminals. Thus, the high-frequency switching module and the high-frequency apparatus equipped with the same are less susceptible to the external effect.

Abstract: A feed-through filter capacitor assembly using an electrically conductive adhesive modified with a filler of low coefficient of thermal expansion (CTE) to provide a conductive relation between the conductive pin and the electrode plates of the ceramic capacitor. The conductive adhesive contains an organic polymer-based adhesive component that has a CTE greater than the CTE of the capacitor ceramic body and a conductive metal filler having a CTE lower than the adhesive component. The conductive adhesive is further provided with a CTE-lowering filler that has a CTE lower than the CTE of the conductive metal filler, thereby lowering the overall CTE of the adhesive to a value closer to the CTE of the capacitor ceramic body.

Abstract: A monolithic LC filter which provides increased magnetic field coupling as compared with a conventional monolithic LC filter, without an increase in component size of the filter. The monolithic LC filter includes first and second resonator inductors coupled together by magnetic field coupling. The inductors include parallel-extending straight coupling sections formed by conductive lines which extend in parallel generally along a diagonal of a supporting dielectric layer. This configuration enables the lengths of the coupling sections to be increased as compared with the lengths of the corresponding coupling sections of a conventional monolithic LC filter.

Abstract: There is described a time base comprising a resonator (4) and an integrated electronic circuit (3) for driving the resonator into oscillation and for producing, in response to this oscillation, a signal having a determined frequency. The resonator is an integrated micromechanical tuning fork resonator (4) supported above a substrate (2) and adapted to oscillate in a plane substantially parallel to the substrate. The tuning fork resonator comprises a base member (5) extending substantially perpendicularly from the substrate, a free-standing oscillating structure (6) connected to the base member and including at least a first pair of substantially parallel fork tines (7, 8) and an electrode structure (9) disposed adjacent to the fork tines and connected to the integrated electronic circuit.

Abstract: An electrical relay that uses a conducting liquid in the switching mechanism. In the relay, a pair of fixed electrical contacts is held a small distance from a pair of moveable electrical contacts. The facing surfaces of the contacts each support a droplet of a conducting liquid, such as a liquid metal. A piezoelectric or magnetorestrictive actuator is energized to move the pair of moveable contacts, closing the gap between one of the fixed contacts and one of the moveable contacts, thereby causing conducting liquid droplets to coalesce and form an electrical circuit. At the same time, the gap between the other fixed contact and the other moveable contact is increased, thereby causing conducting liquid droplets to separate and break an electrical circuit. The actuator is then de-energized and the moveable electrical contacts return to their starting positions. The volume of liquid metal is chosen so that liquid metal droplets remain coalesced or separated because of surface tension in the liquid.

Abstract: The present invention provides an electromagnetic relay that has a long service life, even when being used for interrupting high voltage, and that can be miniaturized. In this electromagnetic relay, the circuit interruption is cut-off by two or more keying circuits, which are operated by a single coil and connected in series. Thus, an amount of generated arc per keying circuit is suppressed. Consequently, the service life of the electromagnetic relay is lengthened. Moreover, the space between the contracts thereof is reduced, so that the electromagnetic relay is miniaturized. Additionally, a magnetic field for extinguishing arc is formed by a back or counter electromotive force generated when the circuit is cut-off. Thus, the generated arc is extinguished.

Abstract: A circuit breaker (10, 12) includes a sensing circuit (48, 50, 52), a control circuit (46), an actuator (42), an operating mechanism, and an interlock mechanism (70, 94). The sensing circuit (48, 50, 52) is configured to generate the sense signal representative of a power signal flowing through a power circuit (54, 56, 58). The control circuit (46) has a frame (74, 76) and is configured to receive the sense signal and to provide a trip signal on a first terminal (68). The actuator (42) is external to the control circuit frame (74, 76) and has a second terminal (98) coupleable to the first terminal (68). The actuator (42) is configured to receive the trip signal on the second terminal (98). The operating mechanism is coupled to the actuator (42) and is configured to open and close the power circuit in response to actuation of a lever (36). The actuator (42) is configured to actuate the lever (36) in response to the trip signal.

Abstract: There is disclosed an electromagnetic relay comprising a stationary first member and a second member adapted to move towards and away from the first member such that when the second member move towards the first member an electrical contact is closed. Spring means biases the members apart, and permanent magnet means are provided for generating a force of attraction between the members, and selectively operable means is provided for generating an electromagnetic force. The permanent magnet means has a strength such that when the first and second members are apart the permanent magnet means is insufficient to overcome the spring means, but when the members are brought together the permanent magnet means is able to hold the members together against the spring means.

Abstract: An upper slot motor assembly for a circuit breaker slot motor assembly where the upper slot motor assembly includes a housing assembly and a plurality of plates, and the plates generally correspond to the shape of the housing assembly. The house assembly has a U-shape with a bight, a first and second leg, and a gap between said legs. The gap has a narrow portion and a wide portion. When installed about the circuit breaker separable contacts, the gap narrow portion is located near the stationary contact and the gap wide portion is located near the movable contact when the movable contact is in the open position.