Abstract: The invention describes an apparatus for preventing gripping of objects having wrong dimensions or orientation. The apparatus comprises a part handler, e.g., a holder for parts to be treated in a chemical reactor, where the parts has to be transferred from a working position to a temporary storage. The holder may have different shapes, e.g., rectangular, elliptical, or circular, and is provided with positioning openings or recesses for engagement with pins or semispherical elements on the engaging surface of the part handler. The apparatus is provided with at least two through beam optical sensor units with adjustable divergence of the light beams emitted from the light emitting to the light-receiving element. The sensor units are located near the edge area of the holder.

Abstract: Light-sensitive sensor unit, especially for the automatic switching of illuminating equipment, preferably in motor vehicles, which includes at least two light-sensitive sensors, at least a first sensor and a second sensor detecting the light conditions in predetermined directions. For this purpose, all light-conducting elements allocated to the sensors are to be connected in one piece as a light-conducting member and integrated into the light-conducting member of a rain sensor.

Abstract: The invention relates to a detector for scattered light, especially for detecting particles in a carrier medium. Said detector comprises a housing (1) and an inlet (3) and an outlet (5) in the housing (1). The carrier medium flows through the housing between said inlet and outlet and on a flow path (7). The inventive detector also comprises a light source (9) that directs light to a scattered light centre (11) which lies on the flow path (7). The inventive detector further comprises a receiver (13) for a portion of the light which is scattered onto particles in the scattered light centre (15) and a light trap (15) for light which is not scattered in the scattered light centre (11). The aim of the invention is to improve such a detector for scattered light in such a way that compact construction and high responsiveness are guaranteed. The light trap (15) can be embodied in two ways.

Abstract: A preferred embodiment of a system for measuring a level of a fluid comprises a light source adapted to generate light having a predetermined wavelength, an optical waveguide slab at least partially filled with a material adapted to fluoresce when illuminated by the light having a predetermined wavelength, and a light pipe. The light pipe is adapted to transmit the light having a predetermined wavelength to the optical waveguide slab at an angle that causes the light to be internally reflected only within a portion of the optical waveguide slab located above the fluid thereby illuminating the fluorescent material within the portion of the optical waveguide slab located above the fluid. The preferred embodiment also comprises a photo-multiplier tube adapted to generate an electrical output in response to the fluorescence of the fluorescent material.

Abstract: In a process for producing an alternate striped electrode array in which transparent electrodes alternate with opaque electrodes: the opaque electrodes are formed on a transparent base; a continuous, transparent conductive film is formed on the opaque electrodes and the transparent base; a continuous, negative resist film is formed on the transparent conductive film; a resist pattern corresponding to the opaque electrodes is formed by using the opaque electrodes as a mask and applying a predetermined type of electromagnetic radiation from the back surface of the transparent base to the negative resist film; and the transparent conductive film is etched by using the resist pattern as a mask so that a portion of the transparent conductive film which remains after the etching is separated from the opaque electrodes and forms the transparent electrodes.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: A p-n junction-type compound semiconductor light-emitting device having a substrate formed of a single crystal, a first barrier layer provided on the substrate and formed of a compound semiconductor of a first conduction type, a light-emitting layer provided on the first barrier layer and formed of an indium (In)-containing group III nitride semiconductor of a first or a second conduction type, and an evaporation-preventing layer provided on the light-emitting layer for preventing the evaporation of indium from the light-emitting layer. The evaporation-preventing layer is formed of an undoped boron phosphide (BP)-base semiconductor of a second conduction type. A method for producing the semiconductor-light emitting device is also disclosed.

Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

Abstract: A TFT-LCD device has a plurality of scanning lines formed by a first level metallic layer, a plurality of data lines formed by a second level metallic layer, and an array of pixels each having a TFT and a pixel electrode made of a third level ITO layer. Each pixel further includes a shied ring formed by the second level metallic layer for suppressing variance in the parasitic capacitances formed between the pixel electrode and other conductive layers. The suppression of the variance in the parasitic capacitances reduces the feed-through voltage, thereby improving the display performance of the TFT-LCD device.

Abstract: A device for seating a semiconductor device in a semiconductor test handler is provided. The device includes a plate having a plurality of device seating members each for seating the semiconductor device. The device also includes a latch rotatably mounted to one side of the device seating member for pressing down or freeing the semiconductor device seated on the device seating member. A latch operating means for causing the latch to press down the semiconductor device when the semiconductor device is seated on the device seating member is also included. The provided device also releases the pressing down action when the semiconductor device is seated on the device seating member and when the semiconductor device is taken away from the device seating member, thereby seating the semiconductor device on the device seating device accurately and positively.

Abstract: To realize a semiconductor device including a capacitor element capable of obtaining a sufficient capacitor without reducing an opening ratio, in which a pixel electrode is flattened in order to control a defect in orientation of liquid crystal. A semiconductor device of the present invention includes a light-shielding film formed on the thin film transistor, a capacitor insulating film formed on the light-shielding film, a conductive layer formed on the capacitor insulating film, and a pixel electrode that is formed so as to be electrically connected to the conductive layer, in which a storage capacitor element comprises the light-shielding film, the capacitor insulating film, and the conductive layer, whereby an area of a region serving as the capacitor element can be increased.

Abstract: A dual panel-type organic electroluminescent display device includes a first substrate and a second substrate bonded together to include a plurality of sub-pixel regions, a first electrode on an inner surface of the second substrate, an insulating pattern on the first electrode along a border portion between adjacent sub-pixel regions, a plurality of partition walls on the insulating pattern, a plurality of organic electroluminescent layers, each within one of the sub-pixel regions between adjacent partition walls, a second electrode on the organic electroluminescent layer, a plurality of thin film transistors on an inner surface of the first substrate each within one of the sub-pixel regions, and including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, a passivation layer covering the thin film transistors and including a contact hole exposing the drain electrode, and a plurality of connection patterns on the passivation layer, each including a first pattern and a second

Abstract: In a conventional analog buffer circuit composed of polycrystalline semiconductor TFTs, a variation in the output is large. Thus, a measure such as to provide a correction circuit has been taken. However, there has been such a problem that a circuit and driver operation are complicated. Therefore, a gate length and a gate width of a TFT composing an analog buffer circuit is set to be larger. Also, a multi-gate structure is adopted thereto. In addition, the arrangement of channel regions is devised. Thus, the analog buffer circuit having a small variation is obtained without using a correction circuit, and a semiconductor device having a small variation can be provided.

Abstract: In a semiconductor light emitting device configured to extract light through a substrate thereof, an electrode layer is formed on a p-type semiconductor layer (such as p-type GaN layer) formed on an active layer, and a nickel layer is formed as a contact metal layer between the electrode layer and the p-type semiconductor layer and adjusted in thickness not to exceed the intrusion length of light generated in the active layer. Since the nickel layer is sufficiently thin, reflection efficiency can be enhanced.

Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.

Abstract: Light-emitting devices, and related components, systems and methods are disclosed.

Abstract: A light source that utilizes light emitting diodes that emit white light is disclosed. The diodes are mounted on an elongate member having at least two surfaces upon which the light emitting diodes are mounted. The elongate member is thermally conductive and is utilized to cool the light emitting diodes. In the illustrative embodiment, the elongate member is a tubular member through which a heat transfer medium flows.

Abstract: A pn-junction-type semiconductor light-emitting device having a single-crystal silicon (Si) substrate of first conduction type; a first boron-phosphide-based semiconductor layer of first conduction type provided on the substrate; a light-emitting layer formed of a Group III-V semiconductor layer of first or second conduction type which is doped with an element belonging to Group IV of the periodic table provided on the first boron-phosphide-based semiconductor layer; and second boron-phosphide-based semiconductor layer of second conduction type formed of a boron-phosphide-based semiconductor layer of second conduction type containing a Group IV element provided on the light-emitting layer. The first boron-phosphide-based semiconductor layer, the light-emitting layer, and the second boron-phosphide-based semiconductor layer form a pn-junction-type hetero structure. In addition, the second conduction type is opposite the first conduction type. Also, disclosed is a method for producing the device.

Abstract: A group III nitride compound semiconductor light-emitting element of a flip chip bonding type for emitting light with a wavelength not longer than 400 nm is coupled to a Zener diode, and the light-emitting element and the Zener diode coupled to each other are sealed with a metal casing having a window.

Abstract: An extended length light emitting diode suitable for auto-insertion including an extended LED body region serving as a standoff or spacer to provide supported spacing from a circuit board to extend the LED die through a faceplate for suitable viewing and to serve as a structure through and about which the lower body portion of the LED and the LED leads can be stabilized and sealed to a printed circuit board. An alternative embodiment includes structure for sealing an LED to a faceplate.

Abstract: An object of the present invention is to provide a novel semiconductor mounting system having a semiconductor mounting member, a metal member and a joining layer joining the mounting and metal members, to improve the flatness of a mounting surface and to control the temperature on the surface of a semiconductor. A semiconductor mounting system 12 has a semiconductor mounting member 1, a metal member 7 and a joining layer 27 joining the mounting member 1 and metal member 7. The metal member 1 has a surface mounting a semiconductor. The adhesive sheet 4 has a resin matrix 11 and a filler 10 dispersed in the resin matrix 11.

Abstract: A semiconductor light detecting device has a light absorbing layer; and a pn junction, carriers generated by the light absorbing layer absorbing the light in a light detecting region being detected as a photoelectric current through a depletion layer provided by applying a backward voltage to the pn junction, wherein the light detecting region in the light absorbing layer is all depleted in a slate where an operating voltage is applied.

Abstract: A unipolar photodiode and methods of making and using employ a Schottky contact as a cathode contact. The Schottky cathode contact is created directly on a carrier traveling or collector layer of the unipolar photodiode resulting in a simpler overall structure to use and make. The unipolar photodiode comprises a light absorption layer, the collector layer adjacent to the light absorption layer, the Schottky cathode contact in direct contact with the collector layer, and an anode contact either directly or indirectly interfaced to the light absorption layer. The light absorption layer has a doping concentration that is greater than a doping concentration of the collector layer. The light absorption layer has a band gap energy that is less than that of the collector layer. The light absorption layer and the collector layer may be of the same or opposite conduction type.

Abstract: A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

Abstract: A conventional solid-state imaging device in which a sealing resin is applied onto a microlens has a low condensing efficiency. There are provided a photodiode 14 for receiving light, a microlens 4 made of a resin set on the photodiode 14 and having a refractive index of n3, a thin-film lens 3 formed on the microlens 4 and having a refractive index of n2, a sealing resin 2 formed on the thin-film lens 3 and having a refractive index of n1, and cover glass 1 formed on the sealing resin 2 to seal the sealing resin 2. The refractive index n2 of the thin-film lens 3 is set to a value smaller than n1 and n3. In this case, it is assumed that values of n1 and n3 are substantially equal to each other and the thin-film lens 3 is made of fluoride and/or oxide.

Abstract: An amorphous layer of a cobalt iron-based (CoFe-based) magnetic alloy suitable for use in magnetoelectronic devices is disclosed. In the most preferred embodiments of the present invention, at least one amorphous layer is provided in an MTJ stack to increase the smoothness of the various layers in the MTJ stack while also enhancing the magnetic performance of the resulting device. Additionally, the alloys of the present invention are also useful in cladding applications to provide electrical flux containment for signal lines in magnetoelectronic devices and as a material for fabricating write heads.

Abstract: A ferroelectric memory (436) includes a plurality of memory cells (73, 82, 100) each containing a ferroelectric thin film (15) including a microscopically composite material having a ferroelectric component (18) and a dielectric component (19), the dielectric component being a different chemical compound than the ferroelectric component. The dielectric component is preferably a fluxor, i.e., a material having a higher crystallization velocity than the ferroelectric component. The addition of the fluxor permits a ferroelectric thin film to be crystallized at a temperature of between 400° C. and 550° C.

Abstract: A magnetoresistive effect element (1) has an arrangement in which a pair of ferromagnetic material layers (magnetization fixed layer (5) and magnetization free layer (7)) is opposed to each other through an intermediate layer (6) to obtain a magnetoresistive change by causing a current to flow in the direction perpendicular to the layer surface, the magnetization free layer (7) is made of a ferromagnetic material containing FeCoB or FeCoNiB and the magnetization free layer (7) has a film thickness ranging from 2 nm to 8 nm. A magnetic memory device comprises this magnetoresistive effect element (1) and bit lines and word lines sandwiching the magnetoresistive effect element (1) in the thickness direction. There are provided the magnetoresistive effect element having satisfactory magnetic characteristics and the magnetic memory device including this magnetoresistive effect element and which can obtain excellent write/read characteristics.

Abstract: Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design.

Abstract: An existent DRAM memory cell comprises transistors as a switch and capacitors for accumulating storage charges in which the height of the capacitor has been increased more and more along with micro miniaturization, which directly leads to increase in the manufacturing cost. The invention of the present application provides a semiconductor memory device of a basic constitution in which a memory cell array having plural memory cells disposed on a semiconductor substrate and word lines and data lines for selecting the memory cells and a peripheral circuit at the periphery of the memory cell array wherein the memory cell comprises a multi-layer of a conductive layer, an insulating layer and plural semiconductor layers containing impurities, and a potential can be applied to the insulating layer enabling the tunneling effect. The invention of the present application concerns a memory cell not requiring capacitor and capable of being formed in simple steps.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A display device driving circuit comprising a thin film transistor array in combination with a charge capacitor and its manufacturing method in which the charge capacitor is formed over an address line for addressing the thin film transistor by depositing first an insulating layer over the address line and then a semiconductor layer. The semiconductor layer is etched to form a protective island. The protective island protects the insulating layer integrity during subsequent etching processes. An upper electrode is formed over the semiconductor layer to complete the charge capacitor. The protection of the insulating layer during subsequent manufacturing steps results in substantially uniform charge capacitors for each TFT in the driving circuit.

Abstract: Methods of forming a uniform cell nitride dielectric layer over varying substrate materials such as an insulation material and a conductive or semiconductive material, methods of forming capacitors having a uniform nitride dielectric layer deposited onto varying substrate materials such as an insulation layer and overlying conductive or semiconductive electrode, and capacitors formed from such methods are provided. In one embodiment of forming a uniform cell nitride layer in a capacitor construction, a surface-modifying agent is implanted into exposed surfaces of an insulation layer of a capacitor container by low angle implantation to alter the surface properties of the insulation layer for enhanced nucleation of the depositing cell nitride material, preferably while rotating the substrate for adequate implantation of the modifying substance along the top corner portion of the container.

Abstract: A memory cell configuration connects two trench capacitors to a bit line through a contact bit terminal. Trench capacitors are disposed in a regular grid. Word and bit lines are disposed in a mutually perpendicular crossover structure. An active region in which a selection transistor of an adjoining trench capacitor is introduced is disposed respectively between two trench capacitors of a row. Trench capacitors of two rows are laterally offset with respect to one another. Two active regions of adjacent rows are electrically connected to one another through a connecting line. Connected active regions form a common terminal region connected to a contact bit terminal, which is connected to a bit line. Bit lines are disposed between rows of trench capacitors and parallel thereto. By reducing the contact bit terminals, capacitances of the bit lines are reduced and interference signal transmission between word line and contact bit terminals is reduced.

Abstract: A semiconductor device that can prevent short-circuit occurring between capacitor electrodes and a method of manufacturing the semiconductor device are obtained. A semiconductor includes two capacitor electrodes formed spaced from each other and including conductive impurities of the first conductivity type, and an electrode isolation film located between the two capacitor electrodes and formed at the same layer as that of the two capacitor electrodes, while including conductive impurities of the second conductivity type different from the first conductivity type. This allows the two capacitor electrodes to be electrically isolated from each other, without the etching step or the like, by introducing conductive impurities of the second conductivity type into a region that is located between the two capacitor electrodes and is formed at the same layer as that of the capacitor electrodes.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: A semiconductor device includes: a conductive plug formed through an insulating film; a conductive oxygen barrier film formed on the insulating film so as to be electrically connected to the conductive plug and to cover the conductive plug; a lower electrode formed on the oxygen barrier film and connected to the oxygen barrier film; a capacitive insulating film formed on the lower electrode, following the lower electrode; and an upper electrode formed on the capacitive insulating film, following the capacitive insulating film. The capacitive insulating film has a bent portion that extends along the direction in which the conductive plug penetrates through the insulating film.

Abstract: A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.

Abstract: A multi-level non-volatile memory transistor is formed in a semiconductor substrate. A conductive polysilicon control gate having opposed sidewalls is insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed sidewalls by thin tunnel oxide. Source and drain implants are beneath or slightly outboard of the spacers. Insulative material is placed over the structure with a hole cut above the control gate for contact by a gate electrode connected to, or part of, a conductive word line. Auxillary low voltage transistors which may be made at the same time as the formation of the memory transistor apply opposite phase clock pulses to source and drain electrodes so that first one side of the memory transistor may be written to, or read, then the other side.

Abstract: A structure is disclosed for split-gate flash memory cells in which isolation regions separate parallel active regions within a semiconductor region. Trapezoidal floating gates, separated from the active regions by an insulator layer, are equally spaced over the active regions. Three tiered parallel strips run perpendicular to the active regions and pass over corresponding trapezoidal floating gates, the bottom and top tiers being insulator layers and the middle tier being a conductor layer. Insulator spacers are disposed over the sidewalls of the three-tiered parallel strips and of the trapezoidal floating gates. These parallel structures are designated floating gate towers. Source/drain regions are formed in the semiconductor region of every other opening between floating gate towers where they are contacted by source/drain contact lines. An insulator layer is disposed over the source/drain contact lines.

Abstract: A vertically structured semiconductor power component is described. A layer thickness of a substrate of the power module between a pn junction and a metallized back is chosen in such a manner that a space charge region produced in the semiconductor component extends as far as the back when a blocking voltage between a source and a drain electrode is applied before a field strength produced by the applied blocking voltage reaches a critical value.

Abstract: The invention concerns an anode voltage sensor of a vertical power component selected from the group consisting of components called thyristor, MOS, IGBT, PMCT, EST, BRT transistor, MOS thyristor, turn-off MOS thyristor, formed by a lightly doped N-type substrate (1) whereof the rear surface (2) having a metallizing coat corresponds to the component anode. Said sensor comprises, on the front surface side, a substrate zone (12) surrounded at least partly by a P-type region with low potential in front of an anode potential, said zone (12) being coated with a metallizing coat (M) in ohmic contact with it, whereon is provided an image of the anode voltage.

Abstract: A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.

Abstract: A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.

Abstract: A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.

Abstract: A microwave transistor structure comprising: (1) a substrate having a top surface; (2) a silicon semiconductor material of a first conductivity type; (3) a conductive gate; (4) a channel region of a second conductivity type; (5) a drain region of the second conductivity type; (6) a body of the first conductivity type; (7) a source region of the second conductivity type; (8) a shield plate region formed on the top surface of the silicon semiconductor material over a portion of the channel region, wherein the shield plate is adjacent and parallel to the drain region, and to the conductive gate region; and (9) a conductive plug region formed in the body region of the silicon semiconductor material, wherein the conductive plug region connects a lateral surface of the body region to the top surface of the substrate.

Abstract: To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region 145 having a P-type behavior more potential than that of a drain region 146 is arranged between a channel forming region 134 and the drain region 146 in the P-channel type thin film transistor whereby the P-channel type thin film transistor having the low OFF characteristic can be provided and a low concentration impurity region 136 is arranged between a channel forming region 137 and a drain region 127 in the N-channel type thin film transistor whereby the N-channel type thin film transistor having the low OFF characteristic and where deterioration is restrained can be provided.

Abstract: A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer. A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device. An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors. The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions. The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region. The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor.

Abstract: A method of fabricating a memory device having a buried source/drain region is provided, in which a dielectric layer and a word-line is sequentially formed on the substrate, then a buried source/drain region is formed in the substrate. After that, a barrier layer is formed on the exposed surface of the word-line, then a metal layer is formed over the substrate. The metal layer is patterned to leave a portion covering the buried source/drain region beside the word-line and crossing over the word-line.

Abstract: A semiconductor device capable of accurately controlling the current value is provided. In a semiconductor integrated circuit having a constant current circuit, the constant current circuit includes a plurality of constant current elements having a gate terminal and a source terminal in common. Branched drain terminals of the constant current element arranged on one end of the gate terminal and the source terminal are arranged to both the gate terminal and the source terminal.