Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

Abstract: A power component formed in an N-type silicon substrate delimited by a P-type wall, having a lower surface including a first P-type region connected to the wall, and an upper surface including a second P-type region, a conductive layer extending above the substrate between the second region and the wall. The component includes a third N-type region of high doping level formed in the substrate under the portion of the layer substantially halfway between the external periphery of the second region and the internal periphery of the wall. This third region is contacted by a field plate extending on either side of the third region in the direction of the wall and of the third region.

Abstract: A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a layer including aluminum nitride disposed over the channel region, and a gate electrode disposed over the insulating layer.

Abstract: A surface acoustic wave device includes a piezoelectric substrate and interdigital electrode portions disposed on the piezoelectric substrate. A functional film including at least one of a silicon nitride film, a silicon oxide film, and a silicon oxide nitride film is formed on the piezoelectric substrate having the interdigital electrode portions such that the functional film is formed on at least a portion of the interdigital electrode portions by an electron cyclotron resonance sputtering method.

Abstract: Ultraviolet light incident from the side of a surface layer 5 passes through the surface layer 5 to reach an optical absorption layer 4. Light which reaches the optical absorption layer 4 is absorbed within the optical absorption layer 4, and photoelectrons are generated within the optical absorption layer 4. Photoelectrons diffuse within the optical absorption layer 4, and reach the interface between the optical absorption layer 4 and the surface layer 5. Because the energy band is curved in the vicinity of the interface between the optical absorption layer 4 and surface layer 5, the energy of the photoelectrons is larger than the electron affinity in the surface layer 5, and so photoelectrons are easily ejected to the outside. Here, the optical absorption layer 4 is formed from an Al0.3Ga0.

Abstract: An optical device includes a substrate, dielectric layers disposed on portions of the substrate, and a piezoelectric layer disposed over the substrate and the dielectric layer, wherein the piezoelectric layer functions as a waveguide in which incident light is transmitted parallel to the surface of the piezoelectric layer. The piezoelectric layer has first piezoelectric layer regions each having an axis orientation directed to a first direction depending on the substrate and second piezoelectric layer regions each having an axis orientation directed to a second direction depending on the dielectric layers, and each of the first piezoelectric layer regions and each of the second piezoelectric layer regions are adjacent. A method manufacturing an optical device includes the steps of forming dielectric layers on portions of a substrate, and forming a piezoelectric layer over the dielectric layers and the substrate.

Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

Abstract: An optical semiconductor device of the present invention is equipped with a photo detect element 10 comprising a photo detect part 7 provided with two photodiodes having two photodiodes having peak wavelength sensitivity in a visible light region and an infrared region, respectively and an amplifying operation processing circuit 8 for amplifying and processing outputs of the photodiodes, and characterized in that substrate resistivity R is as follows: 1≦R≦3(&OHgr;cm)

Abstract: A high withstand voltage semicnductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge.

Abstract: In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. The buried layer may in some embodiments include a first portion underlying the transistor and a second portion spaced apart from and laterally surrounding the first portion. In some embodiments, the circuit may include a doped annular region of the same conductivity type as the buried layer, where the annular region contacts a portion of the buried layer and laterally surrounds the transistor. The circuit may further include metallization adapted to connect the well and annular region to opposite polarities of a power supply voltage, or in some embodiments to preclude such connection.

Abstract: A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.

Abstract: A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical properties and desired chemical properties, and is substantially reactively grown from the semiconducting substrate. A precursor material layer is formed on the bottom of the trench and on the sidewalls of the trench. The precursor material layer has electrical properties and chemical properties that are substantially similar to the desired electrical properties and the desired chemical properties of the isolating material. A substantial portion of the precursor material layer is removed from the bottom of the trench to expose the semiconducting substrate at the bottom of the trench, while leaving a substantial portion of the precursor material layer on the sidewalls of the trench.

Abstract: A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover the structure including a fuse region and an RDL/bump/bonding pad region. A composite metal layer is formed over the intermetal dielectric layer. The composite metal layer including a second metal layer sandwiched between upper and lower first metal layers. The upper first metal layer is patterned to form an upper metal layer portion within the RDL/bump/bonding pad region. The second metal layer and the lower first metal layer are patterned: (1) within the RDL/bump/bonding pad region to form an RDL/bump/bonding pad; the RDL/bump/bonding pad having a patterned second metal layer portion/lower first metal portion with a width greater than that of the upper metal layer portion and forming a step profile; and (2) within the fuse region to form the top-metal fuse structure. The RDL/bump/bonding pad structure includes a step profile.

Abstract: A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness.

Abstract: A switching chip (101) using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink (115), an insulating substrate (114) and a conductive plate (108), with a first conductive layer (109A) sandwiched in between. Further, a diode chip (102) having a smaller area than a cathode electrode (103) and using a wide gap semiconductor as the base material is located on the cathode electrode (103) which has a smaller area than an anode electrode (105), with a second conductive layer (109B) sandwiched in between. A closed container (117) encloses every structural component except an exposed portion of a bottom surface (115BS) in the interior space.

Abstract: An improved lead frame structure for use in a semiconductor package, including: a plurality of leads; a paddle structure electrically isolated from the leads, the paddle structure including at least one lower paddle section having a first top surface to which a die may be attached, at least one mesa section disposed proximate the paddle section and having a second top surface disposed at a different elevation than the first top surface, the lower paddle section and the mesa section being joined by a wall section; and a plurality of tie bars attached to the paddle structure for supporting the paddle structure; whereby contact pads of a die attached to the first top surface may be electrically connected to the second top surface and to the leads prior to encapsulation thereof. A plurality of tie bars extends from opposite edges of the paddle structure, the tie bars providing for stabilizing the paddle structure during package fabrication.

Abstract: An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.

Abstract: A semiconductor packgage includes a semiconductor chip provided with a plurality of electric terminals and a plurality of electrically conductive members electrically connected with the electric terminals. Connection terminals that are spherical in shape and made of solder are electrically connected with the electrically conductive members. A sealing member is used for sealing the semiconductor chip and the electrically conductive members, and for covering the connection terminals so as to allow a part thereof to be exposed. The electrically conductive members are provided with bonding promoters and are connected with the respective spherical connection terminals at the respective bonding promoters.

Abstract: An electronic device including a multi-chip die and a substrate member, said multi-chip die includes a plurality of integrated circuit chips which are integrally formed on the multi-chip die as a unitary member, each the integrated chip includes a plurality of electrodes for making external electrical contacts, the substrate member includes a circuit of a pre-determined pattern and a plurality of electric contacts disposed for making corresponding electrical connections with the electrodes of the integrated chips of the multi-chip die, the plurality of integrated circuit chips of the multi-chip die being connected as a unitary member to the substrate member.

Abstract: A memory array portion, a connection circuit serving as an interface of the memory array portion and a signal wiring connecting the memory array portion to the connection circuit are provided. Mesh wirings comprising first and second wiring layers are provided on the memory array portion. The connection circuit is connected to a plurality of signal lines comprising a third wiring layer provided on the memory array portion, the connection circuit or the signal wiring, through an intermediate wiring comprising the second wiring layer. The region where the intermediate wiring is provide on the memory array portion or on the signal wiring, and the mesh wiring comprising the second wiring layer is not present on the region where the intermediate wiring is provided.

Abstract: A circuit substrate device composed of a circuit unit 2 and a multi-layer wiring substrate 3 in which a pattern conductor of the circuit unit 2 may be prevented from being warped or inundated. The circuit substrate device includes a circuit unit 2 having a pattern conductor formed by a thin film technique, and an insulating layer, and a multi-layer wiring substrate 3 having a connecting terminal portion 14 exposed from its major surface. The circuit unit is formed on a dummy substrate. The circuit unit is connected to the multi-layer wiring substrate 3 so that the pattern conductor is connected to the connecting terminal portion 14. The dummy substrate is then removed to give a structure comprised of the circuit unit 2 formed on the multi-layer wiring substrate 3. The pattern conductor of the circuit unit 2 is freed of warping or inundations along the direction of thickness of the circuit unit 2.

Abstract: A heat-dissipative coating is composed of a plurality of granules having a predetermined thickness and disposed on an object, and is insulated and highly thermal-conductive. The total surface area of the granules is greater than that of the heat-dissipative coating disposed on the object, thereby rendering preferably effective heat-dissipation.

Abstract: The invention relates to a power semiconductor module, in particular a power converter module, with a base plate or for direct installation on a heat sink or other cooling body or means for cooling. The power semiconductor module includes, at least one power semiconductor component, and at least one insulating substrate on whose first surface a metallic layer is provided. A carbon-based layer (including Carbon nano-tubes) is used for at least one of a thermal and a partly electrical contacting, on at least one of the one side for contacting the power semiconductor component with the metallic layer and, (in an alternate embodiment) on the other side to connect the substrate with the heat sink or cooling body.

Abstract: A semiconductor device comprising semiconductor chips each formed with plural pads at the main surface, chip parts each formed with connection terminals at both ends thereof, a module substrate on which the semiconductor chips and the chip parts are mounted, solder connection portions for connecting the chip parts and the substrate terminals of the module substrate by soldering, gold wires for connecting the pads of the semiconductor chips and corresponding substrate terminals of the module substrate, and a sealing portion formed with a low elasticity resin such as an insulative silicone resin or a low elasticity epoxy resin for covering the semiconductor chips, chip parts, solder connection portions and gold wires which prevents flow out of the solder in the solder connection portion by re-melting thereby preventing short-circuit.

Abstract: An apparatus for connecting one substrate, such as a flip-chip type semiconductor die, to an opposing substrate, such as a silicon wafer, printed circuit board, or other substrate is disclosed. Each substrate has a plurality of conductive bumps on its facing surface wherein the conductive bumps on each substrate are the mirror-image of the other substrate. The substrates are attached to one another in a manner in which the conductive bumps on one substrate form an electrical contact with its respective conductive bumps on the opposing substrate without mechanical attachment.

Abstract: The present invention relates to a diffusion barrier layer for a semiconductor device and fabrication method thereof. The diffusion barrier layer according to the present invention is fabricated by forming a diffusion barrier layer containing a refractory metal material and an insulating material on an insulating layer and in a contact hole, wherein the insulating layer being partially etched to form the contact hole, is formed on a semiconductor substrate; and annealing the diffusion barrier layer. Therefore, an object of the present invention is to provide a diffusion barrier layer for a semiconductor device, which is of an amorphous or microcrystalline state and thermodynamically stable even at a high temperature since an insulating material is bonded to a refractory metal material in the diffusion barrier layer.

Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

Abstract: A method and a pattern for reducing interconnect failures are described. The method and pattern are used for a multilevel structure of metal/dielectric/metal. At least one assistant pattern is attached to one metal layer of the multilevel structure. A thermal stress gradient resulting from the assistant pattern can collect vacancies of the metal layer, so as to prevent stress-induced voids from generating at the bottom of a via plug which connects the two metal layers.

Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.

Abstract: A semiconductor device comprises a semiconductor substrate having semiconductor elements integrally formed therein, a wiring layer formed on the surface of the semiconductor substrate, and a conductive connecting plug formed in a through-hole extending through the semiconductor substrate, wherein the connecting plug has a region whose cross section parallel to the upper surface of the semiconductor substrate has an area smaller than the area of each of upper and lower surfaces of the connecting plug.

Abstract: Disclosed is a semiconductor device comprising a substrate, a first region provided on the substrate and comprising a first insulating portion which includes an insulating film having a relative dielectric constant of at most 3.0 and a conductive portion which is provided in the first insulating portion, a second region provided on the substrate, located adjacent to the first region in a direction parallel to a major surface of the substrate and comprising a second insulating portion which is located adjacent to the first insulating portion in the direction and which includes no insulating film having a relative dielectric constant of at most 3.0, and a pad provided on the second region and electrically connected to the conductive portion.

Abstract: An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

Abstract: A multichip cube structure having a foamed insulating material disposed between adjacent integrated circuit chips. The foamed insulating material has lower dielectric constant and therefore reduces the capacitive coupling between electrical interconnects on adjacent chips. The foamed insulating material also has higher ductility and lower thermal coefficient of expansion than conventional oxide insulators so as to reduce the occurrence of stress induced cracking in circuitry.

Abstract: An integrated circuit substrate having embedded wire conductors provides high-density interconnect structure for integrated circuits. Wires are shaped to form a conductive pattern and placed atop a dielectric substrate layer. Additional dielectric is electro-deposited over the wires to form an insulating layer that encapsulates the wires. One or more power planes may be embedded within the substrate and wires within the conductive pattern may be laser-welded to vertical wire stubs previously attached to a power plane. Vias may be formed by mechanically or laser drilling (or plasma or chemical etching) through any power planes and screening a copper paste into the drilled holes to form conductive paths through the holes. Via conductors may then be exposed by a plasma operation that removes dielectric, leaving the ends of the via conductors exposed. Wires within the conductive pattern may then be laser-welded to the via conductor ends.

Abstract: Electronic devices with a semiconductor chip and leadframes with device positions and methods for producing the same are encompassed by the invention. The electronic devices include a semiconductor chip disposed with its rear side on a chip island. The chip island has a coplanar pattern of electrically conductive contact layer regions alternating with insulating adhesion layer regions, which is covered by the semiconductor chip.

Abstract: Apparatus and methods for generating power utilizing the flow of water from an upper water body to a lower water body in order to generate an upward buoyant force on at least one buoyant object located in a chamber. In preferred embodiments, water is recycled between at least two chambers which generate upward and downward strokes of at least two buoyant objects.

Abstract: A fluid power generator system includes an operating mode in which a continuously variable output corresponding to a wide range of a flow rate is given by selectively combining generators with optimum rated outputs from said plurality of generators according to natural fluid energy and the number of rotations of a wing axial shaft; and control means for controlling the operation of each of the generators on the basis of a tip speed calculated from the flow rate of the operative fluid and the number of rotations of said wing axial shaft, thereby acquiring a maximum output for specific flow rate of the operative fluid. In this configuration, the fluid power generator system using operative fluid energy as a driving source can generate a continuously variable output corresponding to a wide range of the flow rate of the fluid and provides a maximum output for an individual flow rate of the operative fluid, thereby increasing a quantity of generated power (by 40% or more than before).

Abstract: A system for use in programming and diagnostics of electronic devices (32) in a vehicle includes a connector jack (36) having a plurality of electrical connection sites configured for electrical connection to the electronic devices (32) in the vehicle. A shorting plug (38) configured to removably engage the connector jack (36) interconnects the plurality of electrical connection sites to form a data communication bus. An electronics module (50) configured to removably engage the connector jack (36) in place of the shorting plug includes a plurality of switching units (56) that, when set in a closed state, electrically interconnect each of the electronic devices (32) to form the data communication bus. Each switching unit (56a, . . . ,56g) in the electronics module (50) is selectively and independently operable to electrically disconnect an electronic device (32) from the data communication bus, especially for programming and diagnostics of the electronic devices (32) in the vehicle.

Abstract: A method and apparatus for unlocking a trunk lid of a motor vehicle is suggested which ensures that a person in the interior of the trunk can free himself from this trunk. For this purpose, an unlocking handle is provided in the interior which, when it is operated and the vehicle is standing still, unlocks the trunk lid. If, when the unlocking handle is operated, the vehicle is driving, a delay time is started after whose expiration the trunk lid is released.

Abstract: A solid-state pulse generator using a split magnetic core transformer is described. In one embodiment, the solid-state drive circuit uses MOSFETs switching a blumlein to produce a desired input pulses in a primary winding of the split magnetic core. The pulse length is determined primarily by the characteristics of the blumlein and the split core transformer. The “on” time of the solid-state devices can exceed the output pulse length, thereby reducing the chance of damaging voltage spikes. The use of a split magnetic core allows several solid-state drive circuits to be used in parallel to produce a single output pulse. In one embodiment, each solid-state drive circuit drives a separate single-turn primary winding of a split magnetic core transformer. In one embodiment, each core of the split core transformer has one primary winding.

Abstract: In a semiconductor integrated circuit device and a contactless electronic device, an AC voltage is applied to first and second input terminals. A rectification transistor having a drain (or collector) connected to a second input terminal and gate (or base) and drain (or collector) connected to each other through a first resistor supplies a rectified current between the first and second input terminals. A first voltage detector means produces a control voltage so that the rectified voltage obtained on the source (or emitter) side of the first rectification transistor is equal to a predetermined reference voltage. The first voltage controlled current source can produce current in accordance with the control voltage and supply the current to the first resistor. Such a power supply circuit is mounted in the contactless electronic device.

Abstract: A permanent magnet synchronous linear motor comprising a field yoke (1) having a plurality of permanent magnets (2) the polarity of which is alternated and which are arranged linearly and an armature (3) facing the array of the permanent magnets (2) through a magnetic air gap, wherein the armature (3) comprises an armature core (4) having main teeth (4b) and slots (4a), an armature winding (5) wound in the slots 4a of the armature core (4), and auxiliary teeth (6) provided at both the ends of the armature core (4). The distance &tgr;p between the centers of the auxiliary teeth (6) and the pitch &tgr;m of the field poles satisfy a relation &tgr;p=(2n−1)×&tgr;m/2 (n is a positive integer) and the length O of the auxiliary teeth (6) is in a relation of O<Hd<Ht where Hd is the length of the auxiliary teeth (6) in the direction orthogonal to the array of permanent magnets and Ht is the length of the main teeth (4b) in the direction orthogonal to the array of permanent magnets.

Abstract: A surface micromachined micromagnetic actuator is described, wherein rotary actuation is accomplished by a member pivotably mounted on the surface of the substrate. Angular motion of the member about the pivot point is imparted by the interaction of a magnetic tab affixed to the member, with flux generated in the gap of an electromagnetic core. Rotary motion is restricted to less than 360 degrees by using an integrally formed hinge between the pivoting member and the pivot point, rather than by a more complex bearing. By virtue of this design, a large range of motion can be achieved without requiring a true bearing to be fabricated in the device. The pivoting member is also constrained in either of two stable positions upon de-energization of the electromagnetic core, by the attachment of a bistable spring between the pivoting member and the substrate.

Abstract: In an electrical drive mechanism, in particular for motor vehicles, having a commutator motor (14) disposed in a housing (10), which commutator motor (14) has a rotor shaft (17) with a commutator (22) non-rotatably supported on it and has a brush holder (30) affixed to the housing (10), and having a bearing (25) disposed in the vicinity of the commutator (22), which bearing has a bearing bush (34) that encloses the rotor shaft (17) with rotary play and a bearing seat (35) that contains the bearing bush (34), in order to achieve a simple embodiment for the bearing (25), a clamping member (37) is formed onto the brush holder (30) of one piece with it, which clamps the bearing bush (34) in a frictionally engaged, axial fashion in the bearing seat (35) formed in the housing (10) (FIG. 1).

Abstract: An electric motor having a cover which is removably mounted to an endshield of the motor and defines an enclosure for electronic components. The cover has an overlapping fit against a wall of the endshield to prevent entry of moisture or contaminants into the enclosure. The cover provides unhindered access to fasteners for connecting the motor to an adjacent part, such as a pump, so that the cover may remain mounted on the endshield while the motor is attached to the pump. Indentations in the cover are positioned at the fasteners, and corresponding recesses are provided in the wall of the endshield.

Abstract: An oil seal arrangement for an electric motor, especially a bypass blower motor assembly has an oil seal protecting a shaft bearing 16 and sealing the shaft aperture between a motor part and a blower part. The oil seal 19 has two lips 25, 28 contacting the shaft 15 at two spaced locations forming a grease chamber 26 therebetween. The volume of the grease chamber 26 is enlarged by a groove 27 in the shaft 15 between the lips 25, 28 of the oil seal 19.

Abstract: A magnetic bearing includes at least one inner bearing part; at least one outer bearing part which surrounds the inner bearing part; at least one permanent magnet and at least one flux guiding element which is positioned axially in relation to a rotation axis, adjacent to the permanent magnet(s), for guiding the magnetic flux of the permanent magnet(s) to one of the two bearing parts, and at least one superconductor on the other of the two bearing parts. The permanent magnet(s) and superconductor interact with each other in such a way that a bearing gap is formed around the rotation axis between the inner bearing part and the outer bearing part. The permanent magnent(s) is/are radially set back towards the bearing gap in relation to the flux guiding element(s) in a radial direction, perpendicular to the rotation axis. Each permanent magnet is held at least one of inwards and outwards by a corresponding radial holding element, at least on the facing towards the bearing gap.

Abstract: Stator cores for a homo-polar magnetic bearing, wherein toothed ends of stator cores around a rotor form N poles and S poles adjacent in the axial direction, and the method of manufacturing them. The stator core 10 is provided with protrusions 11 of adjacent N and S poles extended circumferentially so as to be in contact with or in close proximity to each other, and is composed of U-shaped laminated steel sheets interleaved with an insulating material, of which the center side is open when viewed from the centerline side. In addition, the core is composed of a first yoke, a second yoke and a stem unit that is a magnetic body placed and fixed between the yokes, and at least the stem unit is composed of a magnetic material powder, solidified in resin.

Abstract: A stator device which prevents the formation of varnish accumulations on jumper wires, thereby preventing jumper wire breakage due to temperature variations. A gap is created between the jumper wire and the stud located on the stator body. When varnish is applied to the stud and the jumper wires, excess varnish flows through the gap and pools underneath. Moreover, when there is a significant accumulation of varnish in the gap, the varnish will flow off from the edge of the stator body.