Abstract: A component having at least one adjustable thin-film capacitor is described, which may be manufactured particularly cost-effectively because of its simple design. The component structure is implemented on a substrate and includes at least one first electrically conductive layer and a second electrically conductive layer, which are separated from one another by at least one ferroelectric interlayer. At least one first electrode of the thin-film capacitor is implemented in the first electrically conductive layer, while at least a second electrode of the thin-film capacitor is implemented in the second electrically conductive layer. The capacitor area of the thin-film capacitor is defined exclusively by the overlap region of the first and the second electrodes.

Abstract: A nonvolatile memory cell employing a plurality of dielectric nanoclusters and a method of fabricating the same are disclosed. In one embodiment, the nonvolatile memory cell comprises a semiconductor substrate having a channel region. A control gate is disposed above the channel region. A control gate dielectric layer is disposed between the channel region and the control gate. A plurality of dielectric nanoclusters are disposed between the channel region and the control gate dielectric layer. Each nanocluster may be separated from adjacent nanoclusters by the control gate dielectric layer. A tunnel oxide layer is disposed between the plurality of dielectric nanoclusters and the channel region. Further, a source and a drain are formed in the semiconductor substrate.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.

Abstract: A monolithically integrated vertical DMOS transistor device comprises a semiconductor substrate (11), a gate including a gate semiconductor layer region (27) on top of a gate insulation layer region (25), a source (31), a drain including a buried drain region (13) and a drain contact (21), and a channel region (29) arranged beneath the gate region. The drain comprises a lightly doped, preferably retrograde doped, drain region (23) arranged between the gate and the buried drain region, and the source (31), the channel region (29) and the lightly doped drain region (23) are arranged in a doped well region (17), wherein the lightly doped drain region has a higher doping level than the well region to thereby enhance the high frequency properties of the vertical DMOS transistor device.

Abstract: A power semiconductor module capable of pressure contact, with a base plate and a cover plate, is provided. The power semiconductor module comprises at least one semiconductor device with a first main terminal and with a second main terminal, which is in electrically conducting connection with the base plate, and also at least one spring element, which is arranged between the first main terminal and the cover plate. An electrically conducting connection between the first main terminal and the cover plate is led through an inner region of the spring element.

Abstract: An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.

Abstract: Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300° C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.

Abstract: In a semiconductor device, a plurality of first diffusion regions of a first conductive type are formed on a diffusion layer well of the first conductive type. A plurality of second diffusion regions of a second conductive type are formed on the diffusion layer well of the first conductive type. An impurity concentration of each of the plurality of first and second diffusion regions is desirably higher than that of the diffusion layer well. The plurality of first diffusion regions are connected to a first common node as an anode and the plurality of second diffusion regions are connected to a second common node as a cathode.

Abstract: The present invention provides a device having an N type polysilicon gate and a P type polysilicon gate disposed therein, wherein when both gates are simultaneously etched, they are disposed in such a manner that the area of a non-doped polysilicon gate corresponding to a dummy electrode becomes larger than the total area of the N type and P type doped polysilicon gates, thereby causing non-doped polysilicon to become dominant over doped polysilicon, whereby the polysilicon gates are dry-etched.

Abstract: The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).

Abstract: An electric motor drive system is disclosed which includes a required number of motor driver circuits connected one to each motor armature coil. Fabricated in the form of an integrated circuit, each such motor driver circuit has a parasitic transistor unavoidably created between two neighboring transistors. The parasitic transistor would become conductive when the driver circuit output had a negative potential, adversely affecting the driver circuit operation. An additional transistor is provided in one embodiment of the invention in order to inhibit such action of the parasitic transistor. Becoming conductive when the driver circuit output goes negative, the additional transistor prevents conduction through the parasitic transistor. Another parasitic transistor is intentionally created in another embodiment for the same purpose.

Abstract: Provided is a semiconductor device having a suicide thin film with thermal stability and a method of manufacturing the same. The semiconductor device includes a silicon substrate containing Si a gate oxide film formed on the silicon substrate, a gate electrode containing Si formed on the gate oxide film, a spacer formed on side walls of the gate oxide film and the gate electrode, a LDD region formed in the silicon substrate under the spacer, a source/drain region formed in the silicon substrate, a NiSi thin film on the source/drain region and the gate electrode; and a nitride film formed on the NiSi thin film by surface treating using Ar plasma. The, a semiconductor device having the NiSi thin film has a low sheet resistance and high thermal stability can be obtained.

Abstract: A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.

Abstract: MOSFET gate structures are provided comprising a niobium monoxide gate, overlying a gate dielectric. The niobium monoxide gate may have a low work function suitable for use as an NMOS gate.

Abstract: An element isolation region for electrically isolating an element region where an element is to be formed is formed in a semiconductor substrate. A gate insulating film is formed on the semiconductor substrate in the element region. A gate electrode is formed on the gate insulating film. Source/drain regions are formed to be separated from each other in a surface region of the semiconductor substrate. The source/drain regions sandwich a channel region formed below the gate insulating film. Gate sidewall films are formed on the two side surfaces of the gate electrode. Silicide films are formed on the source/drain regions so as to be separated from the element isolation region.

Abstract: A device for electrical connection between first and second wafers comprises at least first and second contact elements respectively integral to opposite faces of the first and second wafers. The first contact element comprises a salient zone whereas the second contact element is formed by a beam suspended above a cavity formed in the second wafer. The salient zone has a smaller width than the width of the cavity and it can form a stud or a rib. Once the first and second wafers have been assembled, the salient zone and beam come into contact above the cavity and the pressure exerted by the salient zone generates a deformation of the beam, making it flexible.

Abstract: Fast silicon photodiodes with high back surface reflectance in a wavelength range close to the bandgap, and methods of fabrication of such photodiodes. The photodiodes have a patterned oxide or nitride layer on the back surface covered by a metal layer that makes electrical contact with the substrate in a pattern complimentary to the pattern of the oxide or nitride layer. This provided high reflectivity over a large percentage of the back surface, while at the same time providing excellent electrical contact to the back surface.

Abstract: A color filter of an image sensor, an image sensor and a method for manufacturing the image sensor are disclosed, wherein shapes of respective unit color cells closely form various color patterns, such as a red color pattern, a green color pattern and a blue color pattern, within each unit color cell in a stripe type, and various colors such as red, green and blue required for image generation are produced, without interdependence of the respective unit color cells, are normally realized to induce a finished color filter array to smoothly express more colors, so that the resolution of a generated image in an optimal state is achieved.

Abstract: A semiconductor device includes a fuse circuit, which includes a first conductive region and a second conductive region. The first conductive region has a multi-layered structure, and the second conductive region has a less layered structure than the first conductive region.

Abstract: A fusible link formed on a semiconductor substrate. The fusible link comprises a silicide layer overlying a polysilicon layer. The fusible link is programmed to an open state by passing a current therethrough that opens the polysilicon and the silicide layers.

Abstract: In a semiconductor device and a method of fabricating the same, a fuse and a capacitor are formed at a same level on a semiconductor substrate having a fuse area and a capacitor area. The fuse is placed on the fuse area, and a lower plate is placed on the capacitor area. The lower plate is located on a same plane as the fuse. Further, an upper plate is located above the lower plate, and a capping layer is interposed between the lower plate and the upper plate. Therefore, the fuse and the capacitor can be formed at the same time, thereby minimizing photolithography and etch process steps.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductive type, a collector layer formed on the semiconductor substrate and made of a first semiconductor being of the first conductive type and having a higher resistance than that of the semiconductor substrate, an intrinsic base region having a junction surface with the collector layer and made of a second semiconductor of a second conductive type, and an emitter region having a junction surface with the intrinsic base region and made of a third semiconductor of the first conductive type. A periphery of the intrinsic base region is surrounded by an insulating region extending from the collector layer to the semiconductor substrate.

Abstract: An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect adjacent a second interconnect on an interconnect level, spacers formed along adjacent sides of the first and second interconnects, and an air gap formed between the first and second interconnects. The air gap extends above an upper surface of at least one of the first and second interconnects and below a lower surface of at least one of the first and second interconnects, and the distance between the spacers defines the width of the air gap. The air gap is self-aligned to the adjacent sides of the first and second interconnects.

Abstract: An integrated, tuneable capacitance is disclosed that is based on an MOS transistor. In order to improve the linearity characteristics of the tuning characteristic of the varactor, the invention provides for part of the gate region to be doped with the conductance type p, and part to be doped with the conductance type n. Provision is also made for the gate and source/drain regions not to overlap one another, but to be separated from one another on a horizontal plane. This results in a wider variation ratio with a lower series resistance.

Abstract: The present invention is a means for forming substrates for the fabrication of active devices using topography based lithographic manufacturing techniques. A form is used to create a substrate by injection molding, embossing, or by other means of applying a topography to the substrate using a form. This substrate can be plastic, glass or other moldable material or a moldable material layer on another material, but is typically an insulating material that will not participate in the operation of the end devices. The present invention is a means for creating such a form. Furthermore, the present invention is also a means for molding the backside of said substrate, either simultaneously or in multiple steps, such that active devices or portions of a given active device can be formed on both front and back sides of the substrate. The present invention includes means for interconnecting components on both sides of the substrate.

Abstract: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed by forming a conductive layer (42, 64) over a mold encapsulant (35, 62). The conductive layer (42, 64) may be electrically coupled using a wire to the leadframe (10, 52) of the semiconductor package (2, 50). The electrical coupling can be performed by wire bonding two device portions (2, 4, 6, 8) of a leadframe (10) together and then cutting the wire bond (32) by forming a groove (40) in the overlying mold encapsulant (35) to form two wires (33). The conductive layer (42) is then electrically coupled to each of the two wires (33). In another embodiment, a looped wire bond (61) is formed on top of a semiconductor die (57). After mold encapsulation, portions of the mold encapsulant (62) are removed to expose portions of the looped wire bond (61).

Abstract: A packaged integrated circuit for installation on a printed wiring board (PWB) or other type of circuit mounting structure, that allows for the routing of high-speed signals out from high-speed leads on an underside of the packaged integrated circuit. The packaged integrated circuit comprises a die and a package body formed from encapsulant that at least partially encloses the die. A leadframe is also connected to the die and partially enclosed in the package body. Leads extend out from the package body and a subset of these leads are separated by a lead-to-lead pitch. At least two adjacent leads of the leadframe are separated by a space larger than the pitch. An additional lead is also connected to the die and disposed on an underside of the package. The additional lead is connectable to a circuit mounting structure trace passing between the adjacent leads separated by the space larger than the pitch.

Abstract: Methods and apparatus for performing a wire-bonding operation in an integrated circuit are disclosed. The positions of at least one height-sensing pad and at least one bond pad are determined on a top surface of an integrated circuit die. The height-sensing pad is electrically isolated from the die circuitry and the bond pad is electrically connected to the die circuitry. A bonding tool is lowered to the height-sensing pad, and a height coordinate of the height-sensing pad is then determined. Finally, the bond pad is wire-bonded to a leadframe utilizing the height coordinate of the height-sensing pad.

Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.

Abstract: A method for fabricating a chip-scale package includes securing a device substrate that carries at least two adjacent semiconductor devices to a sacrificial substrate. The sacrificial substrate may include conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. The device substrate is then severed along each street and the newly formed peripheral edge of each semiconductor device coated with dielectric material. If the sacrificial substrate includes conductive elements, they may be exposed between adjacent semiconductor devices and subsequently serve as lower sections of contacts. Peripheral sections of contacts are formed on the peripheral edge. Upper sections of the contacts may also be formed over the active surfaces of the semiconductor devices. Once the contacts are formed, the sacrificial substrate is substantially removed from the back sides of the semiconductor devices.

Abstract: A covered chip having an optical element integrated in the cover is provided which includes a chip having a front surface, an optically active circuit area, and bond pads disposed at the front surface. The chip is covered by an at least partially optically translucent or transparent unitary cover that is mounted to the front surface of the chip, and has at least one optical element integrated in the unitary cover. The cover is further aligned with the optically active circuit area and vertically spaced from the optically active circuit area.

Abstract: Stacked interconnect layers each of which includes an interlayer dielectric film and an interconnect line made of copper, and solder resist layer formed as the top layer constitute a multilevel interconnect configuration. The first element, the second element and a circuit element are mounted on the surface of the configuration. The second element bonds to the first element by an adhesion layer. The upper surface of the first element is treated by plasma, and the second element is mounted on the surface.

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.

Abstract: A method for assembling semiconductor devices includes providing a first semiconductor device, applying a predetermined volume of adhesive material to at least a surface of the first semiconductor device, and positioning a second semiconductor device adjacent to the first semiconductor device in superimposed relation thereto. The adhesive material may be applied to a surface of the first semiconductor device prior to positioning the second semiconductor device thereover, or introduced between the first and second semiconductor devices. Upon curing or hardening, the predetermined volume of adhesive material spaces the first and second semiconductor devices a predetermined distance apart from one another. Additional semiconductor devices may also be added to the assembly. The first semiconductor device may be associated with a substrate. Semiconductor device assemblies and packages that are at least partially fabricated in accordance with the method are also disclosed.

Abstract: A method for forming a semiconductor die, comprising forming a trench in a surface of the die; filing the trench with a sacrificial material; patterning the die to form a series of channels extending substantially perpendicularly to the trench; depositing a conductive material in the channels; removing at least a portion of the sacrificial material; and removing portions of the die under the trench so as to separate a portion of the die on one side of the trench from a portion on another side of the trench. The sacrificial material may be patterned so that the channels extend so as to be partially in a portion of the die and partially a portion of the sacrificial material. A series of structures are formed having dies with micro-pins.

Abstract: An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film.

Abstract: A spring contact for establishing electrical contact between a lead element of an IC device and a substrate. The spring contact generally comprises a contact portion and a base portion. The contact portion, which generally comprises a coil-type compression spring, is configured to engage and resiliently bias against a lead element of the IC device. The spring contact is disposed in a mating aperture formed in the substrate. The base portion of the spring contact is configured to secure the spring contact within the mating aperture and to establish electrical contact with the substrate. A plurality of such spring contacts and mating apertures may be arranged on the substrate in an array corresponding to the pin-out of the IC device. A clamping element secures the IC device to the substrate and biases the IC device against the spring contacts.

Abstract: A capped chip is provided which includes a chip and a cap member, the chip having a front surface and a plurality of bond pads exposed at the front surface, the cap member having a bottom surface facing the front surface of the chip and having a top surface opposite the front surface. A plurality of through holes extend from the bottom surface of the cap member to the top surface. The capped chip assembly further includes a plurality of metallic interconnects extending from the bond pads at least partially through the through holes, the metallic interconnects including stud bumps joined to the bond pads, the stud bumps contacting and engaging at least one of (i) the top surface of the cap member surrounding the through holes and (ii) inner surfaces of the through holes.

Abstract: The present invention provides a semiconductor module having: at least one semiconductor device (10); a rigid covering device (14) over the at least one semiconductor device (10) for protecting and dissipating heat from the at least one semiconductor device (10); and a carrier device (17), which has a connection device (19), for receiving the semiconductor device (10) and the covering device (14), the at least one semiconductor device (10) being electrically coupled to the connection device (19) by means of a flexible contact device (11) via the carrier device (17) and being mechanically coupled to the covering device (14) via a contact device (15, 16). The present invention likewise provides a method for producing a semiconductor module.

Abstract: The specification discloses a highly heat dissipative chip module along with its substrate. The chip module contains a highly heat dissipative substrate with several chips installed thereon. The highly heat dissipative substrate is prepared by forming an insulating layer on the surface of a metal compound plate. A copper wired layer is installed on the insulating layer. The copper wired layer can be used to adhere to the chip. The material of the substrate is preferably an aluminum compound material with a high thermal conduction coefficient. It has the advantages of having a light weight and reducing thermal deformations. The insulating layer is also formed using a material with good thermal conductivity, particularly metal oxides with thermal conduction coefficients higher than resins or fibers. The chip can thus homogeneously distribute heat to the whole printed circuit board, dissipating heat into the ambient space.

Abstract: An integrated heat spreader (IHS) having a groove and a cavity formed therein is disclosed. In one embodiment, the groove has an insulating layer formed therein, and a power conduit is mounted in the groove, the power conduit is electrically isolated from the IHS by the insulating layer, and the power conduit conducts a voltage relative to the IHS to deliver power to the cavity. In another embodiment, the IHS is soldered to a semiconductor die and a package substrate. In a further embodiment, the power conduit comprises an edge connector.

Abstract: An embodiment of the present invention is a technique to provide heat extraction for semiconductor devices. At least a thermoelectric film is fabricated onto a bare wafer. The backside of the bare wafer is bonded to an active wafer having at least a device. The bonded bare and active wafers are annealed.

Abstract: Disclosed is a semiconductor device including a SiC substrate and a heat conductor formed in a hole in the SiC substrate and made of a linear structure of carbon elements.

Abstract: An embodiment of the present invention is a technique to stack dies in a die assembly. A plurality of dies are stacked on top of one another in a staggering configuration such that an upper die top surface in a pair of adjacent dies faces downward or upward and is displaced by a first distance with respect to a lower die in the pair. The adjacent dies are attached by an adhesive layer between the adjacent dies.

Abstract: The present invention describes a microsensor with a sensor element (2) and an integrated circuit (1), containing a semiconductor body (11) with an integrated circuit (4), the sensor element (2) being positioned on a main surface (12) of the semiconductor body (11) and there being a eutectic connection (3) formed between the semiconductor body (11) and the sensor element (2).

Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.

Abstract: A circuit chip has an apparatus for an electrically conductive connection of a terminal thereof to an external reference potential. The apparatus has a parallel connection of a bonding wire and a semiconductor area formed in a substrate of the circuit chip. The semiconductor area is doped higher than the substrate of the circuit chip.

Abstract: The present invention includes a first conductor line connected to one end of an optical semiconductor element (20), and supplying an electric signal to this optical semiconductor element (20); a second conductor line connected to the other end of the optical semiconductor element (20), and supplying an electric signal to this optical semiconductor element (20); a first inductance element (21a) connected to the one end of the optical semiconductor element (20), and cutting off the electric signal at a high frequency; and a second inductance element (21b) connected to the other end of the optical semiconductor element (20), and cutting off the electric signal at the high frequency, wherein the first and the second conductor lines constitute differential lines.

Abstract: A ball grid array device includes an array of pads made of an electrically conductive material. The array of pads is positioned on the first major surface. At least one of the array of pads includes a diffusion retarding layer to retard the rate of diffusion of the electrically conductive material from the pad. The ball grid array device also includes a binding layer for binding the diffusion retarding layer to the conductive material of the at least one pad. The ball grid array device also includes a layer of material for receiving solder placed on the diffusion retarding layer.