Abstract: A test key structure includes a substrate, a closed loop, a plurality of spacers, a plurality of first and second doping regions and a plurality of contacts. The closed loop having two conductive lines and two connection portions is located on the substrate. Each connection portion connects to one end of the conductive line and surrounds a contact region. The spacers are disposed at the edge of the closed loop to cover the substrate between the conductive lines. The first doping regions are located in the substrate outside the closed loop and the spacers. The second doping regions are located in the substrate under the spacers. The contacts are electrically connected to the first doping regions within the contact regions. Because the spacers and the conductive lines are incorporated into a test key structure, the influence of spacers upon the entire device can be more accurately determined.

Abstract: The present invention provides an active matrix type display device having a high aperture ratio and a required auxiliary capacitor. A source line and a gate line are overlapped with part of a pixel electrode. This overlapped region functions to be a black matrix. Further, an electrode pattern made of the same material as the pixel electrode is disposed to form the auxiliary capacitor by utilizing the pixel electrode. It allows a required value of auxiliary capacitor to be obtained without dropping the aperture ratio. Also, it allows the electrode pattern to function as a electrically shielding film for suppressing the cross-talk between the source and gate lines and the pixel electrode.

Abstract: In thin film transistors (TFTS) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate. Further, a gate insulating film and a gate electrode are formed. Impurities are introduced by a self-aligning process. Then, the laminate is annealed below the strain point of the substrate to activate the dopant impurities. On the other hand, Neckel or other element is also used as a catalytic element for promoting crystallization of an amorphous silicon film. First, this catalytic element is applied in contact with the surface of the amorphous silicon film. The film is heated at 450 to 650° C. to create crystal nuclei. The film is further heated at a higher temperature to grow the crystal grains. In this way, a crystalline silicon film having improved crystallinity is formed.

Abstract: An imaging area is provided on a surface of a semiconductor substrate, and light-receiving portions and transfer channels are provided in the imaging area. A group of transfer electrodes extends in a direction crossing the transfer channels on the imaging area. A group of transfer signal lines, which are provided for every transfer signal of each phase along the periphery of the imaging area on the semiconductor substrate, is included. A transfer signal line connected to a transfer electrode having a large surface area on the transfer channel, of the group of the transfer electrodes, has an electrical resistance smaller than that of a transfer signal line connected to a transfer electrode having a small surface area on the transfer channel in the group of the transfer electrodes.

Abstract: A thin film transistor panel including: a transparent substrate; scanning lines made of a light blocking electroconductive material to be formed on the transparent substrate; data lines formed on the transparent substrate to be perpendicular to the scanning lines and made of a light blocking electroconductive material; thin film transistors, each provided with a transparent gate electrode connected to one of the scanning lines, a transparent drain electrode connected to one of the data lines, a transparent source electrode and a transparent semiconductor thin film; and transparent pixel electrodes connected to the thin film transistors, wherein each of the pixel electrodes is formed to cover at least a part of the gate electrode of each of the thin film transistors.

Abstract: An object of the present invention is to provide an EL display device having a high operation performance and reliability. The switching TFT 201 formed within a pixel has a multi-gate structure, which is a structure which imposes an importance on reduction of OFF current value. Further, the current control TFT 202 has a channel width wider than that of the switching TFT to make a structure appropriate for flowing electric current. Morever, the LDD region 33 of the current control TFT 202 is formed so as to overlap a portion of the gate electrode 35 to make a structure which imposes importance on prevention of hot carrier injection and reduction of OFF current value.

Abstract: Disclosed herein is a flip-chip type nitride semiconductor light emitting diode. The light emitting diode comprises an n-type nitride semiconductor layer formed on a transparent substrate and having a substantially rectangular upper surface, an n-side electrode which comprises at least one bonding pad adjacent to at least one corner of the upper surface of the n-type nitride semiconductor layer, extended electrodes formed in a band from the bonding pad along four sides of the upper surface of the n-type nitride semiconductor layer and one or more fingers extended in a diagonal direction of the upper surface from the bonding pad and/or the extended electrodes, an active layer and a p-type nitride semiconductor layer sequentially stacked on a region of the n-type nitride semiconductor layer where the n-side electrode is not formed, and a highly reflective ohmic contact layer formed on the p-type nitride semiconductor layer.

Abstract: Provided is a nitride semiconductor light emitting device having enhanced output power and resistance to electrostatic discharge. The light emitting device comprises an n-side contact layer formed on a substrate, a current diffusion layer formed on the n-side contact layer, an active layer formed on the current diffusion layer, and a p-type clad layer formed on the active layer. The current diffusion layer is formed by alternately stacking at least one first InAlGaN layer having a higher electron concentration than that of the n-side contact layer and at least one second InAlGaN layer having a lower electron concentration than that of the n-side contact layer.

Abstract: The present invention provides a wavelength-convertible LED which has first and second surfaces, including first and second conductivity-type cladding layers and an active layer formed between the first and second conductivity-type cladding layers to emit a specific wavelength light. The invention also includes at least a piezoelectric layer on at least one of the first and second surfaces of the semiconductor LED with its thickness variable according to the applied voltage, and a rigid frame made of substantially non-resilient rigid material surrounding the semiconductor LED and the at least one piezoelectric layer such that the increase of the thickness of the piezoelectric layer is applied to the semiconductor LED as pressure. The invention further includes a plurality of terminals on the rigid frame, connected to the first and second conductivity-type cladding layers, and the piezoelectric layer.

Abstract: An optical integrated semiconductor light emitting device with improved light emitting efficiency is provided by preventing leak current from flowing through a high defect region of the substrate. The optical integrated semiconductor light emitting device includes: a substrate, in which in a low defect region made of crystal having a first average dislocation density, one or more high defect regions having a second average dislocation density higher than the first average dislocation density are included; and a Group III-V nitride semiconductor layer which is formed on the substrate, has a plurality of light emitting device structures, and has a groove in the region including the region corresponding to the high defect region (high defect region).

Abstract: A light-emitting element includes a first electrode, a second electrode, and a light-emitting layer disposed between the first electrode and the second electrode, the light-emitting layer including an inorganic semiconductor material, a first material, and a second material, at least one of the first material and the inorganic semiconductor material having a function emit light.

Abstract: An AlGaInP based light emitting diode is provided with a distributed Bragg reflector comprising a combination of an AlGaAs layer and an AlInP layer, each having a film thickness determined by following formulas (1) to (3): t1={?0/(4×n1)}×???(1), t2={?0/(4×n2)}×(2??) ??(2), and 0.5<?<0.9 ??(3) wherein t1 is a film thickness [nm] of the AlGaAs layer, t2 is a film thickness [nm] of the AlInP layer, ?0 is a wavelength [nm] of a light to be reflected, n1 is a refractive index of the AlGaAs layer to the wavelength of the light to be reflected, and n2 is a refractive index of the AlInP layer to the wavelength of the light to be reflected.

Abstract: A light emitting diode includes a substrate tilted toward first and second directions simultaneously, a first cladding layer formed with a semiconductor material of a first conductive type on the substrate, an active layer formed on the first cladding layer, and a second cladding layer formed with a semiconductor material of a second conductive type on the active layer, wherein concavo-convexes are formed on the interfaces of the first cladding layer, the second cladding layer, and the active layer.

Abstract: A light-emitting device includes electron emitters for planarly emitting electrons, collector electrodes disposed to face corresponding one electron emitter, and a phosphor formed near the collector electrodes. During a period when electrons are emitted from the electron emitter, a collector voltage is applied to each of the collector electrodes in the sequence. Electrons are attracted toward a region of the phosphor in the vicinity of the collector electrode to which the collector voltage is applied, and impinge on the region of the phosphor, whereby light is emitted therefrom. The remaining region of the phosphor emit afterglow.

Abstract: A semiconductor device includes a substrate, conductive layer, semiconductor thin films, and individual electrodes. The conductive layer is formed on the substrate and serves as a common electrode. The thin films are bonded on the conductive layer. Each of the plurality of semiconductor thin films includes at least one active region and a contact layer that is in electrical contact with the conductive layer. Each of the individual electrodes is formed on a surface of a corresponding one of the semiconductor thin films in electrical contact with the active region. The thin film may be a single thin film that includes a plurality of active regions formed therein, in which case a different common electrode may be used instead of the common electrode which is in contact with the surface and is electrically isolated from the individual electrodes.

Abstract: A light emitting device in accordance with the present invention includes a light emitting element and a light sensor for detecting the luminous intensity of the light emitted from the light emitting element. The light emitting element includes a lower electrode, a light emitting material layer including at least a light emitting layer, and an upper electrode having light transparency, which are formed on a substrate in the named order. One of the lower electrode and the upper electrode acts as a cathode, and the other acts as an anode. The light sensor is formed on the light emitting element.

Abstract: A semiconductor light emitting device may include a first supporting member having a main surface; a semiconductor light emitting element having a light emitting layer and provided on the main surface of the first supporting member, the light emitting layer being substantially parallel to the main surface of the first supporting member; and a second supporting member provided on the main surface of the first supporting member, the second supporting member having a reflective surface and a front opening, the reflective surface being configured to reflect light emitted from the semiconductor light emitting element. A sealing resin is provided in a space surrounded by the first supporting member and the second supporting member and configured to seal the semiconductor light emitting element.

Abstract: A high efficiency, and possibly highly directional, light emitting diode (LED) with an optimized photonic crystal extractor. The LED is comprised of a substrate, a buffer layer grown on the substrate (if needed), an active layer including emitting species, one or more optical confinement layers that tailor the structure of the guided modes in the LED, and one or more diffraction gratings, wherein the diffraction gratings are two-dimensional photonic crystal extractors. The substrate may be removed and metal layers may be deposited on the buffer layer, photonic crystal and active layer, wherein the metal layers may function as a mirror, an electrical contact, and/or an efficient diffraction grating.

Abstract: In a nitride semiconductor light emitting device, a first conductivity type nitride semiconductor layer is provided on a support base and a second conductivity type nitride semiconductor layer is provided on the support base. An active region is provided between the first conductivity type nitride semiconductor layer and the second conductivity type nitride semiconductor layer. The active region includes an InX1AlY1Ga1-X1-Y1N well layer (1>X1>0 and 1>Y1>0) and an InX2AlY2Ga1-X2-Y2N barrier layer (1>X2>0 and 1>Y2>0). An InX3AlY3Ga1-X3-Y3N buffer layer (1>X3>0 and 1>Y3>0) is provided between the active region and the first conductivity type nitride semiconductor layer. A proportion X1 of indium in the InX1AlY1Ga1-X1-Y1N well layer is smaller than a proportion X3 of indium in the InX3AlY3Ga1-X3-Y3N buffer layer, and a proportion X2 of indium in the InX2AlY2Ga1-X2-Y2N barrier layer is smaller than the proportion X3 of indium in the InX3AlY3Ga1-X3-Y3N buffer layer.

Abstract: A red phosphor composition in combination with a semiconductor light emitting device (e.g., VCSEL, LED, or LD), preferably a GaN based device, that emits light at a bright violet- blue light range, i.e., having a wavelength in the range of 400 nm to 600 nm, which can be further combined with green and blue phosphors. The red phosphor composition in the combination is a vanadate combined with yttrium, gadolinium and/or lanthanum and activated with trivalent Eu3+, Sm3+and Pr3+, or any combination thereof, with or without Tb3+as a co-dopant, has the general formula: Bix,Ln1-xVO4:A where x =0 to 1, Ln is an element selected from the group consisting of Y, La and Gd, and A is an activator selected from Eu3+, Sm3+and Pr3+, or any combination thereof, with or without Tb3+as a co-dopant. Novel red phosphor compositions are provided when x is greater than 0 and less than 1, preferably 0.05 to 0.5.

Abstract: Each pixel includes a region where a lower reflection film is not present. In each pixel, there is a region where a microcavity structure is formed between a counter electrode and a lower reflection film and another region where the microcavity structure is not formed. The regions differentiated in cavity length can differently enhance the peak wavelength so as to improve the viewing angle dependence. Furthermore, in each of R, G, and B light emitting pixels, the area ratio of a region where the microcavity structure is present and another region where the microcavity structure is not present can be adjusted so as to eliminate the differences caused by the microcavity structure.

Abstract: Semiconductor packaging methods, systems and apparatus for semiconductor lasers to achieve high modulation bandwidth. Systems, methods and apparatus for minimizing the inductance of wire bond interconnects and impedance matching in a semiconductor laser package. Systems, methods and apparatus for monitoring a photocurrent in order to provide automatic power control (APC) of a semiconductor laser.

Abstract: A light emitting device is provided. The light emitting device includes a substrate, at least one light emitting chip and a first heat dissipation element. The substrate has a top surface and a bottom surface, and contacts are disposed on the top surface. The light emitting chip disposed on the top surface of the substrate is in contact with the contacts. The light emitting chip includes a light emitting layer, a positive electrode and a negative electrode. The light emitting layer is excited to emit a light by a current applied between the positive electrode and the negative electrode. The first heat dissipation element is disposed at the bottom surface of the substrate for transferring the heat generated by the light emitting chip out of the light emitting device, thus the operation temperature of the light emitting chip can be lowered.

Abstract: The invention relates to a flip-chip nitride semiconductor LED. In the LED, a light emitting structure has first and second conductivity type nitride semiconductor layers and an active layer interposed therebetween. Each of plurality of first and second electrodes has a bonding pad placed adjacent to a top corner of the light emitting structure and at least one electrode finger extended from the bonding pad. The first and second electrodes are connected to the first and second conductivity type nitride semiconductor layers, respectively. Also, bonding pads are arranged alternately along edges of the light emitting structure with different polarity, in a substantially symmetric configuration with respect to the center of the light emitting structure. In addition, each of electrode fingers is extended from a corresponding pad and bent at least once toward the center of the light emitting structure to adjoin the electrode finger having different polarity.

Abstract: A semiconductor light emitting device includes a mold resin having a cup shape portion on an upper surface of the mold resin. One or more holes penetrate through the cup shape portion to outside of the mold resin and/or one or more trenches extend from the cup-shaped portion to outside the mold resin. A first lead is provided in the mold resin and extending from the cup shape portion to outside of the mold resin in a first direction, and a second lead provided in the mold resin and extending from the cup shape portion to outside of the mold resin in a second direction which is opposite to the first direction. A light emitting element is mounted on the first lead in the cup shape portion, and a wire electrically connects the light emitting element and the second lead. A sealing resin is embedded in the one or more holes and the one or more trenches and is configured to seal the light emitting element and the wire.

Abstract: A light emitting device and method for fabricating the device utilizes a layer of photonic crystals with embedded photoluminescent material over a light source. The layer of photonic crystals with the embedded photoluminescent material can be used in different types of light emitting devices, such as lead frame-mounted light emitting diodes (LEDs) and surface mount LEDs with or without reflector cups.

Abstract: There are disclosed a cap or lid for a container which has a light emitter that generates zestful reflected light enabling recognition of a content even in a dark place, a container to which a light emitter is attached to generate zestful reflected light, a base member disposed at a bottom of a container and generating zestful reflected light, and a cap or lid disposed at an upper portion of a can-like container and generating zestful reflected light.

Abstract: A composition for preparing an electron emitter, an electron emitter produced by using the composition, and an electron emission device comprising the electron emitter are provided. The composition for preparing an electron emitter includes carbon-based materials and vehicles, wherein the vehicles comprise a polymer having a vinyl pivalate monomer. The composition for preparing an electron emitter improves a printing and a current-voltage characteristic simultaneously.

Abstract: A compound semiconductor epitaxial substrate having a pseudomorphic high electron mobility field effect transistor structure including an InGaAs layer as a strained channel layer and an AlGaAs layer containing n type impurities as a front side electron-donating layer, wherein said substrate contains an InGaP layer in an orderly state on the front side of the above described InGaAs layer as the strained channel layer.

Abstract: A semiconductor device with high function, multifunction and high added value. The semiconductor device includes a PLL circuit that is provided over a substrate and outputs a signal with a correct frequency. By providing such a PLL circuit over the substrate, a semiconductor device with high function, multifunction and high added value can be achieved.

Abstract: A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used.

Abstract: The present invention is an object to provide a high-performance vertical field effect transistor having a microminiaturized structure in which the distance between the gate and the channel is made short not through a microfabrication process, having a large gate capacitance, and so elaborated that the gate can control the channel current with a low voltage, and a method for simply and efficiently manufacturing such a field effect transistor not through a complex process such as a microfabrication process.

Abstract: A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a first epitaxial layer is formed so as to fill up portions, cut out at the time of forming the side wall spacer, of the semiconductor substrate, and the extension regions are formed on the first epitaxial layer from a second epitaxial layer of a conduction type opposite to that of the first epitaxial layer.

Abstract: An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.

Abstract: Pixels have a photodiode 1, a transfer gate electrode 2 for transferring charges accumulated in the photodiode 1, a floating diffusion section 3 for accumulating the charge transferred by the transfer gate electrode 2, an amplification transistor 15 in which a gate electrode is connected to the floating diffusion section 3, and a reset transistor 14 for resetting a potential of the floating diffusion section 5. A gate length of the amplification transistor 15 is shorter than a gate length of a transistor, among transistors comprising the peripheral circuitry region, whose gate insulating film thickness is a same as a gate insulating film thickness of the amplification transistor 15 and which has a minimum gate length.

Abstract: An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.

Abstract: The present invention provides a semiconductor device comprising: a semiconductor substrate having a DRAM portion and a Logic portion; a first transistor in said DRAM portion; a second transistor in said Logic portion; a first insulating layer covering said DRAM portion and said Logic portion; a first contact plug formed in said first insulating layer in electrically contact with said first transistor in said DRAM portion; a first bit line for said DRAM portion formed on said first insulating layer in electrically contact with said first contact plug; a nitride film formed in contact with said first insulating layer to cover said DRAM portion and said Logic portion, wherein said first bit line locating between said first insulating layer and said nitride film.

Abstract: A method and system for providing a magnetic element is disclosed. The method and system include providing a pinned layer, a magnetic current confined layer, and a free layer. The pinned layer is ferromagnetic and has a first pinned layer magnetization. The magnetic current confined layer has at least one channel in an insulating matrix and resides between the pinned layer and the free layer. The channel(s) are ferromagnetic, conductive, and extend through the insulating matrix between the free layer and the pinned layer. The size(s) of the channel(s) are sufficiently small that charge carriers can give rise to ballistic magnetoresistance in the magnetic current confined layer. The free layer is ferromagnetic and has a free layer magnetization. Preferably, the method and system also include providing a second pinned layer and a nonmagnetic spacer layer between the second pinned layer and the free layer.

Abstract: The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.

Abstract: The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the periphery of the use of sacrificial spacers. The present teachings further describe a method of forming at least one capacitor structure on a substrate. For example, the method comprises forming at least one recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the at least one recess, and defining at least one lower electrode within the at least one recess formed in the substrate by removing at least a portion of the first conductive layer. The method further comprises diffusing an etchant through the at least one lower electrode so as to remove at least a portion of the substrate to thereby at least partially isolate the at least one lower electrode.

Abstract: The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that have read/write speeds and charge retention times that are different from the other memory arrays of the system. Each of the memory cells of each array has a tunnel layer under an embedded trap layer. Each array has memory cells with a different tunnel layer thickness to change the read/write speeds and charge retention times for that array.

Abstract: A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.

Abstract: The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that have read/write speeds and charge retention times that are different from the other memory arrays of the system. Each of the memory cells of each array has a tunnel layer under an embedded trap layer. Each array has memory cells with a different tunnel layer thickness to change the read/write speeds and charge retention times for that array.

Abstract: The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the injector layer. A polysilicon control gate formed over the high dielectric constant layer. The cell can be formed in a planar architecture or a two element, split channel, three-dimensional device. The planar cell is formed with the high dielectric constant layer and the control gate being formed over and substantially around three sides of the embedded trap layer. The split channel device has a source line in the substrate under each trench and a bit line on either side of the trench.

Abstract: A memory structure in a semiconductor substrate essentially comprises a first conductive line, two conductive blocks, two first dielectric spacers, a first dielectric layer, and a second conductive line. The first conductive line, e.g., a polysilicon line, is formed above the semiconductor substrate, and the two conductive blocks composed of polysilicon, for example, are formed at the two sides of the first conductive line and insulated from the first conductive line with the two first dielectric spacers. The first dielectric layer, such as an oxide/nitride/oxide (ONO) layer, is formed on the two second conductive blocks and above the first conductive line, and the second conductive line is formed on the first dielectric layer and is substantially perpendicular to the two doping regions. Accordingly, the stack of the conductive block, the first dielectric layer, and the second conductive line form a floating gate structure which can store charges.

Abstract: When an insulating material deposited in a device isolation trench is etched, an etching process is performed to make a surface height of the insulating film lower than that of the device forming region. As a result, when a polysilicon film for a floating gate electrode is formed on a first tunnel film, the polysilicon film is curved downwardly on the insulating film (oxide film). Therefore, no peak shape is formed at ends of the floating gate electrode. By forming a floating gate electrode without the peak shape, the present invention can improve data retention characteristics of a semiconductor memory device.

Abstract: In one embodiment, a memory device includes a gate structure comprising a metal nitride material in a charge storing layer on a semiconductor substrate. The gate structure is disposed between a first dopant region and a second dopant region formed on the semiconductor substrate. The metal nitride material is structured to function as a trap site for trapping a charge.

Abstract: A nitride semiconductor light-emitting device includes a substrate and a nitride semiconductor layer including a light-emitting layer stacked on the substrate, wherein a normal line relative to a lateral face of the nitride semiconductor layer is not perpendicular to a normal line relative to a principal plane of the substrate. A method for the production of a nitride semiconductor light-emitting device that includes a substrate and a nitride semiconductor layer including a light-emitting layer stacked on the substrate includes the steps of covering a first surface of the nitride semiconductor layer with a mask provided with a prescribed pattern, removing the nitride semiconductor layer in regions to be divided into component devices till the substrate, subjecting the nitride semiconductor layer to wet-etching treatment and dividing the nitride semiconductor layer into the component devices.

Abstract: A method for manufacturing a charge storage stack including a bottom dielectric layer, a charge trapping structure on the bottom dielectric layer, and a top dielectric layer, each comprising silicon oxynitride, are formed using reactant gases that comprise hydrogen, where the hydrogen comprises at least 90 percent deuterium isotope. The bottom dielectric layer, charge trapping structure, and top dielectric layer each have respective relative concentrations of oxygen and nitrogen. The relative concentration of nitrogen in the charge trapping structure is high enough for the material to act as a charge trapping structure with an energy gap that is lower than the energy gaps in the bottom dielectric layer and the top dielectric layer. The presence of oxygen in the charge trapping structure reduces the number of available dangling bonding sites, and thereby reduces the number of hydrogen inclusions in the structure.

Abstract: In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.