Abstract: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

Abstract: Circuit methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This current is then used to generate rising and falling edges of a waveform. The clock signal is used to determine timing of transitions in the waveform. A bandgap or similar reference voltage is used to determine the peak voltage. This waveform is then gained using an amplifier circuit, and the output of the amplifier circuit is used as a programming voltage waveform for an EE-PROM. One embodiment further uses non-overlapping clocks to drive a charge pump that is used to generate a supply voltage for the amplifier circuit that far exceeds the available on-chip supply voltages.

Abstract: A semiconductor memory device includes memory cells, write bit lines, read bit lines, latch circuits, a n-channel MOS transistor, and voltage setting circuits. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. The first MOS transistors are connected commonly to the write bit lines and read bit lines. The latch circuits are provided for the write bit lines and hold write data for the memory cells. The n-channel MOS transistor transfer “1” data to the latch circuits in a data latch operation. The voltage setting circuits supply a potential corresponding to “0” data to the write bit lines in a read operation. In a data latch operation, the latch circuit corresponding to the write bit line connected to the memory cell into which “0” data is to be written latches the potential supplied to the write bit lines in a read operation.

Abstract: A reference voltage generator circuit for nonvolatile memory devices is disclosed. The circuit has at least one sense amplifier bias reference voltage generator (SABRVG) for generating a reference voltage at a predetermined reference point that is coupled to a start-up bias reference voltage generator (SBRVG). It also includes a monitor reference voltage generator (MRVG) for generating a monitor reference voltage, and a comparison module for comparing the monitor reference voltage with the reference voltage to produce a start-up control signal, wherein the SBRVG enhances a changing speed of the reference voltage during a reading cycle of the nonvolatile memory and when the monitor reference and the reference voltages are matched, the start-up control signal stops the SBRVG from operating, thereby having the SABRVG maintain the reference voltage.

Abstract: An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell programmed by the external device as a comparative reference to program additional reference cells.

Abstract: An error correction code is applied and an erasing procedure is passed as accomplished, if a maximum number of single bit failures in compliance with a criterion of the error correction code is not exceeded.

Abstract: A semiconductor device is provided which includes a memory part that includes memory cells having different threshold values; a read circuit that reads data from a memory cell to be programmed with write data that is input; and a detection circuit that compares the write data with the data read from the memory cell to thus detect a pattern in which programming of data causes erasing. The pattern that causes erasing during the programming is processed as an inhibited operation. If the inhibited operation is identified, the process is forcedly terminated without initiating the programming by the write command. This makes it possible to avoid erasing resulting from the programming.

Abstract: A non-volatile memory device includes a word line voltage generator circuit for generating a word line voltage to be supplied to a selected row in response to step control signals, and a program controller for generating the step control signals so that an increment of the word line voltage is varied according to the mode of operation, namely, a test mode or normal mode. Thus test time can be shortened.

Abstract: Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage.

Abstract: A charge trapping memory device in which a field induced inversion layer is used to replace the source and drain implants. The memory cell are adapted to store two bits, one on the left side and one on the right side of the charge trapping structure. A positive threshold voltage erase state is induced using negative gate voltage Fowler Nordheim FN tunneling which establishes a charge balance condition at a positive voltage. A low current, source side, hot electron injection programming method is used.

Abstract: A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.

Abstract: A system and method for communicating information to and from memory deices. In one embodiment, the invention includes a memory system having a memory device having at least one extraneous device pin, a memory controller configured to control the memory device and a signal path extending between the memory device and the controller that includes the at least one extraneous device pin, the signal path being operable to a transfer a selected memory system characteristic between the controller and the memory device.

Abstract: Method and apparatus for use with internal array voltage generators in semiconductor memory devices are disclosed. In one described embodiment, an overdriving level control circuit is used to generate an overdriving control signal for an internal array voltage generator driver, just prior to a sensing operation. The overdriving level control circuit uses a cell modeling circuit to estimate, just prior to the sensing operation, a current requirement for the sensing operation, and an amplifier to generate the overdriving control signal in response to the estimated current requirement. Such a design allows the amount of overdrive signal to track process, voltage, and temperature changes, for example, to provide an accurate overdrive that allows the internal array voltage to remain stable. Other embodiments are described and claimed.

Abstract: In order to decrease the circuit scale of a power supply circuit and the area occupied by the power supply circuit over a semiconductor substrate, the power supply circuit, which supplies a supply voltage to respective parts of a memory circuit, includes a word driver power supply (first power supply circuit), a sense amplifier power supply (second power supply circuit), a bit line precharge power supply, a cell plate power supply, a substrate bias power supply, and a word line bias power supply. The word driver power supply supplies a word driver with a voltage generated by directly increasing an external supply voltage, whereas the other power supplies (e.g., the sense amplifier power supply) supply a sense amplifier, etc., with a voltage generated by decreasing the external supply voltage.

Abstract: A memory device that has an internal memory array provides timing signals to control the output timing of one or more redundant memory blocks that substitute for defective memory blocks in the internal memory array. In one embodiment, the internal memory array includes a pipelined output stage, and the timing signals ensure that the data is output from the memory devices in the order memory access requests are issued, even when the latency of the redundant memory blocks is less than the latency of the main memory array by up to two clock periods. In one embodiment, a FIFO memory queues the output data of the redundant memory blocks waiting to be output.

Abstract: An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control signal and starts a test run independent of the control clock. Driving with the first control signal, selection transistors in a memory bank that can be selected by a memory bank address are turned off. Afterward, bit lines in the selected memory bank are interconnected and driven with a predetermined precharge potential. After a precharge time has elapsed, one of the word lines is selected by an applied word line address and the selection transistors in the selected memory bank connected to the selected word line are turned on. Precharge times are set and tested independently of the clock period of the control clock.

Abstract: A semiconductor memory device comprises a central control circuit for receiving an operation command from an external chipset, generating an active signal for executing the operation command, and generating a precharge signal after a predetermined time, a row path control circuit for controlling a bank according to the active signal or the precharge signal of the central control circuit, and a precharge time control circuit, which is enabled according to the active signal to output an oscillation signal having a predetermined frequency, divides the oscillation signal based on a setting time from when an active operation is performed until when a precharge operation is performed, and then outputs a precharge time control signal, thereby controlling generation of the precharge signal of the central control circuit.

Abstract: A semiconductor memory device comprising: a memory array including a plurality of memory cells; a plurality of word lines corresponding to the respective memory cells; a pair of local bit lines corresponding to the memory array; a pair of global bit lines corresponding to the pair of local bit lines; a precharge circuit including an output terminal being connected to the pair of local bit lines; a local write amplifier circuit including a data input terminal being connected to the pair of global bit lines and an output terminal being connected to the pair of local bit lines; and a control signal line being connected to an input terminal of the precharge circuit and to a control input terminal of the local write amplifier circuit, wherein the local write amplifier circuit is deactivated by the control signal line when the precharge circuit is activated, and the precharge circuit is deactivated by the control signal line when the local write amplifier circuit is activated.

Abstract: A system for read path acceleration has a first strobe reset circuit coupled to a first local amplifier. A second strobe reset circuit is coupled to a second local amplifier. A main amplifier is coupled to an output of the first local amplifier and an output of the second local amplifier.

Abstract: A bit line sense amplifier control circuit includes a driving signal generating unit adapted and configured to generate first through third driving signals in response to a bit line sense amplifier enable signal and an overdrive enable signal for setting an overdrive period, and to disable a first driving signal which is enabled for an overdrive period in response to a refresh signal which is enabled at a refresh mode, and a bit line sense amplifier control signal generating unit adapted and configured to generate first and second bit line sense amplifier control signals in response to the first through third driving signals. As a result, an overdrive pulse is not generated at a refresh mode to remove an overdriving period, thereby reducing current consumption at a refresh mode.

Abstract: A single sensing transistor is selectively diode connected to a sense line that is coupled to reference cells and data cells to store a reference current or leakage currents on the gate of the sensing transistor by opening the switch to disconnect the diode connection of the sensing transistor. Other sensing systems may use two transistors and may stores leakage current. A sensing system with capacitance auto-zeroing is included. The sensing system may include a dynamic differential current differential amplifier.

Abstract: A memory (100) includes first (116) and second (118) sense amplifiers, a first logic gate (120), a first three-state driver (130), and a latch (180). The first sense amplifier (116) is coupled to a first local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the first local data line. The second sense amplifier (118) is coupled to a second local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the second local data line. The first three-state driver (130) has a data input terminal coupled to the output terminal of the first logic gate (120), a control input terminal for receiving a first select signal, and an output terminal coupled to a global data line. The latch (180) has an input/output terminal coupled to the global data line (170).

Abstract: A semiconductor storage device having a memory cell array in which a plurality of memory cells is provided at intersections of a plurality of bit lines and a plurality of word lines and executing refreshing for holding data, including: memory cells for pairing provided on the memory cell array, for compensating for errors of each memory cell; a control circuit for checking a data holding ability of memory cell under test in a predetermined period after power-on; a storage circuit for storing information which specifies the memory cells under test for which it is determined that the data holding ability is low in the checking of the control circuit; and a selecting-line activating circuit for activating circuit for activating a selecting line for pairing corresponding to the memory cells for pairing based on a result of comparing a specific address to be input with the information stored in the storage circuit.

Abstract: A random access memory device has a memory array, and a refresh rate generator circuit. The memory array has a plurality of memory cells that are configured to hold a charge. The memory array has an active mode and a standby mode. The refresh rate generator circuit is coupled to the memory array and is configured to generate a refresh signal having a rate. The refresh signal is used to periodically refresh the memory cells. The memory device detects when the memory array changes from its standby mode to its active mode and then increases the rate of the refresh signal when the memory array changes from its standby mode to its active mode.

Abstract: A fuse circuit has an actual fuse circuit block and a fuse monitor circuit. The actual fuse circuit block stores fuse information; on the other hand, the fuse monitor circuit monitors whether a supply voltage has reached an information capturable voltage at which the fuse information from the actual fuse circuit block can be correctly captured.

Abstract: Semiconductor memory devices. A semiconductor memory device includes a booster circuit generating a predetermined power voltage exceeding an external power voltage, a global power line supplying the predetermined power voltage, and a plurality of memory blocks. Each memory block has a local power line, a plurality of functional circuits coupled to the local power lines and a voltage control device coupled between the global power line and the local power line. The voltage control device outputs the predetermined power voltage or a first voltage to the functional circuits through the local power line in a first period and a second period respectively, according to a select signal, wherein the first voltage exceeds the external power voltage but is lower than the predetermined power voltage.

Abstract: There is provided memory control device and memory control method, which can prevent wiring complication by many crossing wirings, and reduction of yield and quality. When a memory control device CC1 selects a memory chip CC2, an internal circuit of a select circuit 27 is changed by a switch signal SWS2. In this case, the changeover is made so that a select signal S2 outputted from an internal circuit 40 is inputted to a predetermined memory terminal of the memory chip CC2. The select signal S2 is inputted to the corresponding predetermined memory terminal of the memory chip CC2, and thereby, the memory chip CC2 is activated, and set to a state capable of inputting and outputting control signals 21 to 25. The control signals 21 to 25 are assigned to control terminals P21 to P27 after being hanged by the select circuit 27 in signal sequence corresponding to terminal array sequence of memory terminals 21a to 27a of the memory chip CC2.

Abstract: An arrangement of buffer in a memory unit including a plurality of memory banks may store information in rows that span the memory banks. Moreover, a processor may be adapted to (i) establish a plurality of buffers to be associated with the memory unit, wherein the size of each buffer is less than the width of a memory bank, and (ii) arrange for a selected buffer to begin in a memory bank other than a memory bank in which a previously selected buffer begins.

Abstract: A memory having a bit line, a word line crossing the bit line, a memory cell electrically connected to the bit line and to the word line, a column decoder and a selector including a clocked inverter having a plurality of transistors electrically connected in series between a first power source and a second power source is provided. An input node of the clocked inverter is connected to the bit line, an output node of the clocked inverter is electrically connected to a data line, the plurality of transistors comprise a P-type transistor and a N-type transistor, a gate electrode of the P-type transistor and a gate electrode of the N-type transistor are electrically connected to the column decoder, and a sense amplifier is not interposed between the bit line and the input node of the clocked inverter.

Abstract: First-in first-out (FIFO) memory devices are configured to support all four of the following FIFO memory modes: (1) DDR write with DDR read, (2) DDR write with SDR read, (3) SDR write with DDR read and (4) SDR write with SDR read. These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.

Abstract: A method of reading data in and outputting data from a memory structure includes a buffer. In the present method, first read operation is undertaken to read a first set of data in the memory structure and provide data of the first set of data to the buffer, using an output clock. A first output operation is undertaken providing data read in the first read operation from the buffer, and a second read operation is undertaken to read a second set of data in the memory structure and provide data of the second set of data to the buffer, using the output clock. A second output operation is undertaken providing data read in the second read operation from the buffer.

Abstract: A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate a plurality of output signals. During an initialization period, an initialization circuit sets the delay of the delay line to a minimum delay value and then compares this delay value to the period of the input clock signal. Based on this comparison, the initialization circuit programs the programmable divider and adjusts the number of delayed clock signals combined to generate the output signals. More specifically, as the frequency of the reference clock signal increases, the divider is programmed to divide by a greater number, and a larger number of delay clock signals are combined to generate the output signals.

Abstract: A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is configured to receive a clock signal and a first control signal, and output a plurality of data in response to the clock signal after the first control signal is asserted. After the first control signal is asserted, an internal signal which responds to the clock signal transits N times (N is a positive integer and greater than or equal to 2), then output of the data is started. At least one of the data is output at the transition after the output begins.

Abstract: A seismic data acquisition system includes a connector housing and a mating electrical circuitry module. A single interface couples electrical circuitry housed in the electrical circuitry module to one or more signal data carriers that are consolidated at a single location in the connector housing. Preferably, the connector housing and electrical circuitry module each have a substantially contaminant-free interior regardless of whether these two parts are mated. An alternate connector housing has two plug casings, each of which are provided with a plug. A complementary alternate electrical circuitry module includes two receptacles complementary to the plugs and an interior space for holding the electrical circuitry. A locking pin disposed within the plug casing selectively engages the electrical circuitry module.

Abstract: Acoustic telemetry devices and methods that provide directional detection. In one embodiment, a disclosed acoustic telemetry device comprises at least two acoustic sensors and an electronics module. A first of the acoustic sensors detects a communication signal that propagates along a tubing string in a first direction. A second of the acoustic sensors is configured to detect the communication signal before the first acoustic sensor. The electronics module combines the detection signals from the acoustic sensors to obtain a combined signal that substantially excludes signals propagating in a direction opposite to the communication signal. Such signal suppression may significantly enhance the communication signal's signal-to-noise ratio, thereby increasing channel capacity. The acoustic telemetry device may be configured to support logging while drilling and/or full-duplex communication.

Abstract: Provided is a sonar transmitter in which the structure is simplified and the power loss is decreased. A sonar transmitter comprises: a load unit having a transformer constituted with a primary wiring and a secondary wiring, and a wave transmitter to which the secondary voltage generated in the secondary wiring is applied; a control unit for outputting a PWM signal which originally has no offset voltage; and a transmission circuit unit which amplifies the PWM signal outputted from the control unit and applies it to the primary wiring as the primary voltage. The control unit comprises a memory circuit formed by ROM or RAM which stores a transmission signal waveform and a control circuit formed by a microcomputer or DSP, for example. With the present invention, a conventional feedback circuit, an adder and the like become unnecessary by outputting the PWM which originally contains no offset voltage.

Abstract: This date mechanism comprises a calendar mobile (1), a driving mobile (3) an instantaneous-jump cam (7), a finger (9b) kinematically connected to this cam (7) in order to drive the calendar mobile (1). The driving finger (9b) is borne by a release member (9) which is mounted pivotably about two axes (3a, 7a), one (3a) of which is that of the driving mobile (3), this release member (9) having an opening (9a) configured to allow an angular displacement about the second of these two axes (7a), whereby the driving finger (9b) can be released from the toothing (1a) of the calendar ring while the calendar is corrected. A return spring (8) tends to rotate the driving finger (9b) about the second pivot axis (7a) in order to bring it to butt against an edge of the opening (9b), a position in which the driving finger is engaged with the toothing of the calendar ring (1).

Abstract: An electronic timepiece includes a radio wave receiving antenna (8) for receiving radio waves, electromagnetic motors (61, 65) for driving a time display part, a battery (5), and a body case for receiving the antenna (8), electromagnetic motors (61, 65), and the battery (5). The antenna (8), electromagnetic motors (61, 65), and the battery (5) do not overlap as viewed in the viewing direction of a time display part, that is, they do not overlap two-dimensionally. By such a structure, the electronic timepiece can be thin and flat.

Abstract: The invention presents an optical element with which an optical head can be configured, in which there is little deterioration of the correctional effect when the objective lens shifts, as well as an optical head and an optical recording/reproducing apparatus using such an optical element. The invention also presents a novel optical recording/reproducing apparatus and optical recording/reproducing method. The optical element, includes a first voltage application electrode 13, a first opposing electrode 17 arranged in opposition to the first voltage application electrode 13, and a first phase changing layer 15 arranged between the first voltage application electrode 13 and the first opposing electrode 17. By changing a voltage between the first voltage application electrode 13 and the first opposing electrode 17, a phase that converts plane waves into spherical waves is imparted on light that is incident on the first phase changing layer 15.

Abstract: An optical disc unit 2001 comprises: reflective surface detection means 1010 for detecting a reflective surface; focus control means (1202, 1003, 1009, 1008, 1003, 1012, 1005 and 1204) for performing focus control to a reflective surface so that the distance between the focal point of an optical beam applied to an optical disc 2100 and the reflective surface is within a predetermined error limit; shift means 1007 for shifting the focal point of the optical beam in a direction perpendicular to the optical disc; and control means 1006 for controlling the focus control means and the shift means.

Abstract: A tracking control system for outputting a tracking control signal for an optical pickup including a plurality of light detecting sections each of which converts reflected light of a light beam applied to an optical disk into an electric signal, and outputs the signal, includes: a balance correction amount calculating section for obtaining, as a balance correction amount, a value by which a differential phase tracking error signal based on each output of the light detecting sections should be shifted in accordance with a direct-current component of a differential amplitude tracking error signal based on each output of the light detecting sections such that a direct-current component of the differential phase tracking error signal approaches a given reference potential; a balance changing section for shifting the differential phase tracking error signal in accordance with the balance correction amount; and a tracking control section for generating the tracking control signal in accordance with the differential

Abstract: The present invention relates to an optical device which includes a first laser diode, a beam splitter, a first objective lens, a photo-detector, a second laser diode, a wedged plate beam splitter, a second objective lens and a collimator. The present invention deploys two independent transmitting paths. The retrieving paths share the beam splitter and the photo-detector commonly at the returning route.

Abstract: Servo error signal circuitry apparatus and methods are described. The difference between two bottom envelope signals SEbtm and SFbtm is calculated by a subtracter (40) to generate a difference signal (SEbtm?SFbtm). The difference signal (SEbtm?SFbtm) is input as an alignment signal (AL) to an equalizer (42) and as a basic tracking error signal to the positive input terminal of a second subtracter (52). On the other hand, the difference between two top envelope signals SEtop and SFtop is calculated by a third subtracter (48) to generate a difference signal (SEtop?SFtop). The signal K(SEtop?SFtop) obtained by multiplying a coefficient K with the difference signal using a coefficient multiplier (50) is input to the negative input terminal of the second subtracter (52). The difference signal {(SEbtm?SFbtm)?K(SEtop?SFtop)} output from the second subtracter (52) is used as an offset corrected tracking error signal.

Abstract: An optical disc player discriminates an attribution of tracks recorded onto a disc inserted in the player, and normally reproduces MP3 tracks recorded onto discs inserted into a plurality of disc drivers using an MP3 decoder. Also, according to a method of reproducing an optical disc, the optical disc player discriminates a kind of an inserted disc as an audio file disc, an MP3 file disc, or a general data file disc and normally performs a reproducing operation for the files or music recorded onto the inserted disc.

Abstract: An optical disk device for estimating optimum recording power for high speed recording at an outer part of an optical disk, with high accuracy, even when an OPC for high speed recording at the outer part cannot be performed. The optical disk device includes a first optimum recording power calculation part for performing test recording at a first speed lower than the maximum recording speed of a test area by using recording parameters of a required recording speed to calculate first optimum recording power, and a second optimum recording power calculation part for performing test recording at a second speed to calculate second optimum recording power. The first speed is different from the second speed. The optical disk device further includes an estimation part for estimating optimum recording power based on the first optimum recording power and the second optimum recording power.

Abstract: A method and an apparatus are provided, which enable a user's standby time to be shortened or utilized effectively in the course of recording/reproduction of information with respect to an optical disk. Information recorded on a disk is reproduced preferentially, and after counting for a predetermined period of time, recording learning is conducted. Alternatively, management information is reproduced preferentially over recording learning, and recording learning is conducted while a user is confirming this information. Alternatively, the possibility of recording on a disk is identified, and reproduction preference or recording learning preference processing is conducted based the possibility. Alternatively, a rotation speed of a disk is controlled to be variable or constant, based on the possibility of recording.

Abstract: It is an object of the present invention to provide an apparatus for discriminating an optical recording medium which can reliably discriminate the kind of an optical recording medium even in the case where the optical recording medium to be discriminated is warped and formed with periodical undulation in the circumferential direction thereof.

Abstract: A method of adjusting a condition for at least one of a recording operation and a reproducing operation includes the following steps. At least first and second asymmetry values is found. The first asymmetry value is defined based on a first signal combination selected from at least three signals different in cycle from each other. The second asymmetry value is defined based on a second signal combination selected from the at least three signals. The second signal combination is different from the first signal combination. The condition is set with reference to the at least first and second asymmetry values.

Abstract: An adaptive writing method of a high-density optical recording apparatus and a circuit thereof. The circuit includes a discriminator for discriminating a magnitude of a present mark of input NRZI data and magnitudes of leading and/or trailing spaces of the input NRZI data, a generator for controlling the waveform of a write pulse in accordance with the magnitude of the present mark of the input NRZI data and the magnitudes of the leading and/or trailing spaces of the input NRZI data to generate an adaptive write pulse, and a driver for driving a light source by converting the adaptive write pulse into a current signal in accordance with driving power levels for respective channels of the adaptive write pulse. The widths of the first and/or last pulses of the write pulse waveform are varied in accordance with the magnitude of the present mark of input NRZI data and the magnitude of the leading and/or trailing spaces, thereby minimizing jitter to enhance system reliability and performance.