Abstract: Disclosed is a method for fabricating a MOS transistor. The present method includes forming a buffer layer pattern including nitrogen on the semiconductor substrate; forming a gate insulating layer and a gate electrode on the exposed substrate surface; forming a LDD region in the substrate under the buffer pattern; forming a spacer on a top surface of the buffer pattern and sidewalls of the gate electrode; and forming a source/drain region in the substrate under the buffer pattern.

Abstract: A semiconductor sensor is disclosed that includes a semiconductor substrate, a sensing portion provided on the semiconductor substrate, and a pad in electrical communication with the sensing portion and provided on the semiconductor substrate. The semiconductor sensor also includes a bonding wire in electrical communication with the pad. Furthermore, the semiconductor sensor includes a cover member with a covering portion disposed over the semiconductor substrate for covering the sensing portion such that the covering portion is separated at a distance from the sensing portion. The cover member further includes a coupling portion provided on the semiconductor substrate at an area including the pad and for enabling electrical connection of the pad with the bonding wire therethrough.

Abstract: An array of conductive lines for MRAM circuits wherein at least one set of mutually parallel conductive traces is tilted with respect to being perpendicular with a corresponding set of mutually parallel conductive traces wherein individual conductive traces within the sets intersect adjacent individual MRAM cells and wherein the tilting of the at least one set of conductive traces acts to induce both a vertical and horizontal component of a magnetic field such that the net vector addition of magnetic fields induced by the sets of conductive traces is greater than the untilted or perpendicular configuration so as to induce a greater net magnetic field to effect more reliable switching of the underlying MRAM cells. The tilted array also enables reducing the current supplied by the conductive traces while maintaining a comparable net magnetic field to the untilted configuration.

Abstract: It is made possible to provide a highly reliable magnetoresistive effect element and a magnetic memory that operate with low power consumption and current writing and without element destruction. The magnetoresistive effect element includes a first magnetization pinned layer comprising at least one magnetic layer and in which a magnetization direction is pinned, a magnetization free layer in which a magnetization direction is changeable, a tunnel barrier layer provided between the first magnetization pinned layer and the magnetization free layer, a non-magnetic metal layer provided on a first region in an opposite surface of the magnetization free layer from the tunnel barrier layer, a dielectric layer provided on a second region other than the first region in the opposite surface of the magnetization free layer from the tunnel barrier layer; and a second magnetization pinned layer provided to cover opposite surfaces of the non-magnetic metal layer and the dielectric layer from the magnetization free layer.

Abstract: It is possible to perform a writing operation with low power consumption and a low current, and enhance reliability without causing element breakdown. There are provided a first magnetization-pinned layer including at least one magnetic film in which a magnetization direction is pinned; a second magnetization-pinned layer including at least one magnetic film in which a magnetization direction is pinned; a magnetic recording layer formed between the first magnetization-pinned layer and the second magnetization-pinned layer and including at least one magnetic film in which a magnetization direction is changeable by injecting spin-polarized electrons; a tunnel barrier layer formed between the first magnetization-pinned layer and the magnetic recording layer; and a nonmagnetic intermediate layer formed between the magnetic recording layer and the second magnetization-pinned layer.

Abstract: An image sensor comprising a transfer gate electrode having a uniform impurity doping distribution is provided. The image sensor further comprises a semiconductor substrate comprising a pixel area, wherein the pixel area comprises an active region and the transfer gate electrode is disposed on the active region. A method of fabricating the image sensor is also provided. The method comprises preparing a semiconductor substrate, forming a polysilicon layer on the semiconductor substrate, doping the polysilicon layer with impurity ions, and patterning the polysilicon layer.

Abstract: An optoelectronic component has a lens that is formed in the surface of an encapsulant surrounding a semiconductor diode element. With respect to emitters, the lens reduces internal reflection and reduces dispersion to increase overall efficiency. With respect to detectors, the lens focuses photons on the active area of the detector, increasing detector sensitivity, which allows a detector having a reduced size and reduced cost for a given application. The lens portion of the encapsulant is generally non-protruding from the surrounding portions of the encapsulant reducing contact surface pressure caused by the optoelectronic component. This non-protruding lens is particularly useful in pulse oximetry sensor applications. The lens is advantageously formed with a contoured-tip ejector pin incorporated into the encapsulant transfer mold, and the lens shape facilitates mold release.

Abstract: A phase change memory with adjustable resistance ratio is disclosed, which includes a phase change layer and an interfacial layer formed to be in contact with each other, and at least two electrodes in contact with the phase change layer and the interfacial layer respectively. The contact sections between the two electrodes and the phase change layer and the interfacial layer define a contact area respectively, wherein, the area defined by the contact section between the electrode and the phase change layer is larger than the area defined by the contact section between the electrode and the interfacial layer.

Abstract: An SiC Schottky diode die or a Si Schottky diode die is mounted with its epitaxial anode surface connected to the best heat sink surface in the device package. This produces a substantial increase in the surge current capability of the device.

Abstract: Devices including multiple undercut profiles in a single material are disclosed. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.

Abstract: A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate, a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner, and a second via extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner.

Abstract: An isolation insulating film is formed so that an active region of a first access transistor and a substrate contact region can be integrated with each other in a plan view. A dummy gate electrode is formed on the semiconductor substrate between the active region of the first access transistor and the substrate contact region. The dummy gate electrode is electrically connected to a P-type impurity region of the substrate contact region.

Abstract: There is disclosed a semiconductor device comprising a plurality of inter-level dielectric films which are stacked and provided in plural layers above a substrate, at least one first conductor which is provided in at least one inter-level dielectric film of the stacked inter-level dielectric films, and a plurality of second conductors which are provided in the inter-level dielectric film in which the first conductor is provided and which are connected to the lower surface of the first conductor and which are extended along the downward direction from the first conductor and further extended along a first direction and a second direction perpendicular to the first direction in such a manner as to be spaced apart from each other to form a lattice shape.

Abstract: After formation of a gate insulating film for a high voltage transistor on the entire surface, when removing the gate insulating film existing within a low voltage region, etching is not finished upon expose of an active region, but overetching is performed until the surface of an element isolation insulating film becomes lower by, for example, about 15 nm than the surface of the active region within the low voltage region. Then, a high-temperature rapid thermal hydrogen treatment is performed on the active region within the low voltage region. As a result of this, a natural oxide film is removed from the surface of the active region within the low voltage region, so that the flatness is increased and its corners are rounded.

Abstract: A fuse box of a semiconductor device is provided. More specifically, provided is a device of forming a uniformly residual oxide film by rearranging fuse boxes in consideration of an etching ratio depending on plasma density of the semiconductor device to prevent a fuse attack. During a repair etching process to open a fuse box in a chip, an etching loading effect is evenly reflected depending on pattern density of the fuse box so that the residual oxide film is regularly distributed in each fuse of all fuse boxes regardless of the size of an open region. As a result, the fuse attack resulting from an excessive etching process on the oxide film on a small fuse is prevented in fuse blowing to improve yield of FTA (Fixed To Attempt) yield.

Abstract: A plurality of pulses each having relatively low energy are consecutively applied to a subject fuse to cause breakdown, wherein the total energy of pulses is set in light of a prescribed breakdown threshold, which is calculated in advance. The subject fuse has a pair of terminals and an interconnection portion that is narrowly constricted in the middle so as to realize fuse breakdown with ease. A pulse generator generates pulses, which are repeatedly applied to the subject fuse by way of a transistor; then, it stops generating pulses upon detection of fuse breakdown. Side wall spacers are formed on side walls of fuses, which are processed in a tapered shape so as to reduce thermal stress applied to coating insulating films. In addition, pulse energy is appropriately determined so as to cause electro-migration in the subject fuse, which is thus increased in resistance without causing instantaneous meltdown or evaporation.

Abstract: An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.

Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

Abstract: The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's diameters in the lower region is larger than in the upper region; a first electrode; a dielectric layer on top of the first electrode; a conductive layer on top of the electric layer, the conductive layer forming a second electrode of the capacitor; and a plug forming a closed cavity inside the lower region.

Abstract: Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-are lithographic patterning. An opening is aligned above the dielectric pad and etched through an isolation oxide layer to an extrinsic base layer. The opening is equal to or greater in size than the dielectric pad. Another smaller opening is etched through the extrinsic base layer to the dielectric pad. A multi-step etching process is used to selectively remove the extrinsic base layer from the surfaces of the dielectric pad and then to selectively remove the dielectric pad. An emitter is then formed in the resulting trench. The resulting transistor structure has a distance between the edge of the lower section of the emitter and the edge of the extrinsic base that is minimized, thereby, reducing resistance.

Abstract: Improved radio frequency gain in a silicon-based bipolar transistor may be provided by adoption of a common-base configuration, preferably together with excess doping of the base to provide extremely low base resistances boosting performance over similar common-emitter designs.

Abstract: A thin film of organic resin material (17), such as novolac, is used as an etch mask and openings (32) are formed in the mask in a predetermined pattern to allow processing in selected areas defined by the openings. The openings (32) are formed by applying a pattern of droplets (76) of caustic etchant, such as sodium hydroxide (NaOH) or potassium hydroxide (KOH) in the areas where the openings are to be formed. The droplets (76) are applied using a inkjet printer (90) which is scanned over the surface of the organic resin as the droplets are applied. The droplets (76) are of a size which defines the dimension of the openings (32) and allows the organic resin (17) under the droplet (76) to be completely removed. After the etchant has etched through the organic resin to expose an underlying surface (12), the etchant is washed from the organic resin and the openings (32).

Abstract: A method of forming an integrated circuit including forming a dielectric film is described. The forming of the dielectric film includes: providing a substrate, providing a carbon doped oxide film on the substrate, and treating the carbon doped oxide film with an electron beam. The carbon doped oxide film can be provided by chemical vapor deposition.

Abstract: An integrated circuit including an assembly of functional blocks and an interconnection network formed of at least N levels of conductive tracks separated by conductive via levels, the interconnection network including a power supply network comprising a first assembly of substantially parallel rails placed at the N-th track level, and a second assembly of substantially parallel rails placed at the (N?1)-th track level under the first rail assembly, the rails of the first assembly being non-parallel to those of the second assembly, the power supply network further including, for each functional block, a third assembly of power supply rails placed at the (N—2)-th track level above the elements of the considered block, and in which the rails of the second assembly form an acute angle smaller than 80° with the rails of each third rail assembly.

Abstract: The invention discloses a switching element for a pixel electrode of display device and methods for fabricating the same. A gate is formed on a substrate. A high-k dielectric layer is formed on the gate. The high-k dielectric layer comprises HfO2, HfNO, HfSiO, HfSiNO, or HfAlO. A semiconductor layer is formed on the high-k dielectric layer. A source and a drain are formed on a portion of the semiconductor layer.

Abstract: A leadframe includes at least one lead extending from an integrated circuit and terminating at a connector pin. The lead includes multiple predefined bases to connect to one or more components external to the integrated circuit.

Abstract: Packages for an optical integrated circuit die and a method for making such packages are disclosed. The package includes a die, a die pad, a plurality of lead fingers, and an encapsulating dielectric material. The downward second pad surface of the die pad bearing an integrated circuit is encapsulated by a bottom encapsulating dielectric material. The top encapsulating dielectric material provides the function for protecting the leadframe from severe environment. The top encapsulating dielectric material can be neglected if there is no threat on the integrated circuit die and the leadframe. Multiple of lead fingers are mounted on the printed circuit board. A portion of the printed circuit board is removed in order to provide an optical path for the light beam transmitted from a light source through the transparent bottom encapsulating dielectric material into the integrated circuit die. The method of making a package includes forming a leadframe including a die pad and a plurality of lead fingers.

Abstract: A resin-encapsulated semiconductor device includes: a semiconductor chip on a surface of which a group of electrodes is disposed; a plurality of inner leads arranged along a periphery of the semiconductor chip; connecting members for connecting the electrodes of the semiconductor chip with the respective inner leads, an encapsulating resin for encapsulating surfaces of the semiconductor chip and the connecting members; and external electrodes exposed from the encapsulating resin. Each of the inner leads extends across the periphery of the semiconductor chip from an internal side to an external side of the periphery, and includes a protruded portion provided on a surface of the inner lead on an external side relative to the periphery of the semiconductor chip, the protruded portion being protruded in a thickness direction.

Abstract: A semiconductor chip package may have through holes extending from a chip contact surface of a film type die attaching material to a second surface of a die pad. A resin encapsulant may extend into the through holes to directly contact portions of a semiconductor chip that are superposed over the through holes. The through holes may be formed using a stamping method.

Abstract: A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon gate, and source/drain regions for the transistor are formed using the sacrificial carbon sidewall spacers to define the source/drain regions. The sacrificial carbon sidewall spacers are replaced with non-carbon sidewall spacers, and the sacrificial carbon gate is replaced with a desired metal gate material to provide the desired metal gate material on the gate dielectric. Various embodiments form source/drain extensions after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier is used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers.

Abstract: A parallel chip embedded printed circuit board and manufacturing method thereof are disclosed. With a method of manufacturing a parallel chip embedded printed circuit board, comprising: (a) forming a parallel chip by connecting in parallel a plurality of unit chips having electrodes or electrically connected members formed on the upper and lower surfaces thereof, using at least one conductive member; (b) joining an electrode on one side of the parallel chip to a first board; and (c) joining an electrode on the other side of the parallel chip to a second board, chips may be embedded in a printed circuit board at a low cost, as a plurality of unit chips can be embedded at once, and a mechanical drill or router can be used instead of a laser drill in perforating the cavity or via holes.

Abstract: A multi-layered substrate (42) is disclosed. The substrate (42) includes at least a receptor layer (46) and a bonding layer (64). One or more holes (54) extend completely through the receptor layer (46). A shaped block (10) may be disposed in a given hole (54). When the substrate (42) is compressed, the upper surface (14) of the block (10) and the upper surface (50) of the receptor layer (46) are disposed in coplanar relation, and bonding material (68) from the bonding layer (64) flows into the hole (54) to fill any gap between the receptor layer (46) and the block (10) within the hole (54).

Abstract: A memory array module mounting structure is disclosed to include a main board, which has circuit contacts arranged thereon, a plurality of connectors installed in the main board and electrically connected to the circuit contacts of the main board, and a plurality of memory chips respectively detachably inserted into the connectors and kept electrically connected to the circuit contacts of the main board. Each memory chip can be removed from the respective connector for repair or replacement without reflow or desolder process when damaged.

Abstract: A semiconductor device includes: a plurality of stacked semiconductor chips including a first semiconductor chip having a side surface, and a second semiconductor chip stacked on the first semiconductor chip; and a sealing resin placed between the plurality of semiconductor chips, at least one edge of the first semiconductor chip is positioned on an inner side of the second semiconductor chip, and the sealing resin placed between the first semiconductor chip and the second semiconductor chip is extended over the side surface of the first semiconductor chip.

Abstract: Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.

Abstract: A method for fabricating a chip-embedded interposer may comprise forming at least one cavity on a silicon substrate, forming a plurality of through vias penetrating the silicon substrate, providing an integrated circuit chip having a plurality of I/O pads, and forming rerouting conductors connected to the I/O pads and the through vias. A stack structure having different kinds of chips may be incorporated at wafer level using the described interposer.

Abstract: A semiconductor integrated circuit device includes a functional circuit block, a power supply for supplying power to the functional circuit block, a power supply interruption circuit disposed between the functional circuit block and the power supply and including a plurality of switching elements, and a power supply interruption control circuit for individually driving the switching elements. The functional circuit block is formed by integrating functional circuits, such as a logic circuit and a memory circuit. The functional circuits are formed with power supply terminals, respectively, and the power supply terminals are electrically connected through power supply interconnects to the switching elements. The power supply interconnects have the same length.

Abstract: The invention provides a semiconductor multi-chip package including a substrate, a first semiconductor chip mounted on the substrate and a second semiconductor chip disposed directly above the first semiconductor chip. The package further includes a spacer disposed between the substrate and the second semiconductor chip to maintain a vertical interval between the first and second semiconductor chips and electrically connect the second semiconductor chip to the substrate. The invention minimizes noise generated through a bonding wire connecting the substrate with the chip to ensure stable operation of the chip, and reduces the size of the substrate and the number of mounted components, thereby achieving miniaturization of the package.

Abstract: Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. A substrate has a surface, wherein the surface has an opening therein. A stiffener has a surface coupled to the surface of the substrate. An area of the surface of the stiffener can be greater than, equal to, or less than an area of the surface of the substrate. A thermal connector is coupled to the surface of the stiffener through the opening. A surface of the thermal connector is capable of attachment to a printed circuit board (PCB) when the BGA package is mounted to the PCB. The thermal connector can have a height such that the thermal connector extends into a cavity formed in a surface of the PCB when the BGA package is mounted to the PCB. Alternatively, the stiffener and thermal connector may be combined into a single piece stiffener, wherein the stiffener has a protruding portion.

Abstract: The stack package may have a structure in which unit packages may be inserted into slots of a receiving substrate. The unit package may have a plurality of connecting pads. The receiving substrate may have substrate pads, which may be electrically connected to the connecting pads of the unit packages inserted in the slots by mechanical contact. The slots may be provided at regular vertical intervals so that the unit packages may be stacked in the vertical direction. A semiconductor module may include stack packages installed on at least one surface of a module substrate.

Abstract: A nonuniform portion of a film thickness on a substrate owing to effects of a support column, a substrate mounting portion, and the like which constitute a substrate holder is eliminated, and uniformity of the film thickness of the substrate is enhanced. A substrate processing apparatus houses plural wafers (substrates) held on a boat (substrate holder) in a processing chamber, supplying processing gas to the heated processing chamber, thereby performing film-forming processing for the wafers. The boat includes: at least three support columns 15 provided substantially vertically; plural wafer support portions 16 (substrate mounting portions) which are provided at multi-stages on the support columns and mount the plural wafers substantially horizontally at a predetermined interval; and plural ring-like plates 13 arranged on the support columns 15, and provided substantially horizontally at a predetermined interval with respect to the wafers supported on the wafer support portions 16.

Abstract: In a high frequency package device includes a bottom plate, a side wall, a lid, a dielectric plate, an input line, an output line and a projection. The side wall is provided on the bottom plate, and configured to surround a space above the bottom plate. The lid is configured to close an opening formed by the side wall. The input line and the output line are configured to penetrate through the side wall. The projection is provided at a part of the inner surface of the lid to make the distance to the bottom plate short.

Abstract: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The substrate is configured over a second buffer layer such that the second buffer layer substantially encompasses the whole substrate to decrease damage to the substrate when the side of the substrate is collided with an external object.

Abstract: Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

Abstract: Disclosed is a device which comprises a substrate, a plurality of signal output terminal electrodes provided on the substrate, a plurality of signal input terminal electrodes provided on the substrate, and a display driver IC having input terminals thereof connected to the signal input terminal electrodes and output terminals thereof connected to the signal output terminal electrodes. A plurality of output terminals (first, third, fifth, . . . (i+1)th, and (n?1)th) are included on a first side of the display driver IC facing the signal input terminal electrodes. A second side on an opposite side of the first side faces the signal input terminal electrodes. Input terminals 22 are included in at least one segment of the second side, and output terminals (second, fourth, sixth, ith, jth, (j+2)th, (n?2)th, and nth) are included in at least one portion of the remaining segment of the second side.

Abstract: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate and including a plurality of first portions and a second portion disposed between two of the first portions adjacent to each other; and an interconnect electrically connected to the electrode and extending over one of the first portions of the resin protrusion. A lower portion of a side surface of the second portion includes a portion which extends in a direction intersecting a direction in which the resin protrusion extends.

Abstract: A stack type semiconductor package uses rigid, C-shaped guide substrates that hold semiconductor packages stacked in place and which also provide signal pathways between the stacked semiconductors and contact surfaces of the package. The C-shaped guide eliminate short circuits caused by prior art lead wires.

Abstract: An interconnect architecture with improved reliability. An interconnect with rounded top corners is inlaid in a dielectric layer. A filler borders the interconnect along the corners of the interconnect.

Abstract: There is provided a metal line of a semiconductor device and a method for forming the metal line. In the method, a first metal line can be formed above a semiconductor substrate. An etch barrier layer can be formed on the first metal line. An interlayer insulating layer can be formed on the etch barrier layer and selectively removed to form a via hole and a trench. A portion of the interlayer insulating layer located in the via hole can be etched to expose the first metal line, and a plasma surface treatment can be performed on the interlayer insulating layer in which the via hole and the trench are formed and on the exposed first metal line by using an NH3 plasma treatment. A metal diffusion barrier layer and a second metal line can then be formed in the trench and the via hole.

Abstract: A semiconductor device that includes a pad over a multilevel interconnect formed by stacking an interconnect layer and an interlayer insulating film, the semiconductor device including a protective member that is formed in a continuous manner under outer circumference of the pad and has moisture resistance, the protective member surrounding the interlayer insulating film under the pad.