Abstract: The present invention provides a back illuminated photodetector having a sufficiently small package as well as being capable of suppressing the scattering of to-be-detected light. A back illuminated photodiode 1 comprises an N-type semiconductor substrate 10, a P+-type doped semiconductor region 11, a recessed portion 12, and a coating layer 13. In the surface layer on the upper surface S1 side of the N-type semiconductor substrate 10 is formed the P+-type doped semiconductor region 11. In the rear surface S2 of the N-type semiconductor substrate 10 and in an area opposite the P+-type doped semiconductor region 11 is formed the recessed portion 12 that functions as an incident part for to-be-detected light. Also, on the rear surface S2 is provided the coating layer 13 for transmitting to-be-detected light that is made incident into the recessed portion 12.

Abstract: A gate driver circuit includes a driving section and a wiring section. The wiring section receives a plurality of signals from an external device. The driving section includes a plurality of stages providing a plurality of gate lines with a gate signal. The wiring section includes first and second signal wirings. The first signal wiring is disposed adjacent to a first side of the driving section, where the first side receives the signals from the wiring section. The second signal wiring is disposed adjacent to a portion that is disposed at an outer side of the driving section and the first signal wiring. Therefore, a signal applied to the first signal wiring is prevented from being delayed by the second signal wiring. Furthermore, a distortion of signal applied to the gate driver and a maloperation of the gate driver are prevented.

Abstract: A light emitting diode (LED) package for high temperature operation which includes a printed wire board and a heat sink. The LED package may include a formed heat sink layer, which may be thermally coupled to an external heat sink. The printed wire board may include apertures that correspond to the heat sink such that the heat sink is integrated with the printed wire board layer. The LED package may include castellations for mounting the package on a secondary component such as a printed wire board. The LED package may further comprise an isolator disposed between a base metal layer and one or more LED die. Optionally, the LED die may be mounted directly on a base metal layer. The LED package may include a PWB assembly having a stepped cavity, in which one or more LED die are disposed. The LED package is advantageously laminated together using a pre-punched pre-preg material or a pressure sensitive adhesive.

Abstract: In one aspect, an image sensor is provided which includes an array of unit active pixels. Each of the unit active pixels comprises a first active area including a plurality of photoelectric conversion regions, and a second active area separated from the first active area. The first active areas are arranged in rows and columns so as to define row and column extending spacings there between, and the second active areas are located at respective intersections of the row and column extending spacings defined between the first active areas.

Abstract: One aspect of this disclosure relates to an integrated circuit structure. An integrated circuit structure embodiment includes a substrate, a gate dielectric over the substrate, a carbon structure having a predetermined thickness in contact with and over the gate dielectric, and a layer of desired gate material for a transistor in contact with and over the carbon structure. The layer of desired gate material includes a predetermined thickness corresponding to the predetermined thickness of the carbon structure to support a metal substitution process to replace the carbon structure with the desired gate material. Other aspects and embodiments are provided herein.

Abstract: A non-volatile memory device is proposed. The memory device includes a plurality of blocks of memory cells, each block having a common biasing node for all the memory cells of the block, biasing means for providing a biasing voltage, and selection means for selectively applying the biasing voltage to the biasing node of a selected block, for each block the selection means including first switching means and second switching means connected in series, the first switching means being connected with the biasing node and the second switching means being connected with the biasing means, wherein the second switching means of all the blocks are connected in parallel, the selection means including means for closing the first switching means of the selected block and the second switching means of all the blocks, and for opening the second switching means of each unselected block.

Abstract: An image sensor includes a first conductivity type substrate with a trench formed in a predetermined portion thereof, a second conductivity type impurity region formed in the first conductivity type substrate below the trench and being a part of a photodiode, a second conductivity type first epitaxial layer filling the trench and being a part of the photodiode, and a first conductivity type second epitaxial layer formed over the second conductivity type first epitaxial layer.

Abstract: An imager with pixels having a resonant-cavity photodiode. The resonant cavity photodiode increases absorption of light having long wavelengths. A trench is formed for the photodiode and reflective film is grown on the bottom of the trench. The reflective film reflects light that is not initially absorbed back to the active region of the photodiode.

Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.

Abstract: The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate.

Abstract: A semiconductor device having a semiconductor substrate, a SRAM area formed in the semiconductor substrate, the SRAM area having first transistors, the first transistor having a metallic compound film formed on each of a source and a drain regions of the first transistor, and a logic circuit area formed in the semiconductor substrate, the logic circuit area having a second transistor, the second transistor having a metallic compound film on each of a source and a drain regions of the second transistor. The thickness of the metallic compound film of the second transistor is thicker than thickness of the metallic compound film of the first transistor.

Abstract: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitori

Abstract: The field-effect transistor includes: a ferromagnetic layer, having a film thickness of 50 nm or less, which is made of a Ba—Mn oxide showing ferromagnetism at 0° C. or higher; a dielectric layer made of a dielectric material or a ferroelectric material, and the ferromagnetic layer and the dielectric layer are bonded to each other. Thus, it is possible to control the magnetism, the electricity transport property, and/or the magnetic resistivity effect at 0° C. or higher.

Abstract: A semiconductor memory device including a memory cell having a first ferromagnetic film, a tunnel barrier film formed on the first ferromagnetic film, and a second ferromagnetic film formed on the tunnel barrier film, the tunnel barrier film having a larger film thickness in its in-surface edge portion than in its in-surface central portion, a side wall insulating film formed so as to surround at least sides of the second ferromagnetic film, and an interlayer insulating film formed so as to cover the memory cell and the side wall insulating film.

Abstract: A semiconductor device has an N type diffusion layer between an insulating layer formed on the surface of a trench and an N type semiconductor region. An N type impurity is diffused in the N type diffusion layer so as to have a concentration gradient in a direction that connects a source electrode and a drain electrode. By having the N type diffusion layer, the semiconductor device can have a favorable depletion layer produced therein when a reverse-direction voltage is applied, and can reduce leak current. Thus, the semiconductor device has a favorable voltage withstand characteristic.

Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Abstract: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer.

Abstract: Some embodiments of the present invention include capacitors with controlled equivalent series resistance.

Abstract: A semiconductor memory device includes a semiconductor substrate including a semiconductor layer on a first insulation film; a memory cell including a source and a drain formed in the semiconductor layer, and a floating body region provided between the source and the drain, the memory cell storing data according to an amount of charges accumulated in the floating body region; a second insulation film provided on the floating body region of the memory cell; a word line provided on the second insulation film; a bit line connected to the drain; a source line connected to the source; and a plate electrode electrically insulated from the floating body region by the first insulation film, wherein in at least a part of a period for writing data to the memory cell, a potential of the plate electrode is changed to reduce an absolute value of a threshold voltage of the memory cell.

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160).

Abstract: A non-volatile memory device includes a channel region defined between a source region and a drain region, a charge storage film disposed on the channel region to store a charge, and a tunnel insulating film interposed between the channel region and the charge storage film to tunnel the charge, the tunnel insulating film having a quantum confinement film.

Abstract: An integrated circuit is provided including at least one memory cell. Such memory cell, in turn, includes a transistor and a capacitor. The transistor includes a source, a drain, and a gate. Further, the capacitor includes a well and a gate. The gate of the transistor remains in communication with the gate of the capacitor. In various other embodiments, the memory cell includes a transistor and a capacitor including wells of differing types (e.g. P-type, N-type). In such embodiments, the well of the transistor abuts the well of the capacitor. In still further embodiments, for a more compact design, a diffusion region of the transistor is situated less than 2.5 ?m from a diffusion region of the capacitor.

Abstract: A semiconductor process and apparatus includes forming a floating gate stack structure (1) and a low voltage transistor gate stack structure (2) over a substrate (11) by including a shallow extension implant region (51, 52) that is aligned with the floating gate (13). By using a spacer etch process after a deep dielectric isolation (DDI) oxidation step is used to isolate the floating gate (13), a sub-zero spacer (31, 32) may be formed for the shallow extension implant (41, 42) which is subsequently diffused to overlap with the floating gate (13).

Abstract: A nonvolatile memory cell comprising a switchable resistor memory element and a thin-film three-terminal switching device, preferably a MOSFET, in series. The switchable resistor memory element has the property of having at least two stable resistance states, for example a high-resistance state and a low-resistance state. It is switched between the two states, and its resistance state (and thus the data state of the cell) is sensed by providing appropriate current through the three-terminal switching device. Preferred embodiments of the present invention include a highly dense monolithic three dimensional memory array in which multiple memory levels of such memory cells are formed above a single substrate such as a monocrystalline silicon wafer.

Abstract: Non-volatile memory devices include a floating gate having a lower portion and a pair of walls extending upward from opposite edges of the lower portion to define a void. An overlap area between adjacent floating gates is decreased by a side area of the void defined by the lower portion and the walls, so that a parasitic electrostatic capacitance can be reduced.

Abstract: A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

Abstract: A semiconductor device includes a semiconductor layer having a plurality of element regions in its surface area, which are delimited by at least one element isolation trench, a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween and each including a first charge-storage layer having a first width which is equal to that of each of the element regions and a second charge-storage layer stacked on the first charge-storage layer and having a second width which is smaller than the first width, and a plurality of control gate electrodes provided on the floating gate electrodes with a second gate insulation films interposed therebetween. The device further includes an element isolating insulation film buried into the element isolation trench. The top surface of the element isolating insulation film is located higher than that of the first charge-storage layer.

Abstract: A gate structure adapted for use in a SONOS device unit cell is disclosed. The gate structure comprises a charge trap insulator and a single electrode. The charge trap insulator comprises a multilayer structure comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. The single electrode is formed on the charge trap insulator, comprises a P-type impurity receptive semiconductor material, and is doped with P-type impurities.

Abstract: The present invention relates to a GaN-based semiconductor light emitting diode and a method of manufacturing the same. The GaN-based semiconductor light emitting diode includes: a substrate; a n-type nitride semiconductor layer formed on the substrate; an active layer formed on a predetermined portion of the n-type nitride semiconductor layer; a p-type nitride semiconductor layer formed on the active layer; a transparent conductive layer formed on the p-type nitride semiconductor layer; an insulating layer formed on an upper center portion of the transparent conductive layer, the insulating layer having a contact hole defining a p-type contact region; a p-electrode formed on the insulating layer and electrically connected to the transparent conductive layer through the contact hole; and an n-electrode formed on the n-type nitride semiconductor layer where no active layer is formed.

Abstract: The present memory device includes first and second electrodes, a passive layer between the first and second electrodes and an active layer between the first and second electrodes, the active layer being of a material containing randomly oriented pores which are interconnected to form passages through the active layer.

Abstract: In a charge-trapping device having an array of memory cells, which are controlled by word lines buried in trenches within a substrate, further trenches are formed parallel to said word lines within said substrate. These subdivide diffusion regions adjacent to the word lines into each a first diffusion region adjacent to a first trench of a first charge-trapping memory cell and a second diffusion region adjacent to a first trench of a second charge-trapping memory cell. The depth of the further trench is sufficient to impede hot charge carrier exchange between neighboring memory cells. For this purpose the further trenches are filled with dielectric material, e.g., an oxide. The depth of the further trenches may be, e.g., half of that of the word line trench, and the width may, e.g., amount to 15-20 nm.

Abstract: A diode has a semiconductor body (1), which has a front side (11) and a rear side (12) opposite the front side (11) in a vertical direction (z) of the semiconductor (1), and in which a heavily n-doped zone (5), a weakly n-doped zone (4), a weakly p-doped zone (3) and a heavily p-doped zone (2) are arranged successively in the vertical direction (z) proceeding from the rear side (12) toward the front side (11). In order to produce the weakly p-doped zone (3) of such a diode, aluminum may be introduced into the semiconductor body (1) proceeding from the front side (11). Optionally, the diode may have a field stop zone (9). Such a field stop zone (9) may be produced by rear-side indiffusion of sulfur and/or selenium into the semiconductor body (1).

Abstract: A first electrode layer, which comes into contact with a source region, and a second electrode layer, which comes into contact with a body (back gate) region, are provided. The first and second electrode layers are insulated from each other and are extended in a direction different from an extending direction of a trench. It is possible to individually apply potentials to the first and second electrode layers, and to perform control for preventing a reverse current caused by a parasitic diode. Therefore, a bidirectional switching element can be realized by use of one MOSFET.

Abstract: A first main electrode is provided on one surface thereof. On the other surface thereof, a second semiconductor layer of the first conduction type and a third semiconductor layer of the second conduction type are arranged alternately along the surface. A fourth semiconductor layer of the second conduction type and a fifth semiconductor layer of the first conduction type are stacked on the surfaces of the second and third semiconductor layers. The semiconductor device further comprises a control electrode formed in a trench with an insulator interposed therebetween. The trench passes through the fourth and fifth semiconductor layers and reaches the second semiconductor layer. A sixth semiconductor layer of the first conduction type is diffused from the bottom of the trench. A second main electrode is connected to the fourth and fifth semiconductor layers.

Abstract: A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.

Abstract: The LDMOS transistor (99) of the invention is provided with a stepped shield structure (50) and/or with a first (25) and a second (26) drain extension region having a higher dopant concentration than the second drain extension region, and being covered by the shield.

Abstract: A semiconductor component has a semiconductor body (100) having a basic doping and a first and second side, an inner region (103) arranged between the first and second sides, and an edge region (104) adjacent to the inner region in a lateral direction, at least one active component zone (12) which is arranged in the inner region (103) in the region of the first side (101) and is doped complementarily to the basic doping, and a channel stop zone (20), which is arranged in the edge region (104) in the region of the first side (101), is of the same conduction type as the basic doping and is doped more heavily than the basic doping, the doping concentration in the channel stop zone (20) decreasing continuously at least in sections in a lateral direction in the direction of the active component zone (12) at least over a distance (d1) of 10 ?m.

Abstract: An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.

Abstract: According to the present invention, there is provided a semiconductor device manufacturing method comprising: depositing a semiconductor layer and mask material in order over a semiconductor substrate on an insulating film; patterning the semiconductor layer and mask material to form a semiconductor layer in a predetermined region; removing a surface portion of the insulating film by a predetermined depth by performing etching by using the mask material as a mask; forming gate insulating films on at least a pair of opposing side surfaces of the semiconductor layer; depositing silicon on the insulating film, gate insulating films, and mask material; patterning the silicon into a gate pattern to form, on the gate insulating films, a silicon film having the gate pattern on predetermined regions of the pair of opposing side surfaces of the semiconductor layer; ion-implanting a predetermined impurity into the semiconductor layer by using the silicon film as a mask, thereby forming a source region and drain region

Abstract: The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).

Abstract: The present invention provides a method of manufacturing a single-electron transistor device (100). The method includes forming a thinned region (110) in a silicon substrate (105), the thinned region (110) offset by a non-selected region (115). The method also includes forming at least one quantum island (145) from the thinned region (110) by subjecting the thinned region (110) to an annealing process. The non-selected region (115) is aligned with the quantum island (145) and tunnel junctions (147) are formed between the quantum island (145) and the non-selected region (115). The present invention also includes a single-electron device (200), and a method of manufacturing an integrated circuit (300) that includes a single-electron device (305).

Abstract: An electrostatic discharge (ESD) structure having increased voltage withstand at an output terminal of an integrated circuit device has a thin gate oxide layer metal oxide semiconductor (MOS) device coupled in series with a thicker gate oxide layer MOS device. The thin gate oxide layer MOS device may be controlled by a low voltage control circuit of the integrated circuit. The thicker gate oxide layer MOS device may be coupled to an output of the integrated circuit device or a bipolar transistor may be coupled between the output of the integrated circuit device and the thicker gate oxide layer MOS device. The thin gate oxide layer and thicker gate oxide layer MOS devices may be coupled in series.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A semiconductor device including: a semiconductor layer including an active region and an isolation region provided around the active region; an element formed in the active region; an interlayer dielectric formed above the semiconductor layer; and an electrode pad formed above the interlayer dielectric and having a rectangular planar shape having a short side and a long side, the electrode pad at least partially covering the element when viewed from a top side, and the semiconductor layer positioned in a specific range outward from a line extending vertically downward from the short side of the electrode pad being a forbidden region.

Abstract: Example embodiments of the present invention relate to a metal oxide semiconductor (MOS) transistor and a method of manufacturing the MOS transistor. A MOS transistor may include a substrate, a semiconductor pattern, a gate insulation layer and/or source-drain regions. The substrate may include an active region and/or a field region. The semiconductor pattern may extend from the active region and may extend along the active region in a first direction. The gate insulation layer may be formed on the substrate to cover the semiconductor pattern. The gate electrode may be formed on the semiconductor pattern. The gate electrode may have a linear shape extending in the first direction. The source-drain regions may be formed at portions of the active region adjacent to the gate electrode in a second direction substantially perpendicular to the first direction.

Abstract: A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.

Abstract: The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.

Abstract: A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region.

Abstract: A dielectric layer may be formed by depositing the dielectric layer to an intermediate thickness and applying a nitridation process to the dielectric layer of intermediate thickness. The dielectric layer may then be deposited to the final, desired thickness.

Abstract: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.