Patents Issued in January 11, 2007
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Publication number: 20070007506Abstract: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to one embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between two glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100-x composition. According to another embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between chalcogenide glass layers and further having a silver layer above at least one of said chalcogenide glass layers and a conductive adhesion layer above said silver layer.Type: ApplicationFiled: May 31, 2006Publication date: January 11, 2007Inventors: Kristy Campbell, Jiutao Li, Allen McTeer, John Moore
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Publication number: 20070007507Abstract: Microcavity comprising two reflectors, at least one semiconductor layer separating said reflectors and a semiconductor quantum well wherein at least one of said reflectors and of said at least one semiconductor layer comprises a structure which is adjusted to localize a polariton in said microcavity.Type: ApplicationFiled: March 31, 2006Publication date: January 11, 2007Inventors: Benoit Deveaud-Pledran, Cristiano Ciuti, Francois Morier-Genoud
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Publication number: 20070007508Abstract: A semiconductor device may include a stress layer and a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: July 13, 2006Publication date: January 11, 2007Applicant: RJ Mears, LLCInventors: Robert Mears, Scott A. Kreps
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Publication number: 20070007509Abstract: A method for in situ formation of low defect, strained silicon and a device formed according to the method are disclosed. In one embodiment, a silicon germanium layer is formed on a substrate, and a portion of the silicon germanium layer is removed to expose a surface that is smoothed with a smoothing agent. A layer of strained silicon is formed on the silicon germanium layer. In various embodiments, the entire method is conducted in a single processing chamber, which is kept under vacuum.Type: ApplicationFiled: September 13, 2006Publication date: January 11, 2007Inventor: Mohamad Shaheen
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Publication number: 20070007510Abstract: In the present electronic structure, a first electronic device includes a first pair of electrodes and an active layer between the first pair of electrodes. An organic transistor is made up of organic material, a source, a drain, and a gate, one of the first pair of electrodes being connected to one of the source and drain of the organic transistor. A second electronic device includes a second pair of electrodes and an active layer between the second pair of electrodes, one of the second pair of electrodes being in contact with an insulating body adjacent the organic transistor.Type: ApplicationFiled: July 5, 2005Publication date: January 11, 2007Inventors: Igor Sokolik, Suzette Pangrle, Juri Krieger
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Publication number: 20070007511Abstract: A nanoparticle thin film, a method for dispersing nanoparticles and a method for producing nanoparticle thin film using the same. The method for dispersing nanoparticles may include modifying the surface of nanoparticles with a charged material, drying the surface-modified nanoparticles under vacuum and/or dispersing the dried nanoparticles in a solvent. According to the methods provided, the nanoparticle thin film may exhibit more stability, lesser defects and/or lesser aggregation of nanoparticles. In addition, 2-dimensional and/or 3-dimensional nanoparticle thin films may be produced in which nanoparticles may be more uniformly applied over larger areas. The nanoparticle thin films produced by the methods may be more effectively used for a variety of applications (e.g., flash memory devices, DRAMs, hard disks, luminescent devices, organic light-emitting diodes (OLEDs) or the like).Type: ApplicationFiled: March 30, 2006Publication date: January 11, 2007Inventors: Jae Choi, Kyung Cho, Seon Yoon, Eun Lee, Jae Lee
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Publication number: 20070007512Abstract: A method for producing a bio-inorganic conjugate is provided comprising supplying a plurality of inorganic particles that are axially anisotropic; and positioning biomolecules intermediate the particles to form a chain-like structure. Also provided is an organized microscopic structure capable of vectorial electron transport within the structure, comprising a plurality of inorganic oxide particles, each particle having at least two ends; a first molecule covalently attached to each end to form a plurality of constructs; and a second molecule attached to the first molecule so as to link the constructs and form an elongated substrate.Type: ApplicationFiled: May 22, 2006Publication date: January 11, 2007Inventors: Nada Dimitrijevic, Tijana Rajh, Zoran Saponjic, Bryan Rabatic, David Tiede, Lin Chen, Peter Zapol
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Publication number: 20070007513Abstract: Use of a fluoresceine derivative having the following formula: for the production of a electronic device, in particular a memory switch.Type: ApplicationFiled: May 22, 2006Publication date: January 11, 2007Inventors: Sabrina Conoci, Salvatore Petralia, Riccardo Sotgiu, Agostino Pirovano
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Publication number: 20070007514Abstract: A method for contacting an external contact area with a test contact is provided. The external contact area has a galvanically applied coating of a metal or a metal alloy. Before the contact is established between the external contact area and the test contact, the external contact area is wetted with a fluid including an inhibitor which contains an aliphatic hydrocarbon, a binder such as a white mineral oil and/or ethyl acetate, and a lubricant. The fluid lowers the contact resistance between the external contact area and the test contact.Type: ApplicationFiled: July 7, 2006Publication date: January 11, 2007Inventor: Horst Groeninger
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Publication number: 20070007515Abstract: A flat panel display apparatus includes a gate insulating layer having openings which define pixels. The flat panel display apparatus includes: a substrate; a source electrode and a drain electrode formed on the substrate; a semiconductor layer contacting the source electrode and the drain electrode; a gate formed on the substrate; an insulating layer formed between the source and drain electrodes and the gate, and including an opening; and a pixel electrode partially exposed by the opening of the insulating layer. The insulating layer acts as a gate insulating layer and a pixel definition layer defining the pixel electrode.Type: ApplicationFiled: July 5, 2006Publication date: January 11, 2007Inventors: Min-Chul Suh, Taek Ahn, Yong-Woo Park
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Publication number: 20070007516Abstract: The present invention provides a composite material in which an organic compound and an inorganic compound are composited, which is superior in conductivity, a composite material which is superior in a property of injecting carriers to an organic compound, and a composite material having low resistance with metal. Further, the present invention provides a light emitting element operating at a low drive voltage by applying the composite material to a current excitation type light emitting element, and a light emitting device consuming low power by manufacturing a light emitting device using the light emitting element. The present invention provides a composite material including metal oxide and an organic compound having an oxidation peak potential with respect to an oxidation-reduction potential of ferrocene in dimethylformamide (DMF) at room temperature within the range of 0 V and 1.5 V (vs. Fc/Fc+), preferably within the range of 0.1 V and 1.0 V (vs. Fc/Fc+).Type: ApplicationFiled: July 6, 2006Publication date: January 11, 2007Inventors: Satoshi Seo, Kumi Kojima
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Publication number: 20070007517Abstract: A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive adhesive layer. Bond pads on the die are electrically connected, to the traces. The traces are, in turn, electrically connected through conductive vias to conductive element sites on the opposite side of the base laminate through a dielectric layer, the conductive element sites carrying solder balls or other discrete conductive bonding elements for connection to higher-level packaging. A ground plane, may extend over the adhesive layer and frame the cavity, or also extend over the cavity to provide an enclosure for the die. In the former case, an encapsulant is applied over the die and electrical connections to the traces.Type: ApplicationFiled: September 19, 2006Publication date: January 11, 2007Inventors: Jerry Brooks, Steven Thummel
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Publication number: 20070007518Abstract: This invention relates to a method of encapsulating nano-dimensional structures, comprising: depositing at least one material upon a substrate such that the material includes at least one portion; and creating an oxidized layer located substantially adjacent to the deposited material such that the at least one portion of the deposited material becomes substantially encapsulated by a portion of the oxidized layer.Type: ApplicationFiled: July 5, 2005Publication date: January 11, 2007Inventors: Peter Mardilovich, Pavel Komilovich, Randy Hoffman
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Publication number: 20070007519Abstract: Power conversion circuits often consist of several MOSFETs operating in parallel. Due to thermal cycling and mechanical operations, MOSFETs or the respective electric connections of the MOSFETs may fail. According to the present invention, there is provided a diagnosis circuit for a plurality of parallel MOSFETs, which predicts or determines a possible failure on the basis of at least one of temperatures of the MOSFETs or gate voltages of the MOSFETs. Advantageously, a continuous monitoring of the MOSFETs may be provided and an early determination of failures of the MOSFETs can be provided.Type: ApplicationFiled: August 20, 2004Publication date: January 11, 2007Inventor: Thomas Durbaum
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Publication number: 20070007520Abstract: A display substrate includes a plastic substrate, a gate wiring, a gate insulation layer, an active layer, a data wiring and a drain wiring. The gate wiring includes a gate line and a gate electrode portion that is electrically connected to the gate line. The active layer is formed on a portion of the gate insulation layer. The data wiring includes a data line and a repair line that is electrically connected to the data line. The drain wiring is formed on a portion between the data line and the repair line. Therefore, an opening problem induced by a fine crack of the plastic substrate may be solved.Type: ApplicationFiled: November 15, 2005Publication date: January 11, 2007Applicant: Samsung Electronics Co., Ltd.Inventor: Jong-Hyun Seo
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Publication number: 20070007521Abstract: There is provided a semiconductor device comprising, a function unit portion including a circuit element, rank data presenting results of a rank-classification test on the circuit element, the rank-classification test being performed on the basis of a plurality of test criteria on wafer state, a non-volatile memory portion in which the rank data are stored, and a control portion reading out the rank data from the non-volatile memory portion, the control portion being used in a product test after packaging.Type: ApplicationFiled: March 23, 2006Publication date: January 11, 2007Inventor: Takanori Yoshimatsu
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Publication number: 20070007522Abstract: A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate, wherein the gate comprises at least one molybdenum-niobium alloy nitride layer. The gate insulating layer is formed over the substrate to cover the gate. The semiconductor layer is disposed over the gate insulating layer above the gate. The source/drain is disposed over the semiconductor layer.Type: ApplicationFiled: July 5, 2005Publication date: January 11, 2007Inventors: Wen-Kuang Tsao, Hung-I Hsu
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Publication number: 20070007523Abstract: An active matrix substrate includes a substrate, pixel units, driving lines, and an electrostatic discharge protection circuit. The substrate has an active region and a peripheral region. The pixel units are arranged to form a matrix inside the active region. The driving lines are inside the active region and the peripheral region, and electrically connected to pixel units. The ESD protection circuit is inside the peripheral region of the substrate and electrically connected to the pixel units. Furthermore, the ESD protection circuit includes a first conductive line, a second conductive line, first protective elements, and second protective elements. The first protective elements are between the first conductive line and the second conductive line, and are electrically connected to corresponding driving lines. The second protective elements are adjacent to the outer-most driving line and electrically connected to the first and the second conductive line for protecting the outermost driving line.Type: ApplicationFiled: September 18, 2005Publication date: January 11, 2007Inventor: Han-Chung Lai
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Publication number: 20070007524Abstract: A thin film transistor (TFT) plate having improved processing efficiency without degradation in performance and a method of fabricating the TFT plate are provided. The TFT plate includes gate insulating layer patterns made of dual layers. Upper portions of both sidewalls of an upper gate insulating layer pattern are substantially aligned with both sidewalls of a gate electrode. Lower portions of both sidewalls of the upper gate insulating layer pattern are substantially aligned with a boundary portion between a lightly doped region and a source region and a boundary portion between the lightly doped region and a drain region. Thus, the concentration of the lightly doped region under a lower gate insulating layer pattern gradually changes.Type: ApplicationFiled: June 30, 2006Publication date: January 11, 2007Inventors: Chun-gi You, Kyung-min Park, Gyung-soon Park
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Publication number: 20070007525Abstract: A liquid crystal display (LCD) capable of preventing texture, light leakage, and/or formation of an instantaneous afterimage while improving an aperture ratio is presented. The LCD includes a first insulating substrate, a gate line formed on the first insulating substrate, a data line insulated from the gate line and extending substantially perpendicularly to the gate line wherein the gate line and the data line define a pixel, and a thin film transistor (TFT) connected to the gate line and the data line. A first sub-pixel electrode is connected to the TFT, and a second sub-pixel electrode is capacitively coupled to the first sub-pixel electrode through a coupling electrode, the second sub-pixel electrode being separated from the first sub-pixel electrode by a gap.Type: ApplicationFiled: July 5, 2006Publication date: January 11, 2007Inventor: Soon-il Ahn
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Publication number: 20070007526Abstract: The proceeding of peeling of a conductive layer in the vicinity of terminals is prevented. A display panel includes a conductive layer extending to the outside of terminals, and the conductive layer has slits extending in directions from one end face to the other end face alternately at two end faces along the extending direction of the conductive layer.Type: ApplicationFiled: July 7, 2006Publication date: January 11, 2007Inventors: Saori Sugiyama, Yasuko Gotoh
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Publication number: 20070007527Abstract: It is a problem to provide a light-emitting device capable of obtaining a constant brightness without being affected by deterioration in an organic light-emitting layer or temperature change, and of making desired color display. The lowering in OLED brightness due to deterioration is reduced by causing the OLED to emit light while keeping constant the current flowing through the OLED instead of causing the OLED to emit light while keeping constant the OLED drive voltage. Namely, OLED brightness is controlled not by voltage but by current thereby preventing against the change in OLED brightness due to deterioration of OLED. Specifically, the drain current Id of a transistor for supplying a current to the OLED is controlled in a signal line drive circuit thereby keeping constant the drain current Id without relying upon the value of a load resistance.Type: ApplicationFiled: September 8, 2006Publication date: January 11, 2007Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Jun Koyama
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Publication number: 20070007528Abstract: A thin film transistor according to the present invention includes a gate electrode, a semiconductor layer having a channel forming region arranged on the gate electrode and an impurity region arranged on a part of the channel forming region, source and drain electrodes electrically connected to the impurity region, and a gate insulating film that electrically insulates the gate electrode and the semiconductor layer, wherein the distance between the upper end of the gate electrode and the upper end of the impurity region is larger than the distance between the upper end of the gate electrode and the upper end of the channel forming region.Type: ApplicationFiled: September 11, 2006Publication date: January 11, 2007Inventors: Takatoshi Tsujimura, Shinya Ono, Mitsuo Morooka, Koichi Miwa
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Publication number: 20070007529Abstract: A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal, and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 ?m or less in width, and allowing the metal to react with silicon. A high performance TFT can be realized.Type: ApplicationFiled: September 18, 2006Publication date: January 11, 2007Applicant: SEMICONDUCTOR ENERGY LABORATORY LTD.Inventors: Yasuhiko Takemura, Hongyong Zhang, Satoshi Teramoto
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Publication number: 20070007530Abstract: A thin-film transistor includes a source and a drain that have each been replaced with a metal by a heat-treatment at a temperature within the range of 250° C. and 500° C.Type: ApplicationFiled: June 26, 2006Publication date: January 11, 2007Inventors: Man Wong, Hoi Kwok, Dongli Zhang
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Publication number: 20070007531Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, a first gate insulating layer, a second gate insulating layer, a first gate electrode, and a second gate electrode. The semiconductor substrate is divided into a first region and a second region. The first gate insulating layer is formed on the first region. The second gate insulating layer is formed on the second region and formed thinner than the first gate insulating layer. The first gate electrode is formed on the first gate insulating layer.Type: ApplicationFiled: July 7, 2006Publication date: January 11, 2007Inventor: Kwak Ho
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Publication number: 20070007532Abstract: A stacked semiconductor device and a method for manufacturing the stacked semiconductor device are disclosed. The stacked semiconductor device comprises a seed layer doped with first impurities, a multilayer insulation pattern disposed on the seed layer comprising at least two insulation interlayer patterns stacked vertically on the seed layer and an opening. The stacked semiconductor device further comprises at least one active thin layer, wherein each of the at least one active thin layers is disposed on one of the at least two insulation interlayer patterns of the multilayer insulation pattern, and wherein the opening exposes a side surface of each of the at least one active thin layers. The stacked semiconductor device still further comprises and a first plug disposed on the seed layer and doped with second impurities substantially the same as the first impurities, wherein the opening exposes a top surface of the first plug.Type: ApplicationFiled: June 26, 2006Publication date: January 11, 2007Inventors: Sung-Kwan Kang, Yu-Gyun Shin, Jong-Wook Lee, Yong-Hoon Son
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Publication number: 20070007533Abstract: A pixel array structure is provided. The pixel array structure comprises a plurality of pixel units and a plurality of dielectric walls. Each dielectric wall is disposed between two neighboring pixel units, wherein each pixel unit comprises at least one organic light emitting diode and a complementary metal-oxide-semiconductor (CMOS). The organic light emitting diode comprises a transparent electrode, a bottom electrode, and a light emitting material between the transparent electrode and the bottom electrode. The CMOS is disposed in a substrate. The substrate comprises a top-metal-layer structure located thereon and the top-metal-layer structure comprises an upmost top metal layer. Further, the bottom electrode of the CMOS is the upmost top metal layer of the top-metal-layer structure and the upmost top metal layer is a titanium metal layer.Type: ApplicationFiled: July 8, 2005Publication date: January 11, 2007Inventors: Yi-Tyng Wu, Tsuan-Lun Lung, Chih-Hung Cheng, Kuan-Te Pai
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Publication number: 20070007534Abstract: Provided are an optical mask, a method of manufacturing a thin film transistor array substrate using the optical mask, and a thin film transistor array substrate manufactured by the method. The method includes forming a data metal layer on a substrate, forming an insulating layer on the data metal layer, patterning a contact hole exposing a portion of the data metal layer and at least one contact projection projecting toward an interior of the contact hole by etching the insulating layer, and forming a pixel electrode or an auxiliary data line terminal electrically connected to the data metal layer through the contact hole and the contact projection.Type: ApplicationFiled: June 21, 2006Publication date: January 11, 2007Inventors: In-woo Kim, Young-goo Song, Min-sik Um, Byung-duk Yang, Min-wook Park, Young-hoon Yoo
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Publication number: 20070007535Abstract: A pixel circuit for driving a plurality of pixel units within a display includes: a plurality of scanning lines formed within the display for transmitting scanning signals to the pixel units; a plurality of data lines formed within the display and transversely crossing the scanning lines for transmitting data signals to the pixel units, respectively; and a plurality of LDD-TFTs. The LDD-TFT is coupled to a respective scanning line, a respective data line and a driving transistor. The LDD-TFT includes a first lightly doped drain that is most closed to the driving transistor and that has a first length, and a second lightly doped drain that has a second length shorter than the first length.Type: ApplicationFiled: July 6, 2006Publication date: January 11, 2007Inventors: Yu-Chun Tang, Li-Wei Shih
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Publication number: 20070007536Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.Type: ApplicationFiled: August 17, 2006Publication date: January 11, 2007Applicant: Renesas Technology CorporationInventor: Hideto Hidaka
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Publication number: 20070007537Abstract: A semiconductor device comprises: a first semiconductor layer of silicon carbide of a first conductivity type; a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer; a main electrode layer of silicon carbide of the first conductivity type selectively provided on the second semiconductor layer; a gate insulating film provided on the second semiconductor layer; a gate electrode formed on the gate insulating film; and a third semiconductor layer of the first conductivity type intervening a current path which is formed between the main electrode layer and the first semiconductor layer when an ON voltage is applied to the gate electrode. The third semiconductor layer is selectively provided on the first semiconductor layer and is adjacent to the second semiconductor layer. A doping density of the third semiconductor layer is higher than a doping density of the first semiconductor layer.Type: ApplicationFiled: July 3, 2006Publication date: January 11, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo Ogura, Ichiro Omura
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Publication number: 20070007538Abstract: Disclosed herein is a light-emitting device comprising a transparent or semi-transparent first substrate, a second substrate provided opposite to the first substrate, a transparent or semi-transparent first electrode provided on the first substrate, a second electrode provided on the second substrate so as to be opposite to the first electrode, and a light-emitting layer which contains a metal oxide semiconductor porous body, by the surface of which an organic light-emitting material is supported, and is provided between the first electrode and the second electrode.Type: ApplicationFiled: June 10, 2004Publication date: January 11, 2007Inventors: Masayuki Ono, Kenya Hori, Toshiyuki Aoyama, Masaru Odagiri, Kumio Nago, Kenji Hasegawa
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Publication number: 20070007539Abstract: The present invention relates to a light emitting diode module, as well as a backlight assembly and a display device including the same. The light emitting diode module according to an exemplary embodiment of the present invention includes a printed circuit board having a plurality of junction holes, a plurality of light emitting diodes having a light emitting portion for emitting light and a lead portion with one end electrically connected to the light emitting portion and the other end positioned in a corresponding junction hole, and a junction member filled in the corresponding junction hole in which the lead portion is positioned.Type: ApplicationFiled: July 10, 2006Publication date: January 11, 2007Inventors: Gi-Cherl Kim, Sang-Yu Lee, Byung-Choon Yang, Chun-Ho Song, Don-Chan Cho
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Publication number: 20070007540Abstract: A light-emitting device (200) has a submount (100) and a plate for heat transfer (300) having a metallic plate (30). The submount (100) has a mount base (10), at least one light-emitting diode chip (5) mounted thereon and electrically conducting lines (12-17) formed on the mount base (10) to be connected electrically to the light-emitting diode chip (5). A first plane (11) of the mount base (10) of the submount (100) is bonded thermally to the first plate (300). For example, the plate is a circuit board having a metallic plate (30), and the submount (100) is bonded thermally to the metallic plate (30) of the one of the at least one plate (300). In an example, a second plate for heat transfer is also bonded thermally to a second plane of the mount base (100) for providing a plurality of heat transfer paths.Type: ApplicationFiled: May 26, 2004Publication date: January 11, 2007Applicant: Matsushita Electric Works, Ltd.Inventors: Takuma Hashimoto, Masaru Sugimoto, Ryoji Yokotani, Koji Nishioka, Yutaka Iwahori, Shinya Ishizaki, Toshiyuki Suzuki, Yoshiyuki Uchinono, Masahide Muto, Satoshi Mori, Hideyoshi Kimura
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Publication number: 20070007541Abstract: The invention relates to a nitride light emitting device including first and second conductivity type nitride layers and a plurality of active regions emitting light of different wavelength. The active regions are sequentially formed between the first and the second conductivity type nitride layers. The active regions include at least one first active region having a plurality of first quantum barrier layers and quantum well layers, and a second active region emitting light of a wavelength larger than that of the first active region. The second active region has a plurality of second quantum barrier layers and at least one discontinuous quantum well structure formed between the plurality of second quantum barrier layers. The discontinuous quantum well structure comprises a plurality of quantum dots or crystallites.Type: ApplicationFiled: January 13, 2006Publication date: January 11, 2007Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Min Kim, Kyeong Min, Masayoshi Koike
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Publication number: 20070007542Abstract: High-output white light emitting devices that, being unsusceptible to deterioration despite large drive power, are usable in lighting applications. The light-emitting devices are formed by combining a phosphor component (4) with an LED (2, 3). The phosphorescent component (4) is selected from materials in which the relation between thermal conductivity ? (W/cmK) and absorption coefficient ? (1/cm) with respect to light from the LED (2,3) is ?? >2, and the substrate (2) utilized for the LED is selected from SiC, GaN or AIN, with LED and phosphorescent component (4) being disposed in contact. Alternatively, the substrate (2) utilized for the LED is sapphire, and the phosphorescent component (4) is disposed in contact with the substrate side of the LED. Allowing heat to be dissipated sufficiently even with input power being 200 W/cm2 or more, a configuration of this sort can be used free from the influences of temperature.Type: ApplicationFiled: July 7, 2005Publication date: January 11, 2007Applicant: SUMITOMO ELECTRIC INDUSTRIES,LTD.Inventor: Shinsuke Fujiwara
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Publication number: 20070007543Abstract: A semiconductor light emitting device in the present invention is formed by laminating an epitaxial layer 30 including an AlGaInP active layer and a second wafer 23 which transmits light derived from the active layer. The crystal axes of the epitaxial layer 30 and the second wafer 23 are generally aligned with each other and are in the range of ?15° to +15° with respect to a lateral face {100} of the second wafer 23. This semiconductor light emitting device, which is a joining type with high external emission efficiency, allows uniform wafer bonding to be achieved over the entire wafer face with ease and with a high yield without causing bonding failure and wafer cracks.Type: ApplicationFiled: June 30, 2006Publication date: January 11, 2007Applicant: SHARP KABUSHIKI KAISHAInventors: Eiji Kametani, Yukari Inoguchi, Nobuyuki Watanabe, Tetsuroh Murakami
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Publication number: 20070007544Abstract: Methods of forming a semiconductor device can include forming a semiconductor structure on a substrate, the semiconductor structure having mesa sidewalls and a mesa surface opposite the substrate. A contact layer can be formed on the mesa surface wherein the contact layer has sidewalls and a contact surface opposite the mesa surface and wherein the contact layer extends across substantially an entirety of the mesa surface. A passivation layer can be formed on the mesa sidewalls and on portions of the contact layer sidewalls adjacent the mesa surface, and the passivation layer can expose substantially an entirety of the contact surface of the contact layer. Related devices are also discussed.Type: ApplicationFiled: September 13, 2006Publication date: January 11, 2007Inventors: Kevin Haberern, Raymond Rosado, Michael Bergman, David Emerson
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Publication number: 20070007545Abstract: Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC).Type: ApplicationFiled: November 30, 2005Publication date: January 11, 2007Inventors: Javier Salcedo, Juin Liou, Joseph Bernier, Donald Whitney
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Publication number: 20070007546Abstract: The present invention provides a manufacturing method enabling suppression of threshold voltage fluctuation without giving any damage to a gate insulating film when a transistor structure is formed at first in a field effect transistor type of gas sensor and then an electrode with a material responsive to a gas to be detected is formed. The gate insulating film is a film stack including at least an SiO2 film and an SRN (Si-rich nitride) film. The SRN film functions as a etching stopper film when the gate insulating film is exposed by etching of an inter-layer insulating film. Pressure resistance of the gate insulating film is preserved with SiO2. An electric charge in the SRN film can be removed with a lower voltage as compare to that required for removing an electric charge in the Si3N4 film, which enables suppression of threshold voltage fluctuation in gas sensor transistors.Type: ApplicationFiled: June 29, 2006Publication date: January 11, 2007Inventors: Yasushi Goto, Toshiyuki Mine, Koichi Yokosawa
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Publication number: 20070007547Abstract: A III-nitride power semiconductor device that includes a gate barrier under the gate thereof, and a method for fabricating the device.Type: ApplicationFiled: July 6, 2006Publication date: January 11, 2007Inventor: Robert Beach
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Publication number: 20070007548Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.Type: ApplicationFiled: July 6, 2005Publication date: January 11, 2007Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, NOVELLUS SYSTEMS INC.Inventors: Richard Conti, Ronald Bourque, Nancy Klymko, Anita Madan, Michael Smits, Roy Tilghman, Kwong Wong, Daewon Yang
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Publication number: 20070007549Abstract: A plurality of terminals is formed in a basic cell. One terminal has first to fifth patterns. The first and second patterns are arranged to be spaced from each other. The third and fourth patterns are arranged to be spaced from each other, and are arranged so as to be adjacent to the first and second patterns. The fifth pattern is arranged between the first and second grid lines to interconnect the first to fourth patterns. A dimension of the fifth pattern in a direction of extension of a plurality of grid lines is set to be smaller than a dimension obtained by adding dimensions of the first and second patterns in the direction of extension of the grid lines to an interval of the both patterns, and a dimension obtained by adding dimensions of the third and fourth patterns to an interval of the both patterns.Type: ApplicationFiled: July 5, 2006Publication date: January 11, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinji Fujii, Toshiki Morimoto
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Publication number: 20070007550Abstract: A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a spacer shape is formed on the sidewalls of the first gate line with a thin insulating layer interposed therebetween. The first contact electrode is vertically connected with the first gate line. The first dummy gates are formed in array spaced a predetermined interval from the first gate line on the semiconductor substrate. The second gate pad of a spacer shape is formed on the sidewalls of the first dummy gates with a thin insulating layer interposed therebetween. The second gate pad is connected to the second gate line and is also gap-filled between the first dummy gates. The second contact electrode is vertically connected with the second gate pad.Type: ApplicationFiled: July 5, 2006Publication date: January 11, 2007Inventor: Lee Bum
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Publication number: 20070007551Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.Type: ApplicationFiled: September 14, 2006Publication date: January 11, 2007Inventors: Masayuki Ohayashi, Takashi Yokoi
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Publication number: 20070007552Abstract: Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a latter deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.Type: ApplicationFiled: July 5, 2005Publication date: January 11, 2007Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES (AMD)Inventors: Huilong Zhu, Brian Tessier, Huicai Zhong
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Publication number: 20070007553Abstract: An object of the present invention is to provide, in an FeRAM memory device fixed to a cell plate, a memory device in which RES_N (source line) of a reset transistor for resetting a storage node has a low resistance. A memory cell (101) includes a ferroelectric capacitance, a first MOS transistor for selecting the memory cell, and a second MOS transistor which is a reset transistor for resetting the storage node. Potential is supplied to RES_N (source line) (impurity activation region) of the second MOS transistor through the following two conductive layers: an impurity activation region which is a conductive layer below an upper electrode of the ferroelectric capacitance, and a bit-line formation wiring layer making up a bit line BL. This configuration makes it possible to supply potential to RES_N (source line) with a low resistance and perform a stable operation.Type: ApplicationFiled: June 30, 2006Publication date: January 11, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuo Murakuki, Takashi Miki
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Publication number: 20070007554Abstract: The present invention relates to a display device, such as an organic electroluminescent device, for preventing corrosion of a signal line. A display device according to the present invention, comprising a substrate; a first electrode layer disposed over the substrate; a second electrode layer disposed to cover the first electrode layer and configured to electrically communicate with the first electrode layer; and a pixel disposed over the substrate, wherein a signal line is defined as an electrode layer including the first electrode layer and the second electrode layer, wherein the first electrode layer is in electrical communication with the pixel. The display device according to the present invention can prevent the material of the signal line from being corroded. Also, the device can prevent the reduction of brightness and the increase of power consumption.Type: ApplicationFiled: March 15, 2006Publication date: January 11, 2007Inventor: Chun Lee
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Publication number: 20070007555Abstract: A charge splitter for separating an incoming charge packet into two outgoing packets while the charge is in a static state, i.e., not while it is flowing down a channel or over a barrier. A splitting gate may have a biasing charge impressed upon it, such as via the application of voltage or current sources to opposite ends thereof, applying a bias to a semiconductor body portion of the gate structure, or by physically separate the splitting gate into multiple sections that each have different applied voltages or currents When discharge barrier gates are operated, different amounts of charge will thus flow to different output storage gates.Type: ApplicationFiled: July 6, 2005Publication date: January 11, 2007Applicant: Kenet, Inc.Inventors: Michael Anthony, Edward Kohler