Abstract: On the front side of an n-type semiconductor substrate 5, p-type regions 7 are two-dimensionally arranged in an array. A high-concentration n-type region 9 and a p-type region 11 are disposed between the p-type regions 7 adjacent each other. The high-concentration n-type region 9 is formed by diffusing an n-type impurity from the front side of the substrate 5 so as to surround the p-type region 7 as seen from the front side. The p-type region 11 is formed by diffusing a p-type impurity from the front side of the substrate 5 so as to surround the p-type region 7 and high-concentration n-type region 9 as seen from the front side. Formed on the front side of the n-type semiconductor substrate 5 are an electrode 15 electrically connected to the p-type region 7 and an electrode 19 electrically connected to the high-concentration n-type region 9 and the p-type region 11.

Abstract: A system-on-chip (SoC) that is immune to electromagnetic interference has block shield rings fabricated therein. The SoC includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated circuit from electromagnetic interference. The EMI shield ring is grounded and includes a metal rampart consisting of multi-layer metals and vias. A pickup diffusion is connected to the metal rampart. In one embodiment, the memory block is also shielded.

Abstract: A semiconductor chip 6 is mounted on a flexible substrate 1 wherein internal connecting electrodes 4 to be connected to protruding electrodes 7 on an element surface of the semiconductor chip 6 and wires 3 for connecting the internal connecting electrodes 4 and the external connecting electrodes to be connected to external devices are provided on a surface of an insulating film 2. The internal connecting electrodes 4, the wires 3 and the surface of the insulating film 2 are coated with a protective film 5. The protruding electrodes 7 and the internal connecting electrodes 4 are connected by arranging the element surface of the semiconductor chip 6 to face the flexible substrate 1 and causing the protruding electrodes 7 on the element surface to pierce the protective film 5. This semiconductor device manufacturing method makes it possible to prevent ion migration and reduce occurrence of short circuit between wires.

Abstract: A thin film transistor (TFT) structure includes a substrate, a polysilicon structure including a plurality of channel regions, at least one lightly doped region and at least one heavily doped source/drain region, a plurality of gate structures, and an insulating layer formed between the gate structures and the polysilicon structure. The thickness of a first portion of the insulating layer under and between the gate structures is greater than the thickness of a second portion of the insulating layer adjacent to the first portion. At least one lightly doped region is formed under the first portion of the insulating layer and at least one heavily doped source/drain region is formed under the second portion of the insulating layer via the same doping procedure.

Abstract: Microelectronic apparatus having protection against high frequency crosstalk radiation, comprising: a planar insulating substrate; an active semiconductor electronic device located over a first region of the insulating substrate; and a doped semiconductor located in a second region of the insulating substrate substantially surrounding the first region. Apparatus further comprising a dissipative conductor overlaying and adjacent to the doped semiconductor. Apparatus additionally comprising metallic test probe contacts making electrical connections with the active semiconductor electronic device. Application of the apparatus to dissipate crosstalk radiation having a center frequency within a range between about 1 gigahertz and about 1,000 gigahertz. Methods for making the apparatus.

Abstract: A semi-fusible link system and method for a multi-layer integrated circuit including active circuitry on a first layer having a metal one layer including a semi-fusible link element on a second layer having a metal two layer adapted for interconnecting with the metal one layer, and a selector circuit disposed on the first layer.

Abstract: A semiconductor package encapsulating a semiconductor chip provides inner leads and outer leads for establishing electrical connections with the substrate. Herein, a lead frame is set into the metal mold, into which a resin is injected and which is clamped in proximity to the outer leads. Thus, the semiconductor package is sealed so as to avoid unwanted formation of resin burrs around lower surfaces of the inner leads. In addition, a semiconductor device is produced using a package in which a semiconductor chip mounted on a stage and terminals are embedded within a resin. Each terminal provides an electrode surface, an interconnecting portion, and an exposed terminal surface. Herein, an isolation portion is formed as an integral part of the package made by the resin and is arranged in the prescribed area between the electrode surface and the exposed terminal surface.

Abstract: A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

Abstract: An LED assembly includes a heat sink and a submount. The heat sink has a top mating surface that is solder wettable, and the submount has a bottom mating surface that is solder wettable. The top and the bottom mating surfaces have substantially the same shape and area. The submount is soldered atop the heat sink. During solder reflow, the molten solder causes the submount to align with the top mating surface of the heat sink. The LED assembly may further include a substrate having a top mating surface, and the heat sink may further include a bottom mating surface. The top and bottom mating surfaces have substantially the same shape and area. The heat sink is soldered atop the substrate. During solder reflow, the molten solder causes the heat sink to align with the top mating surface of the substrate.

Abstract: A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.

Abstract: In order to manufacture a thin and small semiconductor device at low cost, the semiconductor device and its manufacturing method are disclosed. The semiconductor device comprises: a film wiring substrate made of insulating resin; a semiconductor chip fixed to the main surface of the wiring substrate; conductive wires to connect terminals of the semiconductor chip and wirings on the main surface of the wiring substrate; an encapsulation made of insulating resin integrally laminated on the main surface of the wiring substrate and covering the semiconductor chip and the bonding wires; and conductors penetrating through the wiring substrate and having one ends connected to the wirings on the main surface of the wiring substrate and the other ends protruding to the rear surface of the wiring substrate to form external terminals formed of bump electrodes, wherein the external terminals form the ball grid array.

Abstract: Provided are a glass for a window which glass is suitably fitted to a semiconductor package made of a plastic and a glass window for the semiconductor package which glass window has various functions, the glass (1) being for use as a window material for a semiconductor package made of a plastic and having an average linear expansion coefficient of 120×10?7/° C. to 180×10?7/° C. at a temperature of 100 to 300° C.

Abstract: An apparatus and method to provide a micro-electromechanical systems (MEMS) radio frequency (RF) switch module with a vertical via. The MEMS RF switch module includes a MEMS die coupled to a cap section. The vertical via passes through the cap section to electrically couple an RF switch array of the MEMS die to a printed circuit board (PCB). In one embodiment, the MEMS die includes a trace ring surrounding at least a portion of the RF switch array so that a signal may enter or exit the MEMS RF switch module using the vertical via without crossing the trace ring.

Abstract: A multi-layer piezoelectric component includes a plurality of piezoelectric layers, a first inner electrode sheet, a second inner electrode sheet, a first outer electrode, and a second outer electrode. The piezoelectric layers are wound around an axis to form a laminar roll having first and second end faces transverse to the axis. The piezoelectric layers include at least one first layer and at least one second layer. Each of the first and second layers has opposite first and second edges respectively at the first and second end faces, and opposite inner and outer circumferential surfaces. The first and second inner electrode sheets respectively overlie the inner circumferential surfaces of the first and second layers. The first and second outer electrodes are respectively and electrically connected to the first and second inner electrode sheets.

Abstract: A semiconductor package includes multiple embedded chips, each chip including a common circuit having substantially the same common function. The common circuit in a selected one of the chips is enabled. The common circuit in one or more other ones of the chips is disabled. As a result, the enabled common circuit performs the common function for the selected chip and the one or more other chips.

Abstract: A multi-chip package comprises a double-sided circuit board having first and second surfaces. Each surface has a package area and a peripheral area. Each package area has a chip mounting area on which a chip is attached, and a bonding area with which the chip is electrically connected. The peripheral area of the first surface has a runner area on which molding compound flows, and the peripheral area of the second surface has external connection pattern with which the bonding areas are electrically connected. In particular, the circuit board has gate holes, which are co-located on each surface to result in a common hole.

Abstract: Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

Abstract: A chip structure including a chip, a first passivation layer, a redistribution layer and a second passivation layer is provided. The chip has a wire bonding area adjacent to one side or two sides adjacent to each other of the chip, wherein the chip has multiple first bonding pads disposed inside the wire bonding area and multiple second pads disposed outside the wire bonding area. The first passivation layer disposed on the chip has multiple first openings by which the first and the second bonding pads are exposed. The redistribution layer is disposed on the first passivation layer and extended from the second bonding pads to the wire bonding area. The redistribution layer has multiple third bonding pads located inside the wire bonding area. The second passivation layer disposed over the redistribution layer has multiple second openings by which the first and the third bonding pads are exposed.

Abstract: Methods of forming a semiconductor assembly are described which include a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form a grid array such as a ball grid array (“BGA”) or other similar array-type structure of dielectric conductive elements. The leads may have inner bond ends including a contact pad thermocompressively bonded to a bond pad of the semiconductor chip to enable electrical communication therewith and a lead section with increased flexibility to improve the thermocompressive bond. The inner bond ends may also be wirebonded to the bond pads.

Abstract: A chip embedded package structure is provided. A stiffener is disposed on a tape. The tape has at least an alignment mark and the stiffener has at least a chip opening. A chip having a plurality of bonding pads thereon is disposed on the tape within the chip opening such that the bonding pads face the tape. A plurality of through holes is formed in the tape to expose the bonding pads respectively. After that, an electrically conductive material is deposited to fill the through holes and form a plurality of conductive vias that connects with the bonding pads respectively. A multi-layered interconnection structure is formed on the surface of the tape away from the chip. The multi-layered interconnection structure has an inner circuit that connects to the conductive vias. The inner circuit has a plurality of metallic pads disposed on the outer surface of the multi-layered interconnection structure.

Abstract: A semiconductor device mounting structure includes a bus bar of which a first end part is connected to a high-temperature power-purpose semiconductor device and a second end is connected to another device that is required to be kept at a lower temperature than the semiconductor device. The bus bar includes a ribbonlike part zigzagging between the first and second ends. The ribbonlike part of the bus bar can improve the cooling effect by increasing the length of the path through which the heat travels in the lengthwise direction of the bus bar. Thus, the heat emitted from the semiconductor device is prevented from being transferred to a peripheral circuit element through the bus bar used for supplying electric power to the circuit element from the semiconductor device.

Abstract: A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.

Abstract: An assembly includes a circuit board with a ball grid array device attached to a first side of the circuit board. A brace surrounding the ball grid array device has a series of mounting holes and a series of members extending between the mounting holes. The brace is removably secured to the first side of the circuit board at the mounting holes.

Abstract: An integrated circuit ground system includes an integrated circuit (IC) ground connection, first and second IC package pins, first and second printed circuit board (PCB) pads, a PCB ground connection, and a resonant circuit. The IC ground connection is fabricated on a substrate of an integrated circuit. The first IC package pin is operably coupled to the IC ground connection via a first bond wire. The second IC package pin is operably coupled to the IC ground connection via a second bond wire. The second PCB pad is operably coupled to the second IC package pin to provide a low impedance DC ground connection for the integrated circuit to the printed circuit board. The resonant circuit is operably coupling the first IC package pin to the first PCB pad, wherein the resonant circuit is tuned to resonant with the first bond wire at high frequency range to provide a low impedance AC ground connection for the integrated circuit to the printed circuit board within the high frequency range.

Abstract: The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.

Abstract: A flip-chip semiconductor package with a lead frame and a method for fabricating the same are provided. The lead frame has a plurality of leads, each lead having an upper surface, a lower surface, and an inner end directed toward the center of the lead frame. A recessed portion is formed on the upper surface of the inner end of each lead, making the inner end shaped as a stepped structure. The depth of the recessed portion is equal to a height of a reflow-collapsed solder bump that is for electrically connecting a chip to the lead. At least one chip is electrically connected to the leads in a flip-chip manner via a plurality of solder bumps bonded to the recessed portions. An encapsulation body is formed to encapsulate the lead frame, chip and solder bumps, with the lower surfaces of the leads being exposed from the encapsulation body.

Abstract: A socket is provided which has an insulative housing surrounding a metal substrate. The substrate has an array of apertures which are located in spatially arranged order to accommodate the precise pattern desired for the device to be connected. Contact assemblies include stamped and formed contacts having an insulative plastic molded over a central section of the contact. A grounding clip surrounds the housing and is conductively connected to the substrate, and has spring arms which are connectable to heat sink hardware on one side thereof and to a printed circuit board on the other side.

Abstract: The present invention discloses a bump for a semiconductor package, a semiconductor package applying the bump, and a method for fabricating the semiconductor package. As a second bump unit contacting an electrode terminal of a PCB has a smaller width than a first bump unit contacting an electrode pad of a semiconductor chip through a metal adhering layer, even if a pitch between the electrode pads of the semiconductor chip does not correspond to the pitch between the electrode terminals of the PCB, contact reliability is improved by the bump. In addition, the bump does not contact lines adjacent to the electrode terminal of the PCB, thereby preventing a mis-operation of the semiconductor package. Accordingly, the pitch between the electrode pads of the semiconductor chip and the pitch between the bumps can be minimized.

Abstract: Dielectric rings are configured to be disposed around contact pads on a surface of a semiconductor device or another substrate. The rings may be fabricated or otherwise disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures, such as solder balls, are secured to the contact pads. Upon connecting the semiconductor device face-down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the rings prevent the material of solder balls protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The rings may be preformed structures or fabricated on the surface of the semiconductor device or other substrate. For example, stereolithographic techniques may be used to form the rings.

Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.

Abstract: A conductor with improved magnetic field per current ratio is disclosed. The conductor includes a magnetic liner lining a second surface and sides thereof. The corners of the conductor where the second surface and the sides meet are rounded. The rounded corners have been found to improve the concentration of magnetic flux in the magnetic liner.

Abstract: A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a conductive spacer liner that effectively prevents the contact structure from being damaged during removal of the surrounding sacrificial contact medium material. The sacrificial contact medium is then replaced with a non-boron doped dielectric material.

Abstract: A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP type semiconductor device, is configured that an insulating layer is formed by stacking a plurality of resin layers on a semiconductor chip formed with an electronic circuit, wiring layers are buried in the insulating layer and electrically connected to electrodes, and formation areas of the plurality of resin layers become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, so that a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.

Abstract: A technology for easily forming a multi-layer wiring structure that is fine and reliable. In the multi-layer wiring structure, the lower-layer wiring and the upper-layer wiring that are formed to sandwich an insulating layer are electrically connected to each other in a projection formed in the lower-layer wiring. The projection includes a columnar conductive member and the upper and lower layers thereof and each of the lower layer and the upper layer is formed of a conductive layer formed over the entire lower-layer wiring. The upper-layer is electrically connected to the lower-layer wiring in the portion where the projection is exposed substantially on the same plane as the top surface of the insulating layer.

Abstract: A disclosed semiconductor apparatus includes a substrate, a first insulating layer formed on the substrate, the first insulating layer including a Cu wiring part, and a second insulating layer formed on the substrate, the second insulating layer including a Cu via plug part electrically connected to the Cu wiring part. The first insulating layer is a porous insulating film having an elastic modulus of 5 GPa or more and a hardness of 0.6 GPa or more, and the second insulating layer has an elastic modulus of no less than 10 GPa and a hardness no less than 1 GPa.

Abstract: A capacitive structure is provided that includes secondary stacks of superposed secondary electrodes that each include transverse branches connected via a longitudinal branch, means for connecting the superposed secondary electrodes of each of the stacks, first and second means for successively and alternately connecting so as to constitute a first secondary group of secondary stacks and a second secondary group of secondary stacks, at least two principal stacks of superposed principal electrodes which each include transverse branches that are connected via a longitudinal branch such that the transverse branches of the principal electrodes and the transverse branches of the secondary electrodes of the rows extend opposite one another and between one another in an alternating fashion, means for connecting the superposed principal electrodes of each of the principal stacks, and means for connecting the principal stacks so as to constitute a group of stacks of principal electrodes.

Abstract: A chip generally comprising a logic circuit and a plurality of pads. The logic circuit may be configured to operate in a plurality of modes in response to a mode signal. The pads may be configurable into a plurality of subsets such that one of the subsets is used by the logic circuit at a time in response to the mode signal.

Abstract: Methods and systems for current sharing between power semiconductors in an assembly are provided. The power semiconductor assembly includes a plurality of power semiconductors, each comprising at least one output conductor, the plurality of output conductors are electrically coupled together in parallel, an output bus network configured to transpose the output conductors such that magnetic fields causing a current output imbalance between the plurality of power semiconductors are substantially canceled.

Abstract: An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the full metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.

Abstract: A semiconductor device has interconnecting lines disposed side by side in a dielectric film. Mutually adjacent pairs of interconnecting lines are separated by a substantially constant distance from top to bottom, but the width of each interconnecting line varies from top to bottom. For example, the interconnecting lines may have T-shaped or trapezoidal cross sections, interconnecting lines having wide tops alternating with interconnecting lines having wide bottoms. These cross-sectional shapes can be formed by simple fabrication processes. Since the facing sides of mutually adjacent interconnecting lines do not form mutually parallel vertical planes and therefore do not function as parallel plate electrodes, the interconnect capacitance is reduced.

Abstract: Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically connected to a lower surface of the substrate. That is, with respect to one substrate, semiconductor dies can be stacked on upper and lower surfaces of the substrate. Also, underfill is formed between the respective semiconductor dies and the substrate, thereby enhancing bonding forces between the respective semiconductor dies and the substrate. In addition to stacking the semiconductor dies, packages can be stacked with each other. That is, it is possible to stack a plurality of completed wafer level packages with each other in an up-and-down direction.

Abstract: Methods are provided to improve the adhesive bonding of a semiconductor die to a substrate through an adhesive paste by forming a layer of silicon dioxide on the back surface of the semiconductor die prior to applying the adhesive paste. Contacting the semiconductor die with ozone, in a gas mixture or in a mixture with water provides rapid oxidation of the silicon layer at the back of the semiconductor die to a silicon dioxide layer of at least 10 angstroms thick, which is sufficient to greatly improve bonding to the adhesive. The formation of a silicon dioxide surface layer prior to application of the adhesive is particularly beneficial when combined with rapid, snap curing processes, where the adhesive can be reliably cured by heating the semiconductor die for less than about 1 minute.

Abstract: The present invention relates to a method for connecting an integrated circuit chip to a circuit substrate. The method includes the step of pre-applying adhesive directly to a bumped side of an integrated circuit chip. The method also includes the steps of removing portions of the adhesive from the tips of the solder bumps to expose a contact surface, and pressing the bumped side of the integrated circuit chip, which has previously been coated with adhesive, against the circuit substrate such that the bumps provide an electrical connection between the integrated circuit chip and the circuit substrate. The adhesive is removed from the tips of the solder bumps using a solvent assisted wiping action. The pre-applied adhesive on the chip forms a bond between the integrated circuit chip and the circuit substrate.

Abstract: A laminated radiation member includes a radiation plate, an insulation substrate bonded to the upper surface of the radiation plate and an electrode provided on the upper surface of the insulation substrate. The laminated radiation member is made by a method including the steps of surface treating a bonding surface of the radiation plate and/or the insulation substrate, interposing ceramic particles surface treated to assure wettability with a hard solder or a metal between the radiation plate and the insulation substrate, disposing a hard solder above and/or below the ceramic particles, heating the hard solder to a temperature higher than the melting point of the solder, penetrating the molten hard solder into spaces between the ceramic particles to react the ceramic particles with the solder to produce a metal base composite material, and bonding the radiation plate and the insulation substrate with the metal base composite material.

Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.

Abstract: Numerous embodiments of an apparatus and method to stress and warpage of semiconductor packages are described. In one embodiment, a semiconductor die is disposed above a substrate. An encapsulating material is disposed above the substrate and semiconductor die, in which the encapsulating material has a combination of a low coefficient of thermal expansion material and a high coefficient of thermal expansion material.

Abstract: Circuits under electrode terminals and a nonconductor layer of the electrode terminals in semiconductor devices are prevented from being damaged during a test, such as a burn-in test, on the semiconductor devices formed on a wafer. Alignment patterns provided on the semiconductor wafer have detector electrode terminals and conductor electrode terminals. A detector electrode terminal surrounds a conductor electrode terminal separated by a gap from the detector electrode terminals and a portion of the surrounding detector electrode terminal is open.

Abstract: An apparatus for brushing a surface of a substrate is provided. The apparatus includes a brush for scrubbing the surface of the substrate, a head for holding the brush, and an arm. The arm is configured to hold the head about a connection point. The arm is connected to an oscillating mechanism configured to cause the head to oscillate at an angle of rotation about the connection point.

Abstract: A cogeneration system includes an engine, a generator connected to an output shaft of the engine to generate electricity, a heat pump type air conditioner, which uses the electricity generated from the generator, and includes a compressor, a directional valve, an outdoor heat exchanger, an expansion device, and an indoor heat exchanger, a fluid-heating heat exchanger to heat a fluid, and a waste heat recovering means to supply waste heat of the engine to the heat pump type air conditioner or to the fluid-heating heat exchanger, so that the system exhibits a high energy efficiency.

Abstract: A system for transmitting data and/or energy between a chassis and a seat that is movably arranged on the chassis, the seat being able to glide with the aid of slides in guide rails attached to the chassis; one iron-core half of a transformer, the iron-core half bearing at least one primary winding is positioned on the slide gliding in the guide rail, the primary winding being a cable in the guide rail; and the other iron-core half of the transformer, having a secondary winding, is positioned on the seat, the two limbs of the other iron-core half being arranged in the longitudinal direction with respect to the guide rail, and both iron-core halves of the transformer being positioned relative to each other for the data and/or energy transmission.