Abstract: A circuit arrangement for connection of at least two local coils of a magnetic resonance apparatus with at least two evaluation units has at least two sheath wave barriers arranged so that magnetic fields caused by them substantially cancel one another.

Abstract: A new application of electromagnetic tomography is described directly related to the efficient recovery of oil and gas as well the removal of unwanted liquids from subsurface formations. The process involves the deployment of both surface and a single borehole magnetic dipole structures used for both transmitting and receiving low frequency electromagnetic energy. The surface antenna consists of circularly concentric arrays of small receiving solenoid antennas and the downhole system consists of one or more solenoid antenna in a single borehole. The concentricity of the surface array is centered about or in proximity to the borehole axis. The electromagnetic field radiated by the downhole antenna is received by each surface antenna. The amplitude and phase of voltages and currents received by each surface antenna is electronically processed based on the theoretical processing principles similar to what has been recently established for electromagnetic impedance tomography (EMIT).

Abstract: The invention relates to a resistor arrangement, especially for current measurement in a vehicle electrical system, with two plate-shaped connection elements separated from each other and a plate-shaped first resistive element, which is arranged between the two connection elements and is electrically and mechanically connected to these elements. According to the invention, at least one of the other plate-shaped resistive elements, which are separated from the first resistive element and which are arranged between one of the two connection elements of the first resistive element and another connection element is connected electrically and mechanically to these connection elements.

Abstract: A loop impedance meter for testing an A.C. electrical mains supply, including an electronic control circuit for connecting a load resistance intermittently between the A.C. mains supply terminal and the earth terminal to measure the potential difference between those terminals and to provide an indication of the loop impedance of the A.C. mains supply from that potential difference, wherein the control circuit is arranged to allow a train of short pulses of current to flow through the load resistance and the loop, the pulse train beginning its sequence with a first train of pulses for preconditioning any residual circuit device (RCD) present in the loop to temporarily desensitize it, wherein the first train of pulses is followed by one or more measurement pulses, the pulses of the first train being of generally increasing width.

Abstract: A method and a measurement system determine a transmission response of a device under test (DUT). The method includes measuring a reflection response from a first port of the DUT while a known reflective termination is on a second port of the DUT, and time gating the measured reflection response to produce a gated reflection response that is the transmission response of the DUT. The measurement system includes a vector network analyzer, a controller, a memory and a computer program. The computer program includes instructions that implement measuring the reflection response from the first port of the DUT, and further implement time gating the measured reflection response. The time gating isolates reflection data associated with the known reflective termination from the measured reflection response.

Abstract: In one embodiment, a method for testing continuity of electrical paths through a circuit assembly includes: 1) mating a test-facilitating circuit package to a connector of the circuit assembly; the circuit package having a plurality of contacts for mating to a plurality of contacts of the connector; the circuit package containing incomplete or no mission circuitry for the circuit assembly, but containing a plurality of passive circuit components coupled in parallel between the package's plurality of contacts and a test sensor port of the circuit package; 2) stimulating one or more nodes of the circuit assembly; 3) measuring an electrical characteristic of the circuit package; and 4) comparing the measured electrical characteristic to at least one threshold to assess continuities of at least two electrical paths through the circuit assembly. Other embodiments are also disclosed.

Abstract: A system, method and program product for adjusting an environmental variable of a fuse blow of an electronic fuse are disclosed. A mimic NFET is coupled to a fuse blow source voltage line, a fuse blow gate voltage line, and a chip ground in the same manner as the electronic fuse, except that the mimic NFET is not attached to a poly fuse link. The on current (ion) and off current (ioff) of the mimic NFET are measured to determine a blow current of the electronic fuse. The environmental variable is adjusted based on the determined blow current.

Abstract: An apparatus and method for detecting a defect on a ground layer of microstrip by using scattering parameters is disclosed. The apparatus includes: a providing unit for providing a signal to the microstrip by changing a frequency of the signal in a predetermined range of frequencies; a detecting unit for detecting scattering parameters of an output signal from the microstrip in response to the frequency of the signal; and an analyzing unit for analyzing the interface based on the scattering parameters.

Abstract: A touch sensing apparatus includes a signal source for generating an alternating current signal, a conductor connected to the signal source, a sensor for receiving a noise generated by a contact of an object. The sensor together with the conductor form a simulated capacitor that results in alternating current signal flowing through the sensor when the sensor is contacted by the object. A detector has a first input end and a second input end. The detector results in voltage differences between the first and second input ends thereof when receiving the alternating current signal output from the sensor, and thus output a signal. A rectifying circuit is used for rectifying the alternating current signal generated by the signal source and simultaneously generating a noise. One end of the rectifier circuit is connected to the signal source and other end of the rectifier circuit is connected to the negative power input end of the detector.

Abstract: A capacitive soil moisture sensor that is easy to install, does not require complex calibration, can sense moisture at a particular depth, can accommodate soils of different composition, does not alter soil densities, provides fast response to changes in moisture and provides stable long term use. The sensor comprising of a body (10) onto which is attached a plurality of first electrode (20) and a plurality of second electrode (30). A plurality of protective layer (50) of low dielectric constant material is applied over the electrodes and against the body (10) to provide a physical barrier to prevent a conduction path from the first electrode (20) to the second electrode (30) and to provide protection against physical damage. The first and second electrodes (20), (30), once inserted into the soil, forms a capacitor with the soil as the dielectric. A change in soil moisture causes the capacitance of the sensor to change.

Abstract: A sensor (20) includes a single capacitor (30) that operates in two different modes to obtain capacitance and conductance information when a mixture flows between the electrodes (32, 34) of the capacitor. Two different oscillators (180, 182) are selectively used to obtain the conductance and capacitance information. In a disclosed embodiment, a capacitor includes an outer electrode (32) that is received around an inner electrode (34) such that there is spacing between the electrodes through which the mixture flows. The mixture acts as a dielectric of the capacitor allowing the conductance and capacitance measurements to be made. A glass member (36) seals off the spacing between the electrodes and provides physical support to position the inner electrode to keep the electrodes electrically isolated.

Abstract: Microelectronic components are commonly tested with probe cards. Certain aspects of probes, probe cards, and methods of testing microelectronic components are discussed herein. In one specific example, a probe card includes a base and a probe carried by the base. An actuator is associated with the probe and is adapted to selectively position the probe with respect to an electrical contact on the microelectronic component. A test power circuit is coupled to the first probe and adapted to deliver test power to the first probe. In one exemplary method, an actuator is actuated to move the probe from a first probe arrangement to a second probe arrangement.

Abstract: A probe apparatus and method of terminating a probe that probes a semiconductor device with a signal cable from a tester side by side at a proximal end of the probe and a distal end of the signal cable. In one embodiment, the probe apparatus includes: a chassis; a dielectric block mounted in the chassis for retaining the probe, the probe extending on the chassis from a proximal end of the probe to the dielectric block, extending through the dielectric block, and projecting from the dielectric block towards the semiconductor device at a distal end of the probe; and a terminating apparatus, mounted in the chassis, for terminating the proximal end of the probe with a distal end of the signal cable side by side.

Abstract: One embodiment of the present invention is a method for fabricating a structure useful for testing circuits that includes steps of: (a) aligning a first side of a connector-holder comprised of electrical connectors having retractable ends that are extendable out of the first side of the connector-holder and having retractable ends that are extendable out of a second side of the connector-holder with a substrate; and (b) connecting ends extendable out of the first side to pads on the substrate to form the structure.

Abstract: A system and method of mitigating the effects of component deflections in a probe card analyzer system may implement three-dimensional comparative optical metrology techniques to model deflection characteristics. An exemplary system and method combine non-bussed electrical planarity measurements with fast optical planarity measurements to produce “effectively loaded” planarity measurements.

Abstract: The present invention optimizes the performance of integrated circuits by adjusting the circuit operating voltage using feedback on process/product parameters. To determine a desired value for the operating voltage of an integrated circuit, a preferred embodiment provides for on-wafer probing of one or more reference circuit structures to measure at least one electrical or operational parameter of the one or more reference circuit structures; determining an adjusted value for the operating voltage based on the measured parameter; and establishing the adjusted value as the desired value for the operating voltage. The reference circuit structures may comprise process control monitor structures or structures in other integrated circuits fabricated in the same production run. In an alternative embodiment, the one or more parameters are directly measured from the integrated circuit whose operating voltage is being adjusted.

Abstract: A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit.

Abstract: A test system and method for integrated circuits includes an energy source having an adjustable energy rate, and a feedback device, which measures a physical quantity at a discrete position on an integrated circuit. A control circuit adjusts the power source to externally apply energy to the integrated circuit at the discrete position. A circuit tester applies test programs to the integrated circuit while the discrete position is maintained at a value of the physical quantity in accordance with the control circuit.

Abstract: The present invention provides a testing method for LCD panels. First, a plurality of panels are formed on a substrate. Each panel has first conducting lines and second conducting lines, which are perpendicular to each other. The first conducting lines and the second conducting lines of adjacent panels are electrically connected, respectively. Finally, all panels on the substrate are simultaneously tested by a testing circuit.

Abstract: Systems and methods for reducing variations in the timing of signal transitions which may result from interference with neighboring signal lines by adjusting the drivability of in-line buffers based upon the hostile/friendly condition of the neighboring lines. In one embodiment, a first inverter includes selectable current paths between the buffer output and Vdd/ground. A higher current is selected for one path and a lower current is selected for the other path so that the buffer output will be pulled more strongly in the direction (Vdd/ground) to which the neighboring signals may be hostile. In one embodiment, each selectable current path includes a plurality of parallel transistors, one of which is always switched on and the others of which are switched on or off according to the friendly/hostile states of the neighboring signals.

Abstract: Disclosed is a device for calibrating termination voltage of an on-die termination. The device for calibrating termination voltage of an on-die termination for a semiconductor memory device having a DLL device, comprises an on-die termination enable signal generating part for outputting an ODT enable signal for driving the on-die termination (ODT) when a signal DLL Reset EMRS is applied, a counter circuit of for outputting a plurality of counter signals, an on-die termination (ODT) including a variable resistor part controlled by the counter signals outputted from the counter circuit and outputting a variable termination voltage according to a resistance value of the variable resistor part, and a first control part for comparing a reference voltage with the termination voltage and outputting a control signal for controlling the counter circuit according to a comparison result.

Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Abstract: A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array.

Abstract: Sum bit generation circuit includes first logic generating first signal as XOR of first and second input signals and second signal as the inverse of XOR of the first and second input signals; second logic receiving the first and second signals generated by first logic and generating an output signal as XOR of first signal and third input signal. Second logic includes at least two pass gates. First gate terminal of the first pass gate receives third input signal. A second gate terminal of the first pass gate receives the inverse of third input signal. First gate terminal of the second pass gate receives the inverse of the third input signal. Second gate terminal of the second pass gate receives the third input signal. Input terminals of the first and second pass gates receive the first signal and the second signal respectively. Pass gate output terminals generate the output signal.

Abstract: An impedance controller includes a current mirror section to generate an impedance current. At least one detector includes a transistor array and an impedance corresponding to the impedance current, the at least one detector operating responsive to a code generator. And an at least one code generator generates a first code to adjust a gate voltage of the transistor array by comparing an output of the at least one detector to a reference voltage and generates a second code to adjust a size of the transistor array by comparing the output from the at least one detector to the reference voltage.

Abstract: A method and an apparatus to reduce duty cycle distortion are described. The apparatus may include a first current-mode logic (CML) circuit block comprising a positive input and a negative input and a second CML circuit block coupled in series to the first CML circuit block. The second CML circuit block may comprise a positive output, a negative output and a first transistor coupled between the positive input and the positive output. The second transistor may be coupled between the negative input and the negative output of the second CML circuit block.

Abstract: A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage. A pull up device restores the dynamic stage to a precharged condition, the pull up device controlled by a second clock signal independent of the first clock signal.

Abstract: A gate drive circuit capable of providing both positive and negative drive from a DC power supply is presented. The circuit includes an isolator stage, a driver stage, an optional tuning stage, an offset stage, a shaping stage, and a switching stage, each electrically coupled in the order described. The isolator stage provides electrical isolation from signal level circuitry. The driver stage boosts the power within the signal from the isolator stage. The tuning stage slows rising and falling edges along the signal from driver. The offset stage shifts the unipolar gate drive signal from the tuning stage into the negative voltage range. The shaping stage modifies the signal from the offset stage so as to ensure squared transitions. The switching stage enables voltage control. The described circuit is applicable to electronics utilizing a variety of voltage controlled switching devices.

Abstract: A system and method for reducing a transient response in a phase lock loop (PLL) (100) is disclosed. The system includes an adapt mode charge pump (204), a normal mode charge pump (206) and the use of controlled trickle currents (208), (210) applied to those charge pumps to minimize a transient response of the PLL (100).

Abstract: We describe and claim a delay locked loop harmonic detector and associated method. A delay locked loop includes a detection circuit to generate a detection signal responsive to an input clock and a control circuit to synchronize the delay locked loop to a fundamental of the input clock responsive to the detection signal. A method includes detecting harmonic synchronization in a delay locked loop responsive to an input clock and locking the delay locked loop to a fundamental of the input clock responsive to the detecting.

Abstract: A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.

Abstract: Provided is directed to a circuit of controlling a pulse width and a method of controlling the same, which can remove failure possible to be generated during operations of a DRAM or a DDR in a high frequency by guaranteeing read and write operations of a stabilized data and a precharging time of a local input/output line, in response to identically adjust widths of a pulse synchronized with a clock and a target pulse, by means of comprising: a pulse comparator for comparing a target pulse with a pulse synchronized with a clock; a counter pulse generation circuit for generating a counter pulse according to an output of the comparator; a pulse counter circuit for outputting a plurality of pulse counter signals, sequentially, according to the counter pulse; and a pulse delay circuit for controlling the pulse width synchronized with the clock according to the plurality of pulse counter signals.

Abstract: A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having its gate terminal coupled to an inverted delayed control signal. A first and second pull down transistors are coupled in series between the first pull up transistor and a low voltage bias, wherein the gates of the first and second pull down transistors are coupled to the delayed control signal and inverted control signal, respectively. A third and fourth pull down transistors are coupled in series between the second pull up transistor and the low voltage bias. The gates of the third and fourth pull down transistors are coupled to a control signal and the inverted delayed control signal, respectively.

Abstract: In embodiments, a data-retention circuitry comprises data-retention inverters in a feedback loop, an isolation subcircuit to isolate the inverters from a pass-gate subcircuit in response to a sleep signal, and a supply-switching subcircuit to provide current to the data-retention inverters from a supplemental voltage supply through a well tap during a standby mode. The supply-switching subcircuit switches from a regular voltage supply to the supplemental voltage supply in response to the sleep signal.

Abstract: A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.

Abstract: A hysteresis current comparator includes a first current comparison unit, a second current comparison unit, and a control circuit connected to the two current comparison units. The first current comparison unit compares a first reference current with an input current and outputs a first voltage accordingly. The second current comparison unit compares a second reference current with the input current and outputs a second voltage accordingly. The control circuit generates an output voltage according to the voltages output by the two current comparison units, or generates an output voltage according to the voltages output by the two current comparison units and the output voltage of the control circuit at a former state.

Abstract: An input voltage is applied to an inverting input terminal of a comparator having no hysteresis. A first constant voltage is divided by resistors to create a reference voltage. The reference voltage is applied to a non-inverting input terminal of the comparator through a resistor. Only while an output voltage of the comparator is a low level, a predetermined constant current is supplied to a supply point of the reference voltage and a constant current of the same magnitude is absorbed from the non-inverting input terminal of the comparator.

Abstract: A delay circuit comprising a delay line to delay an input signal that has a plurality of delay cells connected in series; a PLL circuit that supplies the delay line with a delay control voltage to control the delay; and a first selector that selects one of output signals of the delay cells. Each of the delay cells comprises two stages of delay inverters connected in series and an output inverter connected to a connection point of the delay inverter of the first stage and the delay inverter of the second stage. Input into the delay inverter of the first stage is an output signal of the delay inverter of the second stage in the preceding delay cell, and the first selector outputs as a delayed signal an output signal of the output inverter or the delay inverter of the second stage in one of the delay cells.

Abstract: Reference signal generators are provided that automatically adjusts a reference signal's amplitude when that signal is delivered into system loads having unknown capacitances. The amplitude is preferably initiated at a maximum amplitude to insure operation of system elements that require the reference signal. It is subsequently adjusted downward to a controlled reference amplitude which is predetermined to be an amplitude sufficient to sustain proper operation of the system elements but sufficiently reduced to minimize the spurious signals typically generated by fast high-level current transitions. In addition, the reduction to the controlled amplitude reduces the system current drain. The level control is realized in a buffer amplifier so that the amplitude level of an oscillator signal can be set independently to maximize its signal-to-noise performance. Accordingly, requirements for the reference amplitude do not compromise requirements for the amplitude level of the oscillator signal.

Abstract: A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.

Abstract: A switched current temperature sensing circuit comprises a BJT arranged to conduct a forced emitter current IE of the form Ifixed+(Ifixed/?), such that the base current is given by Ifixed/? and the collector current is given by Ifixed+(Ifixed/?)?(Ifixed/?)=Ifixed. Base current Ifixed/? is mirrored to the emitter, and a current source provides current Ifixed, which is switched between at least a first value I and a second value N*I such that the BJT's base-emitter voltage has a first value Vbe1 when Ifixed=I and a second value Vbe2 when Ifixed=N*I, such that: ?Vbe12=Vbe1?Vbe2=(nFkT/q)(ln N), where nF is the BJT's emission coefficient, k is Boltzmann's constant, T is absolute temperature, and q is the electron charge.

Abstract: A driver circuit for driving a light source of an optical pointing device includes a first transistor coupled to the light source. The driver circuit includes a controller coupled to the first transistor for monitoring a first current through the light source, comparing the first current to a reference current, and generating a control signal based on a result of the comparison, wherein the control signal causes the first transistor to change the first current.

Abstract: A low voltage bandgap reference circuit based on a current summation technique where reference voltages with positive and negative temperature coefficients are generated by a first circuit. These reference voltages are coupled to amplifying circuits which generate reference voltages with equal and opposite temperature coefficients based on the ratio of resistors in these amplifying circuits, thereby producing a temperature independent reference voltage. The current from each of these amplifying circuits is then summed in a summing resistor, where the size of the resistor determines the magnitude of the temperature independent reference voltage.

Abstract: A low voltage wide ratio current mirror circuit comprises an n times current mirror having an input port for receiving an input current and an m times current mirror coupled in series to the n times current mirror for resulting in an output current of (N*M the input current) being provided to a load where at least one of N and M is other than 1. The circuit provides precision in output current for use with a low voltage power amplifier without incurring an overhead of quiescent current. The low voltage wide ratio current mirror circuit in accordance with a second embodiment of the invention includes a voltage swing reduction circuit in order to provide increased stability thereto. In additional embodiments of the invention, the load is a differential amplification stage for providing differential amplification to differential RF input signals received at first and second RF input ports thereof.

Abstract: An amplifier including a current source transistor for supplying a current to a node from a voltage rail and an input transistor switching the current at the node in response to an input signal chopped by a chopping signal. A cascode-chopping transistor operating both as a cascode transistor and a chopping transistor couples the node and an amplifier output in response to a bias voltage chopped by the chopping signal.

Abstract: To provide a digital amplifier advantageously performing volume adjustment over a wide range. A first and second field effect transistors include N-channel type field effect transistors. The first field effect transistor has the drain connected to the operation voltage Vreg, the source connected to the drain of the second field effect transistor and the gate to which the first input signal is applied from the first level shifter for on/off operation. The second field effect transistor has the source connected to the ground potential as the reference voltage and the gate to which the second input signal is applied from the second level shifter for on/off operation.

Abstract: A class D power amplifier is provided to drive a low impedance load for audio applications. The amplifier includes a sigma-delta modulator circuit including three or more integrators that are arranged for third or higher order sigma-delta modulation. Also, the sigma-delta modulator circuit includes a quantizer circuit that is arranged to provide a sigma-delta modulator output signal based on a three-level switching scheme. The class D power amplifier drives a speaker based on the three-level switching scheme so that the output switches between three levels: VDD, 0, and ?VDD, based on the input signal.

Abstract: A power amplification circuit (10) includes a scalable power amplifier (20) to produce an RF output signal (50) at an output of the power amplification circuit (10), and a variable impedance circuit (30) coupled to the output of the power amplification circuit (10). The scalable power amplifier (20) includes a plurality of selectively activated amplifier elements (22), (24), (26) to produce the RF output signal (50) in accordance with a desired RF output signal power level. The power amplification circuit (10) selectively activates individual amplifier elements by, for example reducing power or increasing power to at least one amplifier element. The variable impedance circuit (30) varies an impedance of the variable impedance circuit (30) to dynamically load the output of the scalable power amplifier (20).

Abstract: A combined signal of a digital pilot signal and a digital transmission signal is applied to a digital predistorter (20), wherein it is added with odd-order distortions based on a power series model to generate a predistorted signal, then the predistorted signal is converted by a DA converter (31) to an analog signal, then the analog signal is upconverted by a frequency upconverting part (33) to a send frequency band, and the upconverted signal is output after being amplified by a power amplifier (37). A pilot signal component is extracted from the power amplifier output, then odd-order distortion components of the power series model are extracted by a digital predistorter control part (50) from the pilot signal component, and the odd-order distortions in the digital predistorter (20) are controlled to decrease the levels of the distortion components.