Abstract: After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.

Abstract: A capacitor structure which has generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the at least one dielectric layer. The second conductive layer has a second area which is less than the first area of the at least one dielectric layer. A method of fabricating a capacitor structure is also disclosed.

Abstract: A method of forming an SOI semiconductor substrate and the SOI semiconductor substrate formed thereby, is provided. The method includes forming sequentially buried oxide, diffusion barrier and SOI layers on a semiconductor substrate. The diffusion barrier layer is formed by an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer. The diffusion barrier layer serves to prevent impurities implanted into the SOI layer from being diffused into the buried oxide layer or the semiconductor substrate.

Abstract: A method for forming an isolation film of a semiconductor device is disclosed which includes forming trenches in a semiconductor substrate, forming a first HDP oxide film in the formed trenches, performing an etch-back process using a mixing gas of C2F6 gas and O2 gas to form vertical walls in the first HDP oxide films and forming a second HDP oxide film on the resulting structure. The characteristics of a device can be improved because diffusion of F ions in a FSG film formed on the first HDP oxide film is minimized.

Abstract: A flash memory device and method of manufacturing the same. The flash memory device includes a semiconductor substrate in which a first region where a cell region is formed, a second region where a peripheral region is formed, and a third region formed in the peripheral region at the boundary portion of the cell region and the peripheral region. The device also includes a triple well region formed in the first region and a predetermined region of the third region, an isolation film formed in the first region and having a first depth, an isolation film formed in the second region and having a second depth, which is deeper than the first depth of the isolation film, and a gate oxide film for low voltage and a floating gate, which are stacked on a predetermined region of the first region, a gate oxide film and a gate, which are stacked on a predetermined region of the second region.

Abstract: A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

Abstract: A wafer is provided having through-holes therein to form a through-hole via wafer. A substrate of a sacrificial wafer is provided. The substrate is coated with a polymer having low adhesion to metals. A conductive layer is deposited on the polymer. A photoresist layer is coated on the conductive layer. The through-hole via wafer is bonded to the sacrificial wafer wherein the photoresist layer provides the bonding. The photoresist exposed in the through-holes is developed away to expose the conductive layer. The through-holes are filled with a conductive material by electroplating the conductive layer. The photoresist is stripped in an ultrasonic bath wherein the photoresist separates from the through-hole wafer and wherein the filled through-holes separate from the polymer at an interface between the polymer and the conductive layer to complete separation of the through-hole via wafer from the sacrificial wafer.

Abstract: A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, includes forming an oxide layer on at least a first surface of a first one of the wafers and performing a bonding enhancement implantation step by ion implantation of a first species in the first surface of at least either of the pair of wafers. The method further includes performing a cleavage ion implantation step on one of the pair of wafers by ion implanting a second species to define a cleavage plane across a diameter of the wafer at the predetermined depth below the top surface of the one wafer. The wafers are then bonded together by placing the first surfaces of the pair of wafers onto one another so as to form an semiconductor-on-insulator structure.

Abstract: A method of manufacturing a semiconductor wafer wherein a film is formed on a back surface of a starting semiconductor wafer formed with circuits in a front surface thereof.

Abstract: A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting H in the Si substrate, forming a cleaving plane (peak concentration (Rp) H layer) in the Si substrate about as deep as the gettering regions; bonding the circuit to a receiver substrate; cleaving the Si substrate along the cleaving plane; and binding the implanted H underlying the S/D regions with p-dopant in the gettering regions, as a result of post-bond annealing.

Abstract: A method of simultaneously fabricating at least two semiconductor devices, at least one of which is a nanocrystal memory and at least one of which is a non-nonocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semiconductor devices being fabricated. The nanocrystal layer is removed from at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated. A polycrystalline gate is formed for each of the semiconductor devices being fabricated. Doping is provided to provide the source and drain regions for each of the semiconductor devices being fabricated. The substrate is thermally treated after the doping. The thermal budget of the fabrication process is not limited by this thermal treatment.

Abstract: A method of removing an edge bead of a coated material on a substrate. The substrate is rotated, and a fluid that solvates the coated material is delivered. The delivery of the fluid is directed radially inward on the substrate at a rate of between about three millimeters per second and about twenty millimeters per second until a desired innermost fluid delivery position on the substrate is attained. Immediately upon attaining the desired innermost fluid delivery position on the substrate, the delivery of the fluid is directed radially outward off the substrate at a rate of more than zero millimeters per second and less than about four millimeters per second. The rotation of the substrate is ceased.

Abstract: A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.

Abstract: A method for forming a mechanically strengthened feature in a low-k dielectric film on a substrate includes using either spin-on-dielectric (SOD) techniques, or chemical vapor deposition (CVD) techniques to form a low-k dielectric film on the substrate. A sidewall of the feature in the low-k dielectric film is then treated in order to increase the film's mechanical strength. Treatment of the sidewall of the feature in the low-k dielectric film comprises forming a hardened layer by subjecting the low-k dielectric film to low energy, high flux ion implantation. Process parameters of the ion implantation are selected such that the implantation process does not cause a substantial change in the dielectric constant of the low-k dielectric film.

Abstract: A method for making a semiconductor device is described. That method comprises forming a hard mask and an etch stop layer on a patterned sacrificial gate electrode layer. After first and second spacers are formed on opposite sides of that patterned sacrificial layer, the patterned sacrificial layer is removed to generate a trench that is positioned between the first and second spacers. At least part of the trench is filled with a metal layer.

Abstract: The invention includes a method of forming a transistor gate. One or more conductive materials are formed over a semiconductor substrate, and a block is formed over the one or more conductive materials. The block comprises a photoresist mass and a material other than photoresist which is against the photoresist. A pattern is transferred from the block to the one or more conductive materials to pattern a transistor gate construction from the one or more conductive materials.

Abstract: After pulsing the second purging gas, a zirconium-containing precursor is pulsed into reaction chamber 220, at block 430. In an embodiment, the zirconium-containing precursor is ZTB. In other embodiments, a zirconium-containing precursor includes but is not limited to ZrCl4 and ZrI4. The ZTB precursor is pulsed into reaction chamber 220 through the gas-distribution fixture 240 on substrate 210. Mass-flow controller 258 regulates the flow of the ZTB from gas source 253. In an embodiment, the substrate temperature is maintained at about 200° C. The ZTB aggressively reacts at the current surface of substrate 210.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, includes forming a polysilicon gate electrode (250) over a substrate (210) and forming source/drain regions (610) in the substrate (210) proximate the polysilicon gate electrode (250). The method further includes forming a protective layer (710) over the source/drain regions (610) and the polysilicon gate electrode (250), then removing the protective layer (710) from over a top surface of the polysilicon gate electrode (250) while leaving the protective layer (710) over the source/drain regions (250). After the protective layer (710) has been removed from over the top surface of the polysilicon gate electrode (250), the polysilicon gate electrode (250) is silicided to form a silicided gate electrode (1310).

Abstract: The invention provides a method for fabricating contact-making connections, having the steps of: a) providing a substrate (101) with electronic circuit units (102a, 102b) arranged thereon, an intermediate layer (103) filling an interspace between the electronic circuit units (102a, 102b); an insulation layer (104) being deposited on the electronic circuit units (102a, 102b) and on the intermediate layer (103); a masking layer (105) being deposited on the insulation layer (104); and the masking layer (105) being patterned with a through-plating structure (106); b) patterning a contact-making region by means of the masking layer (105), a contact-making hole (112) being etched through the insulation layer (104) and the intermediate layer (103) as far as the substrate (101), a section of the substrate (101) being uncovered in accordance with the through-plating structure (106); c) filling the contact-making hole (112) with a through-plating material (108); d) polishing back the covering layer (107) deposited on t

Abstract: A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device (150) has a semiconductor chip provided with electrodes (158), a resin layer (152) forming a stress relieving layer provided on the semiconductor chip, wiring (154) formed from the electrodes (158) to over the resin layer (152), and solder balls (157) formed on the wiring (154) over the resin layer (152); the resin layer (152) is formed so as to have a depression (152a) in the surface, and the wiring (154) is formed so as to pass over the depression (152a).

Abstract: A method of efficiently and inexpensively fabricating a chip-size package having an electrode pitch expanded by forming a conductor wiring on the electrode forming surface side of a semiconductor chip, especially, a method for facilitating wiring and bump forming. A semiconductor device comprising a semi-conductor elements and conductor wirings formed on the semiconductor elements by etching wiring-forming metal foil; and a fabrication method for a semiconductor device comprising the steps of laminating wiring forming metal foil on the electrode forming surface side on the semiconductor, forming a resist wiring pattern on the metal foil, etching the metal foil, and slicing the device into individual elements.

Abstract: Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.

Abstract: A passivation layer pattern having an opening is formed on a substrate having a metal wiring pattern formed thereon. The opening partially exposes an upper surface of the metal wiring pattern. A photoresist pattern is formed on the passivation layer pattern. The photoresist pattern has an opening that exposes the opening of the passivation layer pattern, and metal is electroplated in the openings to form a bump electrode. The photoresist pattern is removed using a composition including monoethanolamine and dimethylacetamide.

Abstract: A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in the substrate after providing the active and passive areas, and oxidizing the plurality of slots. The method further comprises providing metal in each of the plurality of slots, providing a dielectric coating over the slots, and providing etched contacts in select areas remote from the location of the slots. Additionally, the method provides an additional layer of metal that interconnects the contacts and the buried metal in select areas where contacts were etched, resulting in metal of three levels; and provides one level of the metal is surface and two levels of the metal that comprise a buried power buss (BPB).

Abstract: In a socket used to house semiconductor die during testing, a recessed socket contact and methods of making the same are provided that avoid pinching the die's contacts. Semiconductor fabrication techniques are used to construct a dense array of contacts by forming a plurality of interconnected silicon electric contacts on a substrate having a first side and a second side, each silicon electric contact having a portion connected to the first side of the substrate and a portion extending from the first side of the substrate, applying an alignment-preserving material to the second side of the substrate having the plurality of interconnected silicon electric contacts formed on the side thereof, and disconnecting the plurality of interconnected silicon electric contacts from having electrical connection therebetween.

Abstract: A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.

Abstract: A multilayer interconnection board is disclosed that allows reliable electrical connection between an interconnection having a large width and a large area and a via provided in a via hole formed by pressing a tool against resin. A projecting portion for electrical connection is formed integrally with the insulating member and in a second interconnection groove having a width and an area greater than those of a first interconnection groove. While a first interconnection is being deposited in the first interconnection groove and a second interconnection is being deposited in the second interconnection groove, the projecting portion is formed in the second interconnection groove and a metal plating film is provided on the projecting portion at the same time, so as to electrically connect the second interconnection with the via.

Abstract: A method and apparatus for depositing a material layer onto a substrate is described. The method includes delivering a mixture of precursors for the material layer into a process chamber and depositing the material layer on the substrate at low temperature. The material layer can be used as an encapsulating layer for various display applications which require low temperature deposition process due to thermal instability of underlying materials used. In one aspect, the encapsulating layer includes one or more material layers (multilayer) having one or more barrier layer materials and one or more low-dielectric constant materials. The encapsulating layer thus deposited provides reduced surface roughness, improved water-barrier performance, reduce thermal stress, good step coverage, and can be applied to many substrate types and many substrate sizes. Accordingly, the encapsulating layer thus deposited provides good device lifetime for various display devices, such as OLED devices.

Abstract: A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.

Abstract: A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

Abstract: A semiconductor device has a multi-layer interconnection structure with a first interlayer insulation film and a second interlayer insulation film that is formed on the first interlayer insulation film and has a hardness and an elastic modulus larger than those of the first interlayer insulation film, and is fabricated by a step of forming a resist film on the second interlayer insulation film via an antireflective film, a step of exposing to light and developing the resist film to form a resist pattern, and a step of patterning the antireflective film and the multi-layer interconnection structure using the resist pattern as a mask, wherein a film with no stress or for storing compressive stress is used as the antireflective film.

Abstract: A method of selectively etching organosilicate layers in integrated circuit fabrication processes is disclosed. The organosilicate layers are selectively etched using a hydrogen-containing fluorocarbon gas. The hydrogen-containing fluorocarbon gas may be used to selectively etch an organosilicate layer formed on a silicon oxide stop etch layer when fabricating a damascene structure.

Abstract: A method of forming metal wiring in a semiconductor device is disclosed. The method uses a dual damascene process in which a trench is formed prior to a via-hole.

Abstract: A method of forming a copper oxide film including forming a copper oxide film including an ammonia complex by causing a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 8 to 10 or pH of 9 to 10, to contact a surface of a copper film. A method of fabricating a semiconductor device including burying a copper film to be a wiring or a contact wiring in a wiring groove or a contact hole formed in a surface of an insulating film formed on a semiconductor substrate, or in both the wiring groove and the contact hole, forming a copper oxide film including an ammonia complex on a surface of the copper film by using the copper oxide film forming method, and removing the copper oxide film from the copper film using acid or alkali.

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an NMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the NMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the NMOS transistor is enhanced.

Abstract: Roughly described, a patterned first layer is provided over a second layer which is formed over a substrate. In a conversion process, first layer material is consumed at feature sidewalls to form third layer material at the feature sidewalls. The width of third layer material at each of the sidewalls is greater than the width of first layer material consumed at the respective sidewall in the conversion process. The second layer is patterned using the third layer material as mask. A fourth layer of material is formed over the substrate, and planarized or otherwise partially removed so as to expose the top surfaces of the features in the first layer through the fourth layer. The exposed first layer material is removed to expose portions of the second layer through the fourth layer, and the second layer is further patterned using the fourth layer material as a mask.

Abstract: Fabrication of microelectronic devices is accomplished using a substrate having a recessed pattern. In one approach, a master form is used to replicate a substrate having a pit pattern. In another approach, the substrate is produced by etching. A series of stacked layers having desired electrical characteristics is applied to the substrate and planarized in a manner that creates electrical devices and connections therebetween. The microelectronic devices can include a series of row and columns and are used to store data at their intersection.

Abstract: CVD metallization processes and CVD apparatus used therein are provided. The processes include forming a barrier metal layer on a semiconductor substrate and cooling the semiconductor substrate having the barrier metal layer without breaking vacuum. An additional metal layer may be formed on the cooled barrier metal layer. The in-situ cooling process is preferably performed inside a cooling chamber installed between first and second transfer chambers, which are separated from each other. The barrier metal layer may be formed inside a CVD process chamber attached to the first transfer chamber, and the additional metal layer may be formed inside another CVD process chamber attached to the second transfer chamber.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: The semiconductor device fabrication method of the present invention includes forming metal wirings on a semiconductor substrate, forming a first blocking layer on the semiconductor substrate and the metal wiring, forming a first FSG on the first blocking layer, forming a second blocking layer on the first FSG, forming a second FSG on the second blocking layer, and forming a protection layer on the second FSG.

Abstract: A large-size substrate having improved flatness is prepared by measuring the flatness of one surface or opposite surfaces of a large-size substrate having a diagonal length of at least 500 mm, and partially removing raised portions on the one surface or opposite surfaces of the substrate by means of a processing tool on the basis of the measured data. The processing tool is adapted to blast a slurry of microparticulates in water carried on compressed air against the substrate.

Abstract: The object of the present invention is to provide a process for chemical mechanical polishing of semiconductor substrate that is particularly useful for chemical mechanical polishing a wafer having a wiring pattern and an insulating layer having a low dielectric constant is formed between wiring patterns, interlayers in the case of a multi-layer wiring and the like in the process of producing a semiconductor device, and an aqueous dispersion for chemical mechanical polishing which is used in this process.

Abstract: Described is a polishing technique adapted for multilevel metallization of an electronic circuit device, which comprises polishing a metal film with a polishing liquid containing an oxidizing substance, a phosphoric acid and a protection-layer forming agent. The present invention makes it possible to polishing a metal film at a high removal rate while suppressing occurrence of scratches, delamination, dishing or erosion.

Abstract: A chemical mechanical polishing pad. The pad contains a water-insoluble matrix and Water-soluble particles dispersed in the water-insoluble matrix material and has a polishing surface and a non-polishing surface on a side opposite to the polishing surface. The pad has a light transmitting area which optically communicates from the polishing surface to the non-polishing surface. The non-polishing surface of the light transmitting area has a surface roughness (Ra) of 10 pm or less.

Abstract: In one embodiment, a semiconductor substrate is placed into a process chamber. A gas mixture including a silicon-containing gas, a fluorine-containing gas, an inert gas, and an oxygen gas is introduced into the chamber at a pressure range of from about 30 mTorr to about 90 mTorr. During this time, deposition and etching processes are concurrently performed using a plasma to form a high-density plasma (HDP) insulating layer on the semiconductor substrate. A ratio of deposition to etching is from about 3:1 to about 10:1. A ratio of a flow rate of the fluorine-containing gas to a flow rate of the silicon-containing gas is less than about 0.9.

Abstract: A technique comprises directing a plasma having at least first and second gasses at a substrate. The substrate is at least partially covered with at least the first and second layers. Ions of the first gas are electrostatically attracted towards the substrate. The second gas selectively etches the first layer relative to the second layer.

Abstract: A thermal oxidation process is used to fill trenches with an oxide; however, the oxidation process consumes some of the silicon. The embodiments herein advantageously apply this tendency for the oxidation process to consume silicon so as to convert all the silicon substrate material between the multiple trenches into an oxide. Therefore, because all of the silicon between the multiple trenches is consumed by the oxidation process, the multiple smaller trenches are combined into a single larger trench filled with the oxide.

Abstract: A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas containing at least Cl2 and HBr. Trenches 104a, 104b are formed, as shown in FIG. 1B, in a silicon wafer 101 shown in FIG. 1A through a mask layer such as a nitride silicon layer 103. While adjusting the high-frequency power supplied to the opposed electrode where the wafer is placed, the shape of the sidewalls 105a, 105b of the trenches 104a, 104b is controlled. Thus, the trenches can have desired shapes even if the widths of the trenches are different.

Abstract: The present invention relates to a fabrication method of a semiconductor device using EPD system, which enables uniform hole etching regardless of changes of etch rates of etching chemical and thickness of interlayer insulating layer after CMP, and the fabrication method comprises: forming a nitride layer on an interlayer insulating layer; forming a photoresist layer on the nitride layer, and exposing and developing the photoresist layer to form a photoresist pattern; etching the nitride layer using the photoresist pattern as a mask and contiguously etching the photoresist pattern and the interlayer insulating layer together; setting etch stop point as the point that the photoresist pattern is removed by etching and thus the nitride layer is exposed.

Abstract: An SiO2 film layer formed at a wafer placed inside a process chamber of an etching device is etched by generating plasma from a process gas containing fluorocarbon which has been introduced into the process chamber. The contents of an etchant and the byproducts are measured through infrared laser absorption analysis. The individual contents thus measured are compared with the contents of the etchant and the byproducts in the plasma corresponding to the increase in the aspect ratio of a contact hole set in advance. The quantity of O2 added into the process gas is adjusted to match the measured contents with the predetermined contents. The quantity of O2 added into the process gas is continuously increased as the aspect ratio becomes higher. As a result, a contact hole is formed at the SiO2 film layer without damaging the photoresist film layer or inducing an etch stop.