Abstract: A structure and a method for forming the same. The structure includes an integrated circuit comprising N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit. The structure further includes N solder bumps corresponding to the N chip electric pads. A semiconductor interposing shield is sandwiched between the integrated circuit and the N solder bumps. The structure further includes N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.

Abstract: A structure and method (1000) of forming an interface for a ball grid array includes forming pad (204), (1002) on a substrate (202) and creating a positive feature (206) on the pad (1004). The positive feature (206) provides an interface for a solder ball (208). The improved pad can be incorporated as part of BGA substrate or as part of a printed circuit board substrate. The positive feature (206) provides a contoured or uneven profile having vertical surfaces that increase the pad's surface area without taking up additional substrate space. The vertical surface area interrupts propagation of any fracture incurred during drop and vibration.

Abstract: A semiconductor package for surface mounting has a substrate having electrode patterns formed on both its surfaces which are electrically connected through passages such as throughholes formed through the substrate, all of these electrode patterns having a metal film formed by an electrolytic plating process. Semiconductor chips are wire-bonded onto one its surfaces (mounting surface) which is sealed with a resin layer. Lead-in wires each with one end exposed externally are included only those of the electrode patterns on the back surface of the substrate opposite its mounting surface such that the mounting surface has no lead-in wires with a part exposed externally.

Abstract: The invention is characterized in a printed wiring board having a wiring pattern including a pad for mounting a solder ball as a connection terminal, wherein the pad is constituted by laminating a conductive layer constituting the wiring pattern, a lower layer plating layer, and an upper layer plating layer in this order; an immediate vicinity region surrounding the pad is constituted by laminating the conductive layer, at least the lower layer plating layer in the lower layer plating layer and the higher layer plating layer, and a solder resist layer in the order; a thickness of the upper layer plating layer is a thickness negligible in comparison with respective thicknesses of the lower layer plating layer and the upper layer plating layer; and a height of an upper face of the pad does not exceed a height of an upper face of the immediate vicinity region.

Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.

Abstract: The channel of a MOSFET is selectively stressed by selectively stressing the silicide layers on the gate electrode and the source/drain. Stress in the silicide layer is selectively produced by orienting the larger dimensions of the silicide grains in a first direction and the smaller dimensions in a second, perpendicular direction, with one of the directions being parallel to the direction of carrier movement in the channel and the other direction being perpendicular thereto.

Abstract: A method is provided for designing an integrated circuit having an interconnect structure with a reduced lateral dimension relative to a pre-existing interconnect structure layout. The method begins by reducing in scale by a desired amount the lateral dimension of a given level of metallization in the pre-existing interconnect structure layout by reducing the width of each conductive line in the given level of metallization to a prescribed width. The conductive lines are separated by dielectric material. The given level of metallization in the interconnect structure layout is divided into at least first and second levels of metallization by arranging in the second level of metallization alternating lines from the given level. The prescribed width in the lateral direction of each line is increased in the first and second levels of metallization by a factor of at least two.

Abstract: An interlayer insulating film having a concave portion is formed on a semiconductor substrate. A tight adhesion film is formed on the inner surface of the concave portion and the upper surface of the insulating film. The surface of the adhesion layer is covered with an auxiliary film made of Cu alloy containing a first metal element. A conductive member containing a second metal element other than the first metal element is embedded in the concave portion, and deposited on the auxiliary film. Heat treatment is performed to make atoms of the first metal element in the auxiliary film segregate on the inner surface of the concave portion. The adhesion layer contains an element for enhancing tight adhesion of the auxiliary film more than if the auxiliary film is deposited directly on a surface of the interlayer insulating film.

Abstract: A method of forming an insulating layer and a method of manufacturing a semiconductor device using insulating layer are disclosed. A preliminary insulating layer including a material having a relatively low dielectric constant is formed on an object. An upper portion of the preliminary insulating layer is provided with an ozone gas to transform the preliminary insulating layer into an insulating layer having an upper insulating film including an oxide and a lower insulating film including the material having the relatively low dielectric constant. The upper insulating film may further be located on the lower insulating film.

Abstract: Provided is a method for forming a metal line. According to the method, a silicon carbide (SiC) layer is formed on a semiconductor substrate, a silicon oxide layer is formed on the silicon carbide layer, the silicon oxide layer including an alkyl group, and a via hole and a trench are formed by removing a portion of the silicon oxide layer. Subsequently, a diffusion barrier is formed on remaining portions of the silicon oxide layer, a copper seed layer is formed on the diffusion barrier, and a copper metal layer is formed on the copper seed layer using electroplating.

Abstract: A semiconductor memory device includes a titanium layer and a titanium nitride layer formed on a substrate, a thin layer formed on the titanium nitride layer, and a metal layer formed on the thin layer, wherein the thin layer increases a grain size of the metal layer.

Abstract: A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

Abstract: Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are methods for CVD deposition of MxAlyNzBw alloy diffusion barriers, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W; x is greater than zero; y is greater than or equal to zero; the sum of z and w is greater than zero; and wherein when y is zero, z and w are both greater than zero.

Abstract: Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. The vias are formed within the substrate to have a longitudinal axis sloped at an angle with respect to a reference line extending perpendicular to the first surface and the second surface of the substrate. The vias may be formed from the first surface to the opposing second surface, or the via may be formed as a first blind opening from the first surface, then a second opening may be formed from the second surface to be aligned with the first opening. Vias may be formed completely through a first substrate and a second substrate, and the substrates may be bonded together. Semiconductor devices including the vias of the present invention are also disclosed. A method of forming spring-like contacts is also disclosed.

Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to at least an intermediate depth in a substrate of a workpiece. The hole has a first lateral dimension in the dielectric layer and a second lateral dimension in the substrate proximate to an interface between the dielectric layer and the substrate. The second lateral dimension is greater than the first lateral dimension. The method further includes constructing an electrically conductive interconnect in at least a portion of the hole and in electrical contact with the terminal.

Abstract: A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate opening. The electrode of the semiconductor chip is electrically connected to the connecting pattern via wires through the elongate opening. The elongate opening and the wires are sealed with resin.

Abstract: The semiconductor device comprises one layer including interconnections 32a to 32d formed above a substrate 10, and an insulation layer 34 formed over said one layer, a cavity 40 being included in said one layer. The dummy interconnection is removed by etching, whereby the layer can be planarized while the parasitic capacitance between the interconnections can be made small. Furthermore, the dielectric constant of the air in the cavity is much smaller than that of the inter-layer insulation film, whereby in comparison with the parasitic constant of the case where the inter-layer insulation film are formed simply between interconnections, the parasitic constant between the interconnections of the present invention can be made smaller.

Abstract: A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a first SiOCH layer, a second SiOCH layer formed on the first SiOCH layer, and a silicon dioxide (SiO2) layer formed on the second SiOCH layer. The second SiOCH layer features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer, and an oxygen (O) density higher than that of the first SiOCH layer.

Abstract: Stacked microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such microelectronic device can include a support member and a first known good microelectronic die attached to the support member. The first die includes an active side, a back side opposite the active side, a first terminal at the active side, and integrated circuitry electrically coupled to the first terminal. The first die also includes a first redistribution structure at the active side of the first die. The microelectronic device can also include a second known good microelectronic die attached to the first die in a stacked configuration such that a back side of the second die is facing the support member and an active side of the second die faces away from the support member. The second die includes a second redistribution structure at the active side of the second die.

Abstract: A packaging process including the following steps is provided. First, a first substrate and a second substrate are provided. The first substrate has first contacts, and the second substrate has second contacts. Next, the first substrate is placed on the second substrate, such that the first contacts are aligned with the second contacts. Then, the first substrate and the second substrate are submerged in a solution having BDMT. After that, the first substrate and the second substrate are removed from the solution, such that self-assembly mono-layers are formed between the first substrate and the second substrate, to electrically connect the first substrate and the second substrate. A package structure formed according to the above process is also provided.

Abstract: A semiconductor device includes a package substrate having a chip mounting surface with at least a plurality of first substrate-side pads and a plurality of second substrate-side pads, a rectangular first semiconductor chip having a first main surface fixed on the chip mounting surface, a plurality of first bonding wires through which a plurality of first pads arranged along one side of a second main surface of the first semiconductor chip and the first substrate-side pads are bonded to each other, a rectangular second semiconductor chip having a third main surface fixed on the second main surface, and a plurality of second bonding wires through which a plurality of second pads arranged along one side of a fourth main surface of the second semiconductor chip and the second substrate-side pads are bonded to each other.

Abstract: Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In one embodiment, a method includes constructing a dielectric structure on a microfeature workpiece having a substrate and a terminal carried by the substrate, and removing a section of the dielectric structure to form an opening. The opening has a first portion extending through the dielectric structure and exposing the terminal and a second portion extending to an intermediate depth in the dielectric structure. The second portion is spaced laterally apart from the terminal. The method further includes forming a conductive layer on the microfeature workpiece with the conductive layer in electrical contact with the terminal and disposed in the first and second portions of the opening.

Abstract: There is disclosed a process of forming reinforcements baffles and seals having malleable carriers. The process typically includes application of an activatable material to a malleable carrier and contouring of the activatable material the malleable carrier or both.

Abstract: A board 1 according to the present invention includes a board main body 3; electronic parts 5 electrically connected to and mounted on the board main body 3; and an under-fill material 19 with which a part between the board main body 3 and a surface of the electronic parts 5 electrically connected to the board main body is filled. A hole 21 passing through a layer 19a of the under-fill material that flows outside from a connecting area of the electronic parts 5 and the board main body 3 is provided for electrically connecting other parts to the board main body.

Abstract: A LSI package encompasses: an interposer having board-connecting joints, which facilitate connection with a printed wiring board, and module-connecting terminals, part of the module-connecting terminals are assigned as interposer-site monitoring terminals; a signal processing LSI mounted on the interposer; and an I/F module having a plurality of interposer-connecting terminals, which are arranged to correspond to arrangement of the module-connecting terminals, and a transmission line to establish an external interconnection of signal, which is transmitted from the signal processing LSI, part of the interposer-connecting terminals are assigned as module-site monitoring terminals. The interposer-site and module-site monitoring terminals are configured to flow a monitoring current to confirm electric contact between the signal processing LSI and the I/F module.

Abstract: A chip package includes a chip, a carrier, and at least a bump connecting structure for connecting the chip to the carrier. The bump connecting structure includes a first metal bump disposed on a chip pad of the chip and has a first height relative to a passivation layer of the chip, a second metal bump disposed on a carrier pad of the carrier and has a second height relative to a solder mask layer of the carrier, and a middle metal part disposed between the first and the second metal bumps. The sum of the minimum distance between the first and the second metal bumps, the first height of the first metal bump, and the second height of the second metal bump is less than 60 micrometers. The melting point of the middle metal part is lower than that of the first and the second metal bumps.

Abstract: A semiconductor device includes: a semiconductor chip connected onto a surface of a printed wiring board in a flip-chip connection; a dam for preventing an outflow of underfill, the dam being provided on the surface of the printed wiring board and surrounding an entire circumference of the semiconductor chip; an external connection terminal for the semiconductor chip, the external connection terminal being provided on the surface of the printed wiring board and arranged outside the dam; a solder resist layer covering the surface of the printed wiring board except for portions for the flip-chip connection and the external connection terminal arrangement; and at least one recess portion being provided in the solder resist layer and within a region between a corner portion of the semiconductor chip and a corner portion of the dam being opposed to the corner portion of the semiconductor chip.

Abstract: A pad open structure, after an insulation layer is installed at the up of the pad, the insulation layer forms plural pad opens by lithography. The insulation layer is exposed to the surface of the pad by the pad opens. The gold bump forms the upper part of the insulation layer, which forms an electric connection through the pad opens to the pad. By way of this, when the gold bump is formed at the surface of the pad opens and the surrounding insulation layer, reducing the affection produced by a single pad open that hollows the surface of the gold bump such that the gold bump has an extra flat surface.

Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.

Abstract: A semiconductor memory card comprises a wiring substrate having input-output terminals for inputting and outputting a signal formed on its topside; a semiconductor memory chip connected to pads formed on a topside or an underside of the wiring substrate; wirings for plating for supplying electric power necessary for electrolytic plating, formed on the wiring substrate and cut at a side edge portion thereof; and a sealing resin for sealing the semiconductor memory chip on the wiring substrate and sealing the side edge portion of the wiring substrate and an end of at least one of the wirings for plating.

Abstract: Improved lithographic type microelectronic spring structures and methods are disclosed, for providing improved tip height over a substrate, an improved elastic range, increased strength and reliability, and increased spring rates. The improved structures are suitable for being formed from a single integrated layer (or series of layers) deposited over a molded sacrificial substrate, thus avoiding multiple stepped lithographic layers and reducing manufacturing costs. In particular, lithographic structures that are contoured in the z-direction are disclosed, for achieving the foregoing improvements. For example, structures having a U-shaped cross-section, a V-shaped cross-section, and/or one or more ribs running along a length of the spring are disclosed. The present invention additionally provides a lithographic type spring contact that is corrugated to increase its effective length and elastic range and to reduce its footprint over a substrate, and springs which are contoured in plan view.

Abstract: Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.

Abstract: The present invention provides a semiconductor device and a fabrication method therefor, the semiconductor device including a first semiconductor chip (20) disposed on a substrate (10), a first sealing resin (26) sealing the first semiconductor chip (20), a built-in semiconductor device (30) disposed on the first sealing resin (26), and a second sealing resin (36) sealing the first sealing resin (26) and the built-in semiconductor device (30) and covering a side surface (S) of the substrate (10). According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefor, in which downsizing and cost reduction can be realized.

Abstract: A method for forming an alignment mark comprises forming an etch stop film and an interlayer insulating film over a semiconductor substrate including a cell region and a scribe region, etching a predetermined region of the interlayer insulating film and the etch stop film to form a storage node region in the cell region and an alignment mark region in the scribe region, forming a layer for storage node over an entire surface of the resultant including the storage node region in the cell region and the alignment mark region in the scribe region, etching the layer for storage node until the interlayer insulting film is exposed, and removing the interlayer insulating film to form a capacitor in the cell region and an alignment mark in the scribe region.

Abstract: A carburetor has a housing with intake channel section. A throttle element and a choke element are arranged in the intake channel section and are adjustable between a closed position in which a flow cross-section of the intake channel is substantially closed and an open position in which the flow cross-section of the intake channel is substantially released. The choke element has a start position in which the flow cross-section of the intake channel is at least partially closed. A coupling device couples the throttle element to the choke element when the choke element is in the start position. The choke element has an enriching position. The coupling device has an actuator that moves the choke element into the enriching position when the throttle element is moved, starting from the start positions of the throttle element and of the choke element, toward the open throttle position of the throttle element.

Abstract: A cooling tower fill support grid assembly and method of use which includes multiple cooling tower assembly fill hangers, each having a grid pattern that defines multiple grid openings of selected size. In one embodiment an anchor rivet pin extends from the horizontal grid members upwardly and disproportionally spaced-apart from the vertical grid members, into each grid opening. The anchor rivet pins are located off-center on the horizontal grid members between respective vertical grid members for engaging elliptical splash fills that are inserted in the aligned grid openings of adjacent assembly fill hangers in a first configuration. Once so inserted, the elliptical splash fills are rotated ninety-degrees into contact and engagement with the anchor rivet pins in a second, installed configuration.

Abstract: Evaporative cooling is an effective and efficient method for rapidly removing heat from a system device. In accordance with the disclosure herein, a microfluidic Y-junction apparatus is provided which can produce low temperatures and can be integrated into microdevices.

Abstract: The air humidifier 2,976,026 needs to add water every half hour, while this new air humidifier only needs to add water every 24 hours, and this addition is made by hands (is made manually). In this new air humidifier the heater element is no longer in the tray elements but rather in the chamber C. The chamber C no longer consists of one cavity but of two cavities. One of these cavities is larger than the other and has water and the heater element inside it. The other cavity houses the blower.

Abstract: Double mold opto-coupler and method for manufacture. A first subassembly is formed that includes that includes a light detector. The first subassembly is molded with a first mold material to form a molded first subassembly. A light source is attached to the molded first sub-assembly to form a second sub-assembly. The second sub-assembly is molded with a second mold material to form a final assembly with predetermined dimensions.

Abstract: The disclosure is directed to techniques to transfer data information to optical disks. A stamper is formed by registering a disk-shaped stamper substrate to a master through a common centering pin. A resin ring is added to the inner edge of the master to be sandwiched between the disk-shaped stamper substrate and the master. Spinning the assembly at high speeds forces the resin to form a uniform layer between each disk, thus forming an inverse surface pattern on the disk-shaped stamper substrate. Once ultraviolet light passes through the transparent disk-shaped stamper substrate to cure the resin, the stamper can be removed from the master and used to form readable, or correct, surface patterns in data layers for optical disks. Concentrically registered stampers may be used to create optical disks with two or more layers without the need to optically register the center of the data layer after formation.

Abstract: Products, especially masses and shaped parts with fire-resistant (refractory) qualities when used in an authorized application, are used in particular in devices for receiving, treating and/or transporting melts. Such melts can be steel melts (ferrous melts), non-ferrous melts (such as copper melts) as well as glass melts or rock melts, whereby such melts customarily have temperatures between 1000° C. and 2000° C. According to the invention these refractory products are used to amend the corresponding melt.

Abstract: The present invention enables an automatic roll gap adjustment, thereby facilitating operations at a set-up or when changing forming conditions. Specifically, one embodiment of the present invention controls a sheet take-off speed (a roll rotation speed) in accordance with a deviation of a measurement value from a set value of a roll gap under a constant pressing load control.

Abstract: This invention relates to extruded composite materials specifically focusing on the increasing load bearing capacity and the overall strength of composites. Injectable conformable structural core materials are used to replace foam cells inside extruded composite materials thereby increasing the overall load bearing stability and strength. The core materials are tailored to have a desired CTE with respect to the structural materials. The core materials may also incorporate fibers and solid structural fillers for increasing the strength of the composite member. The objective is to enable composite materials to have the highest structural load bearing capability possible so that these technologies can be used as the replacement of wood, in aerospace applications and for other purposes.

Abstract: A process to effect random color variation in multi-color molded articles includes feeding individual colors to molding equipment in a pre-established sequence and manner that prevents substantial mixing of the colors, and at pre-established ratios in relation to a non-integer multiple of the volume associated with the molded article.

Abstract: Disclosed is a method of making a light-reflecting article comprising: mixing a polymer with a high-pressure gas or a supercritical fluid in an extruder to create a homogeneous single-phase mixture; and extruding the homogeneous single-phase mixture through a die to form an extrudate, wherein the resultant extrudate contains a polymer foam having micro voids with a mean cell diameter of no more than 200 ?m.

Abstract: It is an object to provide the manufacturing method for the friction material (4) which maintains the quality of the friction material (4) and reduces the cost of the facilities and the maintenance cost. The manufacturing method for a friction material (4) comprising a molding step of the friction material (4) as pressurizing and heating a molding material made of a raw friction material within a molding die with an upper die (1), a middle die (2), and a lower die (3), wherein a temperature of the upper die (1) and the lower die (3) in said molding step is 190° C.-230° C. and a pressure thereof is 0.05 MP-10 MP.

Abstract: Highly compactable granulations and methods for preparing highly compactable granulations are disclosed. More particularly, highly compactable calcium carbonate granulations are disclosed. The granulations comprise powdered materials such as calcium carbonate that have small median particle sizes. The disclosed granulations are useful in pharmaceutical and nutraceutical tableting and provide smaller tablet sizes upon compression than previously available.

Abstract: A composition and method of infiltrating an article of manufacture prepared by a laser sintering process is disclosed. The infiltration process maintains the dimensions and flexibility of the article, increases the strength of the article, and improves the physical and esthetic properties of the article.

Abstract: The invention provides a board forming system comprising a forming table comprising a belt with a surface for conveying a backing layer; a mixer fitted with a mechanism capable of depositing cementitious slurry material over a top surface of the backing layer; and a slurry spreader positioned downstream of the mixer, wherein a portion of the slurry spreader comprises a plurality of apertures which are connected to a source of pressurized fluid. The slurry spreader is configured such that the pressurized fluid flows out of the slurry spreader through the apertures so as to provide a continuous film of fluid across an outer surface of the slurry spreader. The slurry spreader is positioned such that it can contact at least a portion of the cementitious slurry after the slurry exits the discharge and before the slurry is spread across the width of the backing layer such that the thickness of the slurry is approximately equal to the desired slurry thickness for board formation.

Abstract: A method of forming a multilayer film is disclosed, comprising coextruding a first layer comprising a weatherable composition, and a second layer comprising a polycarbonate composition comprising a visual effect filler, wherein the first and second layers are formed by flowing each of the weatherable composition and polycarbonate composition through separate flow channels in a multi-manifold coextrusion die. The shear stress during extrusion on the polycarbonate composition is greater than or equal to 40 kilo-Pascals.