Abstract: A buried photodiode with shallow trench isolation technology is formed in a semiconductor substrate of a first conductive type. A trench having a bottom portion and a sidewall portion is formed in the semiconductor substrate. An isolation region is formed on the bottom portion of the trench. A gate structure covers the sidewall portion of the trench. A first doped region of a second conductive type is formed in the semiconductor substrate adjacent to the trench and the gate structure. A second doped region of the first conductive type is formed overlying the first doped region near the surface of the semiconductor substrate.

Abstract: A MEMS package (100, 300) and method of fabrication include a package (100, 300) that is formed by bonding a first component (102, 302), which includes a MEMS device (106, 306) and a substrate (104, 304) upon which the MEMS device (106, 306) was formed as a part thereof, to a second component (202, 402) during wafer level packaging. The first component (102, 302) is bonded to the second component (202, 402) using bump bonding or coined wire bonding. The MEMS device (106, 306) resides in a sealed cavity (250, 350) defined by a collar structure (252, 352) formed by the two components (101, 202, 302, 402). The collar structure (252, 352) provides a sealed airspace in which the MEMS device (106, 306) resides and operates.

Abstract: Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Abstract: Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a microelectronic device that includes a microfeature workpiece having a side and an aperture in the side. The device can further include a workpiece contact having a surface. At least a portion of the surface of the workpiece contact can be accessible through the aperture and through a passageway extending between the aperture and the surface. Other aspects of the invention are directed toward a microelectronic support device that includes a support member having a side carrying a support contact that can be connectable to a workpiece contact of a microfeature workpiece. The device can further include recessed support contact means carried by the support member. The recessed support contact means can be connectable to a second workpiece contact of the microfeature workpiece.

Abstract: In a semiconductor package, a semiconductor chip is mounted on a wiring board or package board. A lid member defines a recess for accommodating the semiconductor chip, and is mounted on the package board so that the semiconductor chip is accommodated in the recess of the lid member. A first adhesive layer is formed on the package portion so that a peripheral portion of the lid member is adhered on the package board with the first adhesive layer. A second adhesive layer is formed on the semiconductor chip so that a central portion of the lid member is adhered to the semiconductor chip with the second adhesive layer. The following relationship is established: 25 ?m?h?d?300 ?m where: “h” is a depth of the recess of the lid member; and “d” is a sum of a thickness of the semiconductor chip and a thickness of the second adhesive layer.

Abstract: A method of processing a wafer having a plurality of streets formed on the front surface in a lattice pattern and a plurality of devices formed in a plurality of areas sectioned by the plurality of streets, comprising an adhesive tape amounting step for mounting the front surface of the outer peripheral portion of an adhesive tape having an adhesive layer on the front surface and a plurality of via holes onto an opening of an annular frame to cover it; a frame fixing step for placing the rear surface of the adhesive tape mounted on the annular frame on the chuck table for suction-holding a workpiece of a processing machine and fixing the annular frame; a wafer affixing step for placing the wafer on the front surface of the wafer affixing area of the adhesive tape, suction-holding the adhesive tape on the suction-holding area of the chuck table by exerting suction-force to the suction-holding area, and sucking the wafer to affix it to the front surface of the adhesive tape; and a processing step for processing

Abstract: An opto-coupler and a process for fabricating an opto-coupler are disclosed. The opto-coupler includes at least one light-emitting diode and a photodiode for galvanically isolating electric circuits. The optical components are mounted in a yielding material, such as silicone rubber, in a housing. The interior walls are coated with a pigmented yielding coating which includes TiO2 to enhance light reflection inside the housing and increase the current transfer efficiency of the device. The opto-coupler has a high dielectric breakdown voltage and is immune to radiation. The device can be employed in space applications.

Abstract: A circuit board includes a substrate having a heat exhausting function. A wiring layer of a metal composite material is provided on the substrate with an insulating layer in between. The metal composite material has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of a silicon semiconductor chip and less than a coefficient of thermal expansion of copper. Accordingly, a circuit board that is suitable for mounting power devices, requires no heat sink or heat spreader is provides. Further, the number of components for assembling a module is reduced.

Abstract: A semiconductor chip package has a pillar body including at least three conductors insulated from each other by an insulating layer. The pillar body has a periphery that includes a plurality of mounting faces, with each mounting face defined by two adjacent conductors separated by a portion of the insulating layer. A plurality of semiconductor chips are attached on the mounting faces and selectively and electrically connected to the conductors. The semiconductor package of the present invention can be used in a semiconductor illuminator which has a housing having a reflecting cup, with the pillar body positioned inside the reflecting cup.

Abstract: A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.

Abstract: A printed circuit board (PCB) with an improved thermal dissipating structure for a package substrate of a multi-package module (MPM). A first upper metal layer is on a substrate and corresponds to the package substrate. A second upper metal layer is on the substrate outside the package substrate. An inner metal layer is in the substrate. Pluralities of first and second heat conductive vias are in the substrate to thermally connect the inner metal layer to the first and second upper metal layers, respectively. An electronic device with an improved thermal dissipating structure is also disclosed.

Abstract: A semiconductor device which is excellent in chemical and physical strength and circumstance resistance is provided. A first stacked film including a first base material and a first adhesive layer is adhered so as to cover one surface of a stacked body including an integrated circuit, the stacked body is sealed by adhering a second stacked film including a second base material and a second adhesive layer so as to cover the other surface of the stacked body, and the first stacked film and the second stacked film are cut. Then, a side surface of the first stacked film and the second stacked film, which is exposed by the cutting, is irradiated with laser light.

Abstract: A structure of an ultra-thin wafer level stack package is provided. A method for manufacturing the structure includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method for manufacturing microelectronic devices includes forming a stand-off layer over a plurality of microelectronic dies on a microfeature workpiece, removing selected portions of the stand-off layer to form a plurality of stand-offs on corresponding dies, cutting the workpiece to singulate the dies, attaching a first singulated die to a support member, and coupling a second die to the stand-off on the first singulated die.

Abstract: A test carrier for a semiconductor component includes a base for retaining the component, and an interconnect on the base having contacts configured to electrically engage component contacts on the component. The base includes conductors in electrical communication with the contacts on the interconnect, which are defined by grooves in a conductive layer. In addition, the conductors include first portions of the conductive layer configured for electrical transmission, which are separated from one another by second portions of the conductive layer configured for no electrical transmission. The test carrier is configured for mounting to a burn in board in electrical communication with a test circuitry configured to apply test signals through the contacts on the interconnect to the component.

Abstract: A Quad Flat Pack (QFP) package which includes first and second dies arranged in a side-by-side orientation, and a power supply bus which protrudes between adjacent sides of the first and second dies and which supplies power to the adjacent sides via connections to the adjacent sides.

Abstract: A multichip sensor includes an element chip having a detection element of a sensor; a signal-processing IC chip having a signal-processing IC for processing an output signal of the detection element; and a package adapted to accommodate at least the element chip and the signal-processing IC chip and having a surface to be mounted on an ECU board. The plane of the element chip and the surface to be mounted on the ECU board are perpendicular to each other. The plane of the signal-processing IC chip, which is greater than the element chip, and the surface to be mounted on the ECU board are in parallel with each other.

Abstract: The laminated product in a structure including a glass-cloth contained resin layer according to this invention is a laminated product in which a wiring layer and an insulating layer alternately laminated are included and different wiring layers are electrically connected to each other by a via hole passing through the insulating layer, characterized in that at least one insulating layer 11 is formed of a laminated body including an insulating resin layer 7 on a lower wiring layer 5 and a glass-cloth contained resin layer 9 thereon, and in the laminated body, a via hole 17 continuously passes through from the upper glass-cloth contained resin layer 9 to the lower insulating resin layer 7.

Abstract: Microfeature assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One particular embodiment of a microfeature assembly includes a microelectronic die having integrated circuitry, a plurality of terminals electrically coupled to the integrated circuitry, and conductive bumps on the individual terminals. The conductive bumps include first engagement features. The assembly also includes a microfeature workpiece having a substrate and a plurality of pads on the substrate. The pads include non-planar second engagement features engaged with the first engagement features on corresponding conductive bumps.

Abstract: A printed circuit board (PCB) assembly includes a PCB. An integrated circuit (IC) carrier defines a receiving zone to receive an IC. The carrier has a plurality of island portions about the receiving zone. Each island portion includes a solder member for contacting the PCB. A plurality of resilient serpentine members interconnect neighboring island portions so that at least some relative displacement of the PCB and the carrier is accommodated by the serpentine member, thereby alleviating strain imparted to the solder member.

Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.

Abstract: A wiring board includes a substrate core, ceramic capacitors and a built-up layer. The substrate core has a housing opening portion therein which opens at a core main surface. The ceramic capacitors are accommodated in the housing opening portion and oriented such that the core main surface and a capacitor main surface of each capacitor face the same way. The built-up layer includes semiconductor integrated circuit element mounting areas at various locations on a surface thereof. In the substrate core, each ceramic capacitor is respectively disposed in an area corresponding to each semiconductor integrated circuit element mounting area.

Abstract: An electronic package and method for forming such package that expands the current capability of lines and/or reducing line resistance for packages with a given feature dimension while relaxing feature tolerances. The methods and structures include electrical wirings having regions of larger wire cross-sectional areas in locations where the package must supply higher current distribution to the electronic devices and/or where signal lines need lower electrical resistance. These larger wire cross-sectional areas are vertically extended conductors applied to either the entire conductor or portions of the conductor.

Abstract: An apparatus provides a memory having a transmission line circuit with an associated high permeability material. The high permeability material may include a layered structure of a nickel iron compound.

Abstract: A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. Terminal pads of the interposer substrate may be electrically connected to either or both of a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. Additional components, active, passive or both, may be connected to pads of the two-dimensional array to provide a system-in-a-package. Lead fingers of a lead frame may be superimposed on the opposing side of the interposer substrate, bonded directly to the land grid array land and wire bonded to pads as desired for repair or to ease routing problems on the interposer.

Abstract: A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of the die extends between the lid and the substrate, contains the thermal compound, and flexes in response to expansion and contraction of both the substrate and the lid during cycling of the semiconductor module. More particularly, either the barrier is formed of a flexible material or has a flexible connection to the substrate and/or to the lid. The barrier effectively contains the thermal compound between the die and the lid and, thereby, provides acceptable and controlled coverage of the thermal compound over the die for heat removal.

Abstract: A method for forming through hole vias in a substrate uses a partially exposed seed layer to plate the bottom of a blind trench formed in the front side of a substrate. Thereafter, the plating proceeds substantially uniformly from the bottom of the blind hole to the top. To form the through hole, the rear face of the substrate is ground or etched away to remove material up to and including the dead-end wall of the blind hole.

Abstract: A printed circuit board for inhibiting warpage is disclosed. The printed circuit board has a core layer, which is formed by an insulating material; a circuit pattern layer, which is formed in the upper part of the core layer and has a central area, in which a circuit pattern is formed, and a fringe, which surrounds the central area and is made of a material of high stiffness; an insulating layer, which is formed in the upper part of the circuit pattern layer; and a solder resist, which is formed in the upper part of the insulating layer. The printed circuit board with a dual type inner structure in accordance with the present invention has an effect of inhibiting warpage by having an inner structure in which the rim is made of a material that is hardly warped and a vertex in which the rim is shaped round.

Abstract: A packaging assembly (100) includes a plurality of dissimilar die (102, 104, 106) bonded to a base board (110) and ground coupled to a heat sink (108) through an opening (132). A mating board (112) is coupled to the base board (110) to provide separate surface mountable contacts (148-158, 166) with which to independently bias each die (102, 104, 106) while the heat sink (108) provides thermal dissipation for the die. Assembly (100) provides a surface mountable package well suited to multiband applications.

Abstract: A composition and method for die-level packaging of microelectronics is disclosed. The composition includes about 20% to about 80% of a thermoplastic base matrix; about 20% to about 70% of a non-metallic, thermally conductive material such that the composition has a coefficient of thermal expansion of less than 20 ppm/C and a thermal conductivity of greater than 1.0 W/mK. Using injection molding techniques, the composition can be molten and then injected into a die containing the microelectronics to encapsulate the microelectronics therein.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The first IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes a portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface.

Abstract: A supply voltage management system and method for an integrated circuit (IC) die are provided. The supply voltage management system includes one or more temperature sensing elements located on the IC die and configured to sense temperature of the die and to output a sensed temperature value for the die. A dynamic voltage controller is located on the die and is configured to receive the sensed temperature value for the die and to identify a technology process category of the die. Based on the sensed temperature value and the identified technology process category of the die, the dynamic voltage controller adjusts an output voltage to at least one circuit of the die.

Abstract: Microfeature workpiece substrates having through-substrate vias, and associated methods of formation are disclosed. A method in accordance with one embodiment for forming a support substrate for carrying microfeature dies includes exposing a support substrate to an electrolyte, with the support substrate having a first side with a first conductive layer, a second side opposite the first side with a second conductive layer, and a conductive path extending through the support substrate from the first conductive layer to the second conductive layer. The method can further include forming a bond pad at a bond site of the first conductive layer by disposing at least one conductive bond pad material at the bond site, wherein disposing the at least one conductive bond pad material can include passing an electrical current between the first and second conductive layers via the conductive path, while the substrate is exposed to the electrolyte.

Abstract: A semiconductor multi-chip package includes: a first semiconductor memory chip having n address pads, a first control pad, and a first address controller; and a second semiconductor memory chip whose memory density is greater, e.g., at least 1.5 times greater, than the first semiconductor memory chip and which is disposed on the first semiconductor memory chip, and has (n+1) address pads, a second control pad, and a second address controller. The n address pads of the first semiconductor memory chip and the n address pads of the second semiconductor memory chip are respectively connected to corresponding n address pins. The first and second control pads are connected to a control pin. The first and second address controllers are operable in a mutually exclusive manner, e.g., manner of activation, according to a signal applied to the control pin.

Abstract: Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

Abstract: In a flip chip semiconductor package, a substrate is provided. At least one chip is flip-bonded onto the substrate to electrically connect to a circuit pattern-printed on the substrate. A molded part is formed on the substrate so as to expose a backside ground of the chip. Also, a conductive metal layer is extended along an outer surface of the molded part to electrically connect to the backside ground. According to the invention, heat generated from the chip is released through the backside ground to improve heat releasing properties. Furthermore, the electrical ground is formed without creating a parasitic component to enhance electrical properties.

Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.

Abstract: A method and an apparatus for separating elongated semiconductor strips from a wafer of semiconductor material are disclosed. Vacuum is applied to the face of each semiconductor strip forming an edge of the wafer or being adjacent to the edge. The wafer and the source of the vacuum are displaced to separate each elongated semiconductor strip from the wafer. Further, a method and an apparatus for assembling elongated semiconductor strips separated from a wafer of semiconductor material into an array of strips are disclosed. Still further, methods, apparatuses, and systems for assembling an array of elongated semiconductor strips on a substrate are also disclosed.

Abstract: A connector layout for arranging a plurality of parallel electrical connectors between two electronic devices. Each connector has a strip connected to a bump pad. Each strip has a certain required strip width and each bump pad has a certain required pad width. Each bump pad on one electronic device is electrically connected to a corresponding bump pad on the other device by superimposition. The connectors are grouped into a group of three or more. Within each group, a strip is connected to a bump pad along one side edge thereof, and the bump pads are offset in two directions such that after the bump pads are superimposed, the pattern of the connected connectors in each group of connectors resembles a plurality of zigzag paths offset to maintain a constant gap between two strips. As such, the gap between two connectors can be minimized.

Abstract: A controlled collapse chip connection (C4) comprises a copper metal C4 bump formed on an integrated circuit substrate, where the C4 bump includes a metal barrier cap to prevent electromigration of the copper metal. The barrier cap is formed from nickel or cobalt and it can either be formed on a top surface of the C4 bump or it can encapsulate the C4 bump. A method of forming the C4 bump with the barrier cap comprises providing an integrated circuit substrate, depositing a photoresist layer on a top surface of the integrated circuit substrate, exposing and developing the photoresist layer to form an opening, depositing copper metal into the opening to form a C4 bump, plating a metal barrier layer onto a surface of the C4 bump, and stripping the photoresist layer.

Abstract: Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed herein. A method of manufacturing a substrate in accordance with one embodiment of the invention includes forming a conductive trace on a first side of a sheet of non-conductive material, and forming a via through the non-conductive material from a second side of the sheet to the conductive trace. The method further includes removing a section of the non-conductive material to form an edge of the non-conductive material extending across at least a portion of the via. In one embodiment, forming the edge across the via exposes at least a portion of the second conductive trace for subsequent attachment to a terminal on a microelectronic die.

Abstract: A chip package structure includes a substrate, a chip, a first B-stage adhesive, bonding wires, a heat sink and a molding compound. The substrate comprises a first surface, a second surface and a through hole. The chip is arranged on the first surface of the substrate and electrically connected thereto while the through hole of the substrate exposes a portion of the chip. The first B-stage adhesive is arranged between the chip and the first surface of the substrate, and the chip is attached to the substrate through the first B-stage adhesive. The bonding wires are connected between the chip exposed by the through hole and second surface of the substrate. The heat sink is arranged on the first surface of the substrate, covering the chip. The molding compound is arranged on the second surface of the substrate, covering a portion of the substrate and bonding wires.

Abstract: In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower chip and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete fill of the gap.

Abstract: A semiconductor device including: a semiconductor layer; an electrode pad provided above the semiconductor layer; an insulating layer provided above the electrode pad and having an opening which exposes at least part of the electrode pad; and a metal electrode provided at least in the opening and including a first portion provided above the electrode pad, and a second portion provided above part of the insulating layer positioned outside the electrode pad, an area of a top surface of the second portion being larger than an area of a top surface of the first portion.

Abstract: The invention includes solder materials having low concentrations of alpha particle emitters, and includes methods of purification of materials to reduce a concentration of alpha particle emitters within the materials. The invention includes methods of reducing alpha particle flux in various lead-containing and lead-free materials through purification of the materials. The invention also includes methods of estimating the fractionation of a low concentration of one or more alpha particle emitters during purification of a material.

Abstract: The invention includes solder materials having low concentrations of alpha particle emitters, and includes methods of purification of materials to reduce a concentration of alpha particle emitters within the materials. The invention includes methods of reducing alpha particle flux in various lead-containing and lead-free materials through purification of the materials. The invention also includes methods of estimating the fractionation of a low concentration of one or more alpha particle emitters during purification of a material.

Abstract: A circuit component and method by which degradation of a solder connection by electromigration can be prevented or reduced. The component generally includes an interconnect pad on a surface of the component, a metallic multilayer structure overlying the interconnect pad and having a solderable surface layer, and a solder material on the multilayer structure. According to a preferred aspect of the component and method, a stud is wire-bonded to the solderable surface layer of the multilayer structure and encased by the solder material to provide a low electrical resistance path through the solder material.

Abstract: A semiconductor chip and manufacturing method thereof, the semiconductor chip including a plurality of bumps connected to a driving circuit integrated on a semiconductor substrate and an organic insulating layer disposed on the driving circuit. The organic insulating layer extends from the semiconductor substrate less than the plurality of bumps such that a lower edge of the plurality of bumps protrudes further than a lower edge of the organic insulating layer.

Abstract: The invention includes solder materials having low concentrations of alpha particle emitters, and includes methods of purification of materials to reduce a concentration of alpha particle emitters within the materials. The invention includes methods of reducing alpha particle flux in various lead-containing and lead-free materials through purification of the materials. The invention also includes methods of estimating the fractionation of a low concentration of one or more alpha particle emitters during purification of a material.

Abstract: The present invention relates to a substrate for a Ball Grid Array device comprising a support element, a solder ball pad arranged on the support element and adapted to be applied by a solder bump, a bond pad arranged on the support element and adapted to be bonded by a bond wire and a silver layer provided on both the solder pad and the bond pad.