Abstract: Semiconductor integrated circuit apparatus capable of raising detection sensitivity of a leakage current detection circuit and improving response. A semiconductor integrated circuit apparatus has a substrate voltage control block that supplies a substrate voltage to an internal circuit and controls NchMOS transistor threshold voltage of the internal circuit, and a leakage current detection circuit constituted by a leakage current detection NchMOS transistor supplied with a high potential side supply voltage to a drain, that has a source connected to a constant current source, and that is applied with an arbitrary stabilizing potential to a gate in such a manner that the substrate voltage is controlled by the substrate voltage control block, and a comparator comparing the source potential of the leakage current detection NchMOS transistor and a predetermined reference potential.

Abstract: A power semiconductor device (1) has a semiconductor chip stack (4) and lines (5) within a housing (6). The lines electrically connect large-area contact regions (7) of power semiconductor device components (8) within the housing (6) to one another. In this case, at least one of the lines (5) has a large-area planar conductive layer (9). This planar conductive area (9) electrically connects the large-area contact regions (7) to one another.

Abstract: A semiconductor device 50 is constructed to connect Al electrode pads 20 and rewiring patterns 52 via through electrodes 56 and flip-chip connect the rewiring patterns 52 of a semiconductor element 14 and wiring patterns 24 on a wiring substrate 12 via solder bumps 58. A device forming layer 18 and a plurality of Al electrode pads 20 are formed on an upper surface of the semiconductor element 14. Through holes 54 passing through the semiconductor element 14 are provided between the Al electrode pads 20 and the rewiring patterns 52 by the dry etching, and through electrodes 56 are formed in insides of the through holes 54 by the Cu plating. The device forming layer 18 is arranged on an upper surface of the semiconductor element 14 to make a light reception and a light emission easily.

Abstract: Methods and apparatus are described that reduce the possibility that unintended subway short-circuits will occur between contacts of different potentials along the boundary between tensile and compressive liners (the T-C boundary). This may be done without unduly increasing the size of the semiconductor device, or even increasing the size at all over previous designs. For example, simply by adjusting the layout of the device, the contacts of two different common gates may be offset in opposing directions relative to the T-C boundary. Or, by forming a T-C boundary having a zigzag or other similar pattern, the contacts may be arranged even closer together while still reducing the likelihood of short-circuiting subways forming. Such layout adjustments do not otherwise require any additional steps or cost.

Abstract: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

Abstract: A metal oxide semiconductor transistor comprising a first doping type substrate, an isolation layer, a plurality of gates, a masking layer, a gate oxide layer, a plurality of second doping type source/drain regions and spacers. The first doping type substrate has a plurality of trenches patterning out a plurality of first doping type strips. The isolation layer is disposed within the trenches. The gates is disposed over the first doping type strips and oriented in a direction perpendicular to the first doping type strips. The masking layer is disposed over the first doping type substrate. The gate oxide layer is disposed between the sidewall of the first doping type strips and the gate. The second doping type source/drain regions are disposed in the first doping type strip on each side of the gate. The spacers are disposed on the sidewalls of the gates and the first doping type strips.

Abstract: The present invention provides a MOS transistor device for providing ESD protection comprising at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further comprises at least one isolation gate formed in at least one of the interleaved fingers. The device can further comprises a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.

Abstract: A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon gate, and source/drain regions for the transistor are formed using the sacrificial carbon sidewall spacers to define the source/drain regions. The sacrificial carbon sidewall spacers are replaced with non-carbon sidewall spacers, and the sacrificial carbon gate is replaced with a desired metal gate material to provide the desired metal gate material on the gate dielectric. Various embodiments form source/drain extensions after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier is used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers.

Abstract: A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 ? to 60 ?. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.

Abstract: A semiconductor device with a recessed L-shaped spacer and a method for fabricating the same. A recessed L-shaped spacer includes a vertical portion and a horizontal portion. The vertical portion is disposed on lower sidewalls of a conductor pattern, exposing upper sidewalls thereof. A top spacer is on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2:1.

Abstract: The invention relates to a single-chip gyro device, which includes a substrate, a plurality of metal layers and a plurality of dielectric layers, and a plurality of metal side walls. Each of the dielectric layers is located between two adjacent layers selected from a layer group consisting of the metal layers and the substrate. The metal side walls are located on edges of the plurality of dielectric layers so as to prevent the dielectric layers from being undercut and form a mechanical structure together with the metal layers and the dielectric layers to connect the circuit formed on the substrate.

Abstract: A nanoelectronic sensing device includes a substrate, a nanostructure element disposed adjacent the substrate, and at least a conductive element electrically connected to the nanostructure element. The device is configured to heat at least a portion of the sensor structure including the nanostructure element. In certain embodiments, the nanostructure element comprises at least one nanotube, the nanotube being electrically connected to at least two conductors so as to permit an electric current on the order of 10 microAmps or greater to be passed through the nanotube, causing the nanotube to heat up relative to the substrate. In alternative embodiments, the sensing device includes a platform or membrane which is at least partially thermally isolated by one or more cavities, the platform supporting at least the nanostructure element adjacent to a microheater element.

Abstract: A sensor capable of increasing an electric signal output therefrom by inhibiting an electrode plate from vibration is obtained. This sensor comprises a diaphragm provided in a vibrative manner, an electrode plate, opposed to the diaphragm at a prescribed distance, having a hole and a support made of a material having an elastic modulus higher than the elastic modulus of a material constituting the electrode plate for supporting the electrode plate. The support is so formed as to cover at least two of the upper surface and the lower surface of the electrode plate and the side surface of the hole.

Abstract: A structure that is well suited to connecting an MTJ device to a CMOS integrated circuit is described. It is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum. A method for its formation is also described.

Abstract: An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

Abstract: A photoelectric conversion device comprising: a semiconductor substrate; an inorganic photoelectric conversion layer provided within the semiconductor substrate; and an organic photoelectric conversion layer provided above the inorganic photoelectric conversion layer, wherein the organic photoelectric conversion layer is prepared by a shadow mask method.

Abstract: A technique for forming a white light LED is disclosed. In one embodiment, the LED emits blue light. A first phosphor for producing red, yellow, yellow-green, or green light is formed to conformably coat the LED die. One suitable deposition technique is electrophoretic deposition (EPD). Over the resulting LED structure is deposited another phosphor (to add the remaining color component) in a binder (e.g., silicone) for encapsulating the die. The blue LED light combines with the two phosphor colors to create white light. Since the two different deposition techniques are independent and easily controllable, the resulting white light temperature is highly controllable and the color emission is substantially uniform.

Abstract: An arrangement of semiconductor chips is provided. The arrangement includes a plurality of stacked semiconductor chips each including an integrated circuit. At least one via is formed through the thickness of at least one of the semiconductor chips. A carbon nanotube conductor is formed in the via. The conductor has first and second opposite ends. The first end of the conductor is selectively interconnected with the integrated circuit of its semiconductor chip and the second end of the conductor is selectively interconnected with the integrated circuit of another of the semiconductor chips.

Abstract: A CMOS image sensor integrated with 1T-SRAM is provided on a substrate having a pixel array part, a logic circuit part, and a memory part by adding only one photoresist process. There are a plurality of CMOS image sensor devices in the pixel array part, a logic circuit in the logic circuit part, and a plurality of 1T-SRAMs in the memory part, and each part is isolated by a plurality of STI regions. The 1T-SRAM includes a capacitor structure and a transistor. The capacitor structure includes a well region as a bottom capacitor plate, a capacitor dielectric layer, and a top capacitor plate formed on the substrate respectively. The transistor includes a gate dielectric layer, a gate, a drain, and a source continuous with and electrically connected to the well region.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a semiconductor region of the first conductivity type formed on a top surface of the semiconductor substrate, a lower electrode formed on a bottom surface of the semiconductor substrate, an upper electrode formed on a top surface of the semiconductor region, a buried semiconductor layer of a second conductivity type formed in the semiconductor region, a first semiconductor layer of the second conductivity type, formed on the top surface of the semiconductor region and connected to the upper electrode, and a second semiconductor layer of the second conductivity type, formed on a side surface of the semiconductor region and connected to the buried semiconductor layer and the first semiconductor layer, the second semiconductor layer having a lower second conductivity type impurity concentration than the buried semiconductor layer.

Abstract: A semiconductor device including a substrate driven field-effect transistor with a lateral channel and a parallel-coupled Schottky diode, and a method of forming the same. In one embodiment, the substrate driven field-effect transistor of the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof, and a lateral channel above the conductive substrate. The substrate driven field-effect transistor also includes a second contact above the lateral channel and an interconnect that connects the lateral channel to the conductive substrate operable to provide a low resistance coupling between the first contact and the lateral channel. The semiconductor device also includes a Schottky diode parallel-coupled to the substrate driven field-effect transistor. A first and second terminal of the Schottky diode are couplable to the first and second contacts, respectively, of the substrate drive field-effect transistor.

Abstract: A conductive element and an electric connector using the same, wherein the conductive element is formed by plating a thin metal layer on the surface of a liquid electric conductor. The electric connector comprises an insulating body and at least a conductive element contained therein, wherein the conductive elements are formed by plating the thin metal layer on the surface of the liquid electric conductor. The conductive element of the present invention has a liquid metal with low impedance to obviously reduce the impedance of the conductive element, and it plates the thin meal layer on the surface of the liquid electric conductor to increase the elasticity of the conductive element. Besides, the structure of the conductive element is simple to manufacture easily.

Abstract: Structure and method are provided for semiconductor devices. The devices include trenches filled with highly doped polycrystalline semiconductor, extending from the surface into the body of the device for, among other things: (i) reducing substrate current injection, (ii) reducing ON-resistance and/or (iii) reducing thermal impedance to the substrate. For isolated LDMOS devices, the resistance between the lateral isolation wall (tied to the source) and the buried layer is reduced, thereby reducing substrate injection current. When placed in the drain of a lateral device or in the collector of a vertical device, the poly-filled trench effectively enlarges the drain or collector region, thereby lowering the ON-resistance. For devices formed on an oxide isolation layer, the poly-filled trench desirably penetrates this isolation layer thereby improving thermal conduction from the active regions to the substrate. The poly filled trenches are conveniently formed by etch and refill.

Abstract: The present invention aims at providing a semiconductor device that can prevent quality degradation of a signal caused by noise, reduce a malfunction of a circuit caused by latch-up, and secure favorable isolation, and the semiconductor device includes: a first layer with a resistivity higher than 10 ?cm and lower than 1 k?cm which is formed in a semiconductor substrate; a second layer formed on a surface of the semiconductor substrate so as to be located above the first layer; two semiconductor devices formed in the second layer or on the second layer; and a trench-type insulating region which is located between the two semiconductor devices, is formed in the semiconductor substrate so as to reach the first layer from the surface of the semiconductor substrate, and electrically isolates the two semiconductor devices.

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

Abstract: A semiconductor device is composed of: an array of CMOS primitive cells provided in a circuit region; a power supply line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a ground line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a first decoupling capacitor provided under the power supply line; a second decoupling capacitor provided under the ground line. The first decoupling capacitor is formed of a PMOS transistor having a gate connected to the ground line. At least one of the source and drain of the PMOS transistor is connected to the power supply line. The second decoupling capacitor is formed of an NMOS transistor having a gate connected to the power supply line. At least one of the source and drain of the NMOS transistor is connected to the ground line.

Abstract: A reprogrammable switch includes first phase-change material, a reference element, and a sense amplifier. The sense amplifier is coupled to the first phase-change material and the reference element and configured to compare a signal from the first phase-change material to a signal from the reference element and output a voltage signal based on the comparison.

Abstract: A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and bottom insulating layers. The fuse layer is connected to the other metal layers through via plugs. The fuse layer includes separate blocks and at least a connecting block and is coupled to at least a heat buffer block of a different layer. Because the heat buffer block is coupled to the blocks of the fuse layer, new fusing point and a new path for effectively dissipating the heat are provided and a longer and sinuous electric current path is obtained between the blocks through the heat buffer blocks. The heat buffer block and the blocks coupled to the heat buffer block can avoid large current flowing through the fuse structure and prevent overheating.

Abstract: An integrated electronic device includes a substrate, passive components, pads for external connection, and three-dimensional wiring. The passive components includes a multi-stage coil inductor provided on the substrate. The multi-stage coil inductor has a plurality of coils disposed in several layers. Mutually adjacent coil wires are spaced-apart from each other. The three-dimensional wiring includes a first wiring portion which extends on the substrate, a second wiring portion which extends off the substrate but along the substrate, and a third wiring portion connecting with the first wiring portion and the second wiring portion.

Abstract: A capacitor is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor generally comprises a top conductive plate, a capacitor dielectric and a bottom conductive plate that respectively comprise a patterned layer of tantalum nitride TaN, a layer of a nitride based material and a layer of patterned polysilicon.

Abstract: The present invention relates to a high performance heterojunction bipolar transistor (HBT) having a base region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 nm thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not less than about 80% of the predetermined critical germanium content. The present invention also relates to a method for enhancing carrier mobility in a HBT having a SiGe-containing base layer, by uniformly increasing germanium content in the base layer so that the average germanium content therein is not less than 80% of a critical germanium content, which is calculated based on the thickness of the base layer, provided that the base layer is not more than 100 nm thick.

Abstract: A semiconductor device having high ruggedness is provided. The distance Wm2 between buried regions, positioned at the bottoms of different base diffusion regions and face each other, is set smaller than the distance Wm1 between buried regions positioned at the bottom of the same base diffusion region (Wm1>Wm2). An avalanche breakdown occurs under the bottom of the base diffusion region, and the avalanche current is not passed through a high resistance part immediately under the source diffusion region in the base diffusion region, thereby providing high withstand strength against destruction.

Abstract: A micronized semiconductor nanocrystal complex including a plurality of semiconductor nanocrystals embedded in a first matrix material wherein the first matrix material is a micronized polymer. The micronized semiconductor nanocrystal complex can be used in or include inks, paints, dyes, LEDs, taggants, tracers and cosmetics. The present application further provides methods of making micronized semiconductor nanocrystal complexes.

Abstract: A wafer holder for a wafer prober, a heater unit including the same, and a wafer prober including the heater unit are provided in which deformation or breakage of a chuck top can be prevented and proper measurement can be realized even in repeated use. A wafer holder in the present invention includes a chuck top having a chuck top conductive layer on a surface thereof and a support body supporting the chuck top. The chuck top and the support body are fixed to each other by a screw. The difference of thermal expansion coefficient between the screw and the chuck top is 5.0×10?6/K or less.

Abstract: A method for forming through-wafer interconnects (TWI) in a substrate of a thickness in excess of that of a semiconductor die such as a semiconductor wafer. Blind holes are formed from the active surface, sidewalls thereof passivated and coated with a solder-wetting material. A vent hole is then formed from the opposite surface (e.g., wafer back side) to intersect the blind hole. The blind hole is solder filled, followed by back thinning of the vent hole portion of the wafer to a final substrate thickness to expose the solder and solder-wetting material at both the active surface and the thinned back side. A metal layer such as nickel, having a glass transition temperature greater than that of the solder, may be plated to form a dam structure covering one or both ends of the TWI including the solder and solder-wetting material to prevent leakage of molten solder from the TWI during high temperature excursions.

Abstract: Methods for forming blind wafer interconnects (BWIs) from the back side of a previously thinned substrate structure such as a semiconductor wafer to the underside of a bond pad on its active surface includes the formation of a blind hole from the back side, application of a passivating layer therein, anisotropically etching to remove passivation material from the blind hole bottom, blanket-depositing at least one conductive layer within the blind hole and over the back side, blanket-depositing a resist in the blind hole and over the back side, planarizing the back side to remove resist and the at least one conductive layer, removing resist from the blind hole, and filling the blind hole with solder or other conductive material or a dielectric material.

Abstract: A hermetic interconnect is fabricated on a substrate by forming a stud of conductive material over a metallization layer, and then overcoating the stud of conductive material and the metallization layer with a layer of compliant dielectric material. In one embodiment, the layer of compliant dielectric material is low Young's modulus silicon dioxide, formed by sputter-deposition at low temperature, in a low pressure argon atmosphere. The interconnect may provide electrical access to a micromechanical device, which is enclosed with a capping wafer hermetically sealed to the substrate with an AuInx alloy bond.

Abstract: An aspect of the present invention provides an ohmic electrode that includes an SiC (silicon carbide) substrate, an impurity region selectively formed in a surface of the SiC substrate, an insulating film formed on the surface of the SiC substrate, a contact hole opened through the insulating film, to expose a surface of the impurity region, a conductive thermal reaction layer formed in the contact hole in contact with the impurity region, a conductive plug formed to fill the contact hole, an metal wiring formed on the insulating film and electrically coupled to the plug, and a diffusion preventive layer formed between the metal wiring and the plug to electrically couple the plug with the metal wiring, the diffusion preventive layer configured to prevent the diffusion of metal atoms from the metal wiring.

Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrate. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (first terminal) and a second current inlet/outlet terminal (second terminal) respectively provided at an end and the other end of the first fuse link, and a third current inlet/outlet terminal (second terminal) and a fourth current inlet/outlet terminal (third terminal) provided at an end and the other end of the second fuse link.

Abstract: A lead frame-based semiconductor device package including at least one land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. The terminal pads of the interposer substrate may be electrically connected to both a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. The assembly is overmolded with an encapsulant, leaving the opposing side of the interposer substrate free of encapsulant. Lead fingers of a lead frame superimposed on the opposing side of the interposer substrate are bonded directly to the land grid array lands.

Abstract: The lead frame 10 has drain leads 7 with first ends proximate one edge of the die pad and second ends distal from the die pad. A gate lead is proximate an opposite edge of the die pad and extends away from it. Source leads 6 are integral with the die pad and extend away from the same edge as the gate lead. After encapsulation the universal drain clip 30 is attached to the drain of the die and selectively attached to the distal ends of the drain leads. For landed grid footprints and ball grid footprints, the universal clip provides a drain contact on the same exterior surface as the source and gate contacts. For an MLP footprint, the universal drain is connected to the distal ends of the drain leads to carry the drain contact to the opposite external surface.

Abstract: A continuous plating system with mask registration is disclosed herein that uses drums and rollers with protruding pins which engage with guide holes in a masking belt and a lead frame. Through engagement with the pins the masking belt is keyed to the lead frame as the lead frame passes through a plating solution tank.

Abstract: A semiconductor device comprises a package having a cavity in the interior thereof, a chip having a semiconductor element, and an adhesive portion comprised of a silicone or fluorine resin and particles each having a predetermined shape. The adhesive portion fixes the chip on the bottom of the cavity.

Abstract: In a stacking semiconductor device in which a first-layer and a second-layer semiconductor devices are stacked and bonded with a solder, warpage occurs due to a difference in thermal expansion coefficient of constituent members or a difference in elastic modulus of individual members. Therefore, between the first-layer and the second-layer semiconductor devices are provided an external connection terminal of solder and a thermosetting resin, and the stacking semiconductor device is heated at 150 to 180° C., which are the temperatures of preheating for reflow of the solder, for 30 to 90 seconds. Thereby the warpage of the first-layer semiconductor device is reduced and the thermosetting resin is cured completely in this state. Then, the temperature is raised to a reflow temperature of the solder and solder bonding using the external connection terminal is performed. Thereby, the bonding reliability of a solder-bonded portion of the stacking semiconductor device is considerably improved.

Abstract: In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.

Abstract: A striped tape carrier for TAB includes a plurality of mounting parts. In the respective mounting parts, wiring patterns to bond electrodes of electronic components are formed. Each of exposure regions includes a predetermined number of mounting parts. On both sides of each of the exposure regions, alignment marks and identification marks are formed. The alignment marks are used for alignment during the exposure. The identification marks are used for specifying positions of the respective exposure regions on the tape carrier.

Abstract: The present invention provides a semiconductor device which comprises a lower substrate having wiring patterns formed of a plurality of wirings, semiconductor chips located above the lower substrate and electrically connected to the wirings, an intermediate member which seals the semiconductor chips in columnar form and substantially, and a resin board which substantially covers the entire upper surface of the intermediate member. A thermal expansion coefficient of the resin board and a thermal expansion coefficient of the lower substrate are made approximately identical to each other.

Abstract: The semiconductor device includes a chip, a sealing resin for sealing the chip, which includes a first lateral side and a second lateral side, both of which are located adjacent to each other, and a plurality of leads that protrude from different positions on the first lateral side. The positions on the first lateral side have different distances from the second lateral side, and the protruding distances of the plurality of the leads are set to be longer as their positions on the first lateral side are located nearer to the second lateral side. The semiconductor device is mounted on a mounting board through a second lateral side of the sealing resin.

Abstract: A semiconductor device includes a silicon substrate having first and second surfaces, in which a wiring pattern is formed on the first surface; a first resin layer formed over the first surface of the silicon substrate; and a second resin layer formed over the second surface of the silicon substrate. The silicon substrate has a thickness less than 150 ?m, and each of the first and second resin layers has a thickness larger than that of the silicon substrate.