Abstract: The invention relates to an LED package for facilitating color mixing using a diffuser and a manufacturing method of the same. The LED package includes a substrate with an electrode formed thereon, and an LED chip mounted on the substrate. The LED package also includes an encapsulant applied around the light emitting diode chip, containing a diffuser. The LED package further includes a lens part disposed on the light emitting diode chip and the encapsulant to radiate light in a wide angle. The LED package allows light from the light emitting diode chip to be emitted out of the package without distortion. The invention allows light to exit through the encapsulant containing the diffuser and the lens part, achieving uniform diffusion and emission of light from the LED chip, thereby increasing a radiating angle and obtaining a uniform light source.

Abstract: The invention provides a high quality composite phosphor powder which ensures diversity in emission spectrum, color reproduction index, color temperature and color, a light emitting device using the same and a method for manufacturing the composite phosphor powder. The composite phosphor powder comprises composite particles. Each of the composite particles includes at least two types of phosphor particles and a light transmitting binder. The phosphor particles have different emission spectrums. In addition, the light transmitting binder is formed between the phosphor particles and binds them together.

Abstract: The invention relates to a surface mount optoelectronic component with a lens attachment, the method for precising the lens position and the method to manufacture the whole component.

Abstract: A display panel package includes a first electronic member, a second electronic member and an electrically conductive structure for electrically connecting the first electronic member and the second electronic member. The electrically conductive structure has a plurality of bumps electrically and spacedly connected to the first electronic member, and a plurality of posts electrically connected to the second electronic member and penetrated into the bumps respectively.

Abstract: A package structure of a light emitting diode for outputting a target peak wavelength includes a carrier, a first die and a second die. The first die is disposed on the carrier. The first die has a first peak wavelength greater than the target peak wavelength. The second die is disposed on the carrier and has a second peak wavelength smaller than the target peak wavelength. The first die and the second die emit light of the same color group.

Abstract: A light source device including a substrate, a first LED chip, a second LED chip, a third LED chip and a light guide element is provided. The first LED chip is disposed on one side of the substrate. The second LED chip is disposed on the other side of the substrate. The third LED chip is disposed above the substrate. The light guide element has a first light-receiving surface corresponding to the first LED chip, a second light-receiving surface corresponding to the second LED chip, a third light-receiving surface corresponding to the third LED chip, and a light-emitting surface. The light guide element correspondingly receives and mixes the light emitted by the first LED chip, the second LED chip and the third LED chip via the first light-receiving surface, the second light-receiving surface and the third light-receiving surface, and then projects the mixed light via the light-emitting surface.

Abstract: Phosphor compositions having the formula EueMmAaGgQqNnXx, where M is at least one of Be, Mg, Ca, Sr, Ba, Cd, Sn, Pb or Zn; A is at least one of B, Al, Ga, In, Bi, Sc, Y, La or a rare earth element other than Eu; G is at least one of Si or Ge; Q is at least one of O, S, and Se; X is at least one of F, Cl, Br and I; 0<e<2, 0<m<2, 0?a<1, 0<g<1, 0<q<4, 0?n<2, 0?x<2, and 2e+2m+3a+4g=2q+3n+x; and light emitting devices including a light source and the above phosphor. Also disclosed are blends of EueMmAaGgQqNnXx and one or more additional phosphors and light emitting devices incorporating the same.

Abstract: A n-type GaAs buffer layer 2, a n-type GaInP buffer layer 3, a n-type AlGaInP cladding layer 4, an undoped AlGaAs guide layer 5, an AlGaAs/GaAs multiquantum well (MQW) active layer 6, a first p-type AlGaInP cladding layer 7, a p-type GaInP etching stopper layer 8, a second p-type AlGaInP cladding layer 9, a C-doped AlGaAs layer (Zn-diffusion suppressing layer) 10, a p-type GaInP intermediate layer 11, and a p-type GaAs cap layer 12 are sequentially grown on a n-type GaAs substrate 1.

Abstract: A semiconductor device is provided that includes a semiconductor substrate, a first resistance element on a semiconductor substrate, a capacitance element over the first resistance element, and an insulating layer between the first resistance element and the capacitance element.

Abstract: A structure includes a semiconductor light emitting device including a light emitting layer disposed between an n-type region and a p-type region. The light emitting layer emits first light of a first peak wavelength. A wavelength-converting material that absorbs the first light and emits second light of a second peak wavelength is disposed in the path of the first light. A filter material that transmits a portion of the first light and absorbs or reflects a portion of the first light is disposed over the wavelength-converting material.

Abstract: Disclosed herein is a high-quality group III-nitride semiconductor thin film and group III-nitride semiconductor light emitting device using the same. To obtain the group III-nitride semiconductor thin film, an AlInN buffer layer is formed on a (1-102)-plane (so called r-plane) sapphire substrate by use of a MOCVD apparatus under atmospheric pressure while controlling a temperature of the substrate within a range from 850 to 950 degrees Celsius, and then, GaN-based compound, such as GaN, AlGaN or the like, is epitaxially grown on the buffer layer at a high temperature. The group III-nitride semiconductor light emitting device is fabricated by using the group III-nitride semiconductor thin film as a base layer.

Abstract: The invention relates to a high-output, high-efficiency nitride semiconductor light emitting device with low operating voltage and high resistance to electrostatic discharge. The nitride semiconductor light emitting device includes an n-contact layer formed on a substrate and a current spreading layer formed on the n-contact layer. The nitride semiconductor light emitting device also includes an active layer formed on the current spreading layer and a p-clad layer formed on the active layer. The current spreading layer comprises at least three multiple layers composed of at least one first nitride semiconductor layer made of InxGa(1?x)N, where 0<x<1 and at least one second nitride semiconductor layer made of InyGa(1?y)N, where 0?y<1 and y<x, the first and second nitride semiconductor layers formed alternately. The multiple nitride semiconductor layers comprise some layers doped with n-type dopant and other layers which are undoped.

Abstract: A silicon-controlled rectifier apparatus, comprising a substrate upon which a low-voltage triggered silicon-controlled rectifier is configured. A plurality of triggering components (e.g., NMOS fingers) are formed upon the substrate and integrated with the low-voltage triggered silicon-controlled rectifier, wherein the plurality of triggering components are inserted into the low-voltage triggered silicon-controlled rectifier in order to permit the low-voltage triggered silicon-controlled rectifier to protect against electrostatic discharge during human-body model and charged-device model stress events.

Abstract: A semiconductor substrate, includes: a capacitance-adjusting semiconductor layer which is disposed in a predetermined region on a semiconductor substrate material and which is sufficiently thick and has a lower impurity density than that of the semiconductor substrate material; a first insulation film disposed on the capacitance-adjusting semiconductor layer; and a body layer made of a semiconductor disposed on the first insulation film.

Abstract: A system to provide power to a motor includes a multi-channel output array comprising first and second field effect transistors configured to be operable simultaneously.

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. A first-conductivity-type transistor included in the high-speed I/F circuit block is formed in a second-conductivity-type well, and a second-conductivity-type transistor included in the high-speed I/F circuit block is formed in a first-conductivity-type well formed in a second-conductivity-type substrate to enclose the second-conductivity-type well. A first-conductivity-type transistor and a second-conductivity-type transistor included in the driver logic circuit block are formed in a region other than a region of the first-conductivity-type well for the high-speed interface circuit block.

Abstract: A heterojunction structure composed of a nitride semiconductor thin film and nanostructures epitaxially grown thereon exhibits high luminescence efficiency property due to facilitated tunneling of electrons through the nano-sized junction, and thus can be advantageously used in light emitting devices.

Abstract: An organic photosensitive optoelectronic device having a plurality of cells disposed between a first electrode and a second electrode. Each cell includes a photoconductive organic hole transport layer adjacent to a photoconductive organic electron transport layer. A metal or metal substitute is disposed between each of the cells. At least one exciton blocking layer is disposed between the first electrode and the second electrode.

Abstract: A substrate for film growth of group III nitride, a method of manufacturing the same, and a semiconductor device using the same are provided which can make an AlN thin film relatively thin without cloudiness, as well as cracks and pits are reduced in a group III nitride thin film layer constituting the device grown thereon. A substrate 10 for film growth of group III nitride is constituted which includes a substrate material 11 and an AlN thin film 12 formed on said substrate as a buffer layer, and a semiconductor device comprising group III nitride thin film is formed thereon, and the AlN thin film is formed at plural steps at least one of which changes film growth conditions during the film growth.

Abstract: A field effect transistor according to an embodiment of the invention includes: a semiconductor substrate; a channel layer of a first conductivity type formed on the semiconductor substrate; and a semiconductor layer of a second conductivity type that is buried in a recess structure formed in a semiconductor layer on the channel layer and connected with a gate electrode, in which the recess structure is formed using a recess stopper layer containing In, a semiconductor layer that contacts the bottom of the semiconductor layer of the second conductivity type does not contain In, and the uppermost semiconductor layer among semiconductor layers that contact a side surface of the semiconductor layer of the second conductivity type does not contain In.

Abstract: A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier gene

Abstract: An integrated circuit device includes a CMOS image sensor and a MIM capacitor therein. The CMOS image sensor includes a transfer gate electrode on a semiconductor substrate and a P-N junction photodiode within the semiconductor substrate. The photodiode is located adjacent a first side of the transfer gate electrode. A floating diffusion region is also provided within the semiconductor substrate. This floating diffusion region is located adjacent a second side of the transfer gate electrode. An interlayer insulating layer is provided on the semiconductor substrate. The interlayer insulating layer extends opposite the transfer gate electrode, the P-N junction photodiode and the floating diffusion region. An optical shielding layer of a first material is provided on the interlayer insulating layer. The optical shielding layer has a single opening therein, which extends opposite the P-N junction photodiode. This single opening inhibits optical crosstalk between adjacent unit cells within the sensor.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, an USG (undoped silicate glass) layer is utilized during a process of forming a capacitor to leave a hard mask layer and a polysilicon layer on the top surface of a peripheral circuit region, and then a plate electrode layer on the peripheral circuit region is removed in a subsequent process to prevent a cut fuse pattern from being oxidized, thereby improving device characteristics and reliability of the semiconductor device.

Abstract: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used to form nanotubes in arrays in the presence of directing electric fields, optionally in combination with self-assembled monolayer patterns. Bistable devices are described.

Abstract: The present invention provides a solid-state imager device having a patterned buried doped region in the substrate, preferably an n+ doped region, that collects excess electrons and thus reduces cross-talk, minimizes blooming of excess electrons, and reduces dark current in a solid-state imager device.

Abstract: An image sensor according to an embodiment of the invention includes: a plurality of pixels arranged in line; a reading gate adjacent to the plurality of pixels; a plurality of memory gates formed adjacent to the reading gate and corresponding to the plurality of pixels; a plurality of memory control gates corresponding to the memory gates; and a CCD accumulation gate common to the plurality of memory control gates.

Abstract: The nitride-based semiconductor device includes a carrier traveling layer 1 composed of non-doped AlxGa1-xN (0?X<1); a barrier layer 2 formed on the carrier traveling layer 1 and composed of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the carrier traveling layer 1; a threshold voltage control layer 3 formed on the barrier layer 2 and composed of a non-doped semiconductor having a lattice constant equal to that of the carrier traveling layer 1; and a carrier inducing layer 4 formed on the threshold voltage control layer 3 and composed of a non-doped or n-type semiconductor having a lattice constant smaller than that of the carrier traveling layer 1. The nitride-based semiconductor device further includes a gate electrode 5 formed in a recess structure, a source electrode 6 and a drain electrode 7.

Abstract: A multi-level transistor comprising a second active region having a single-crystalline characteristic and a method for manufacturing the multi-level transistor are disclosed. The multi-level transistor comprises a substrate comprising a first active region, a first transistor formed on the first active region, a first insulating layer covering the first transistor, and adapted to isolate the first active region, a second active region comprising a patterned first selective epitaxial growth (SEG) layer formed on the first insulating layer, and a second transistor formed on the second active region.

Abstract: The present invention provides a photoelectric conversion device capable of detecting light from weak light to strong light and relates to a photoelectric conversion device having a photodiode having a photoelectric conversion layer; an amplifier circuit including a transistor; and a switch, where the photodiode and the amplifier circuit are electrically connected to each other by the switch when intensity of entering light is lower than predetermined intensity so that a photoelectric current is amplified by the amplifier circuit to be outputted, and the photodiode and part or all of the amplifier circuits are electrically disconnected by the switch so that a photoelectric current is reduced in an amplification factor to be outputted. According to such a photoelectric conversion device, light from weak light to strong light can be detected.

Abstract: A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.

Abstract: A semiconductor device includes: two MOSFETs each having a gate electrode formed on a substrate through a gate insulating film, a gate sidewall formed on both sides of the gate electrode, and a source/drain region formed in the substrate; a filled film filled between the adjacent gate sidewalls of the two MOSFETs; and a covering layer covering the gate electrodes and the gate sidewalls of the two MOSFETs, and the filled film to give each of channels formed between the source/drain regions, respectively, a strain.

Abstract: A high voltage MOS transistor including a substrate, a well, a gate insulation layer, a gate, two drift regions, a channel region, a source/drain region and an isolation structure is provided. The well is disposed in the substrate and the gate insulation layer is disposed over the substrate. The gate is disposed over the gate insulation layer. The two drift regions are in the well at two sides of the gate and the width of the gate is greater than or equal to that of the drift regions. The channel region is disposed between the drift regions and the width of the channel region is greater than that of the drift regions. The source/drain regions are formed within the drift regions. The isolation structure is disposed inside the drift regions between the source/drain region and the channel region. The drift regions enclose the source/drain regions and the isolation structure.

Abstract: A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon gate, and source/drain regions for the transistor are formed using the sacrificial carbon sidewall spacers to define the source/drain regions. The sacrificial carbon sidewall spacers are replaced with non-carbon sidewall spacers, and the sacrificial carbon gate is replaced with a desired metal gate material to provide the desired metal gate material on the gate dielectric. Various embodiments form source/drain extensions after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier is used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers.

Abstract: An imaging device with readout chain circuitry that uses multiple analog-to-digital converters and amplifiers, which are similarly calibrated using a stitching technique, to readout each color of a column and mitigate the possibility of a boundary effect.

Abstract: A transient index stack having an intermediate transient index layer, for use in an imaging device or a display device, that reduces reflection between layers having different refractive indexes by making a gradual transition from one refractive index to another. Other embodiments include a pixel array in an imaging or display device, an imager system having improved optical characteristics for reception of light by photosensors and a display system having improved optical characteristics for transmission of light by photoemitters. Enhanced reception of light is achieved by reducing reflection between a photolayer, for example, a photosensor or photoemitter, and surrounding media by introducing an intermediate layer with a transient refractive index between the photolayer and surrounding media such that more photons reach the photolayer. The surrounding media can include a protective layer of optically transparent media.

Abstract: A pixel cell array architecture having ion implant regions as isolation regions between adjacent active areas of pixels in the array. In one exemplary embodiment, the invention provides an ion-doped p-well region separating n-type photosensitive areas of neighboring pixel cells. The pixel cells have increased fill factor without encountering the disadvantages associated with conventional shallow trench isolation regions.

Abstract: Imager devices having an array of photosensors, each photosensor having at least two doped regions. The two doped regions are each independently tailored to a particular wavelength.

Abstract: Methods for operating a pixel cell include efficient transferring of photo-charges using multiple pulses to a transistor transfer gate during a charge integration period for an associated photosensor. The pixel cell can be operated with efficient transfer characteristics in either normal or high dynamic range (HDR) mode. The high dynamic range can be realized by either operating an optional HDR transistor or by fluctuating the voltage applied to a reset gate.

Abstract: A pixel cell including a substrate of a first conductivity type over an epitaxial layer of a second conductivity type. The epitaxial layer has a dopant gradient, wherein the dopant concentration decreases from a surface of the epitaxial layer adjacent the substrate to the surface of the epitaxial layer opposite the substrate. A photo-conversion device is at a surface of the epitaxial layer.

Abstract: The photodiode cell (1) includes at least one photosensitive area (3), made in a silicon semiconductor substrate (2), for receiving light, particularly coherent light, and a passivation layer and a dielectric layer (4). The passivation layer is composed of at least a first silicon oxide layer (5) and a second nitride layer (6), made on the photosensitive area. The second nitride layer is made with a thickness within a determined margin, so as to be situated in a zone with the most constant possible light reflectivity independently of the thickness of the first layer. An etch (7) can be performed on one portion of the dielectric layer (4) or on the first layer (5) corresponding to half of the reception surface of the photosensitive area in order to obtain a reflectivity percentage mean of the light to be sensed by the photodiode cell.

Abstract: An image sensor includes a trench formed by a shallow trench isolation (STI) process, a channel stop layer formed over a substrate in the trench, an isolation structure filled in the trench, and a photodiode formed in the substrate adjacent to a sidewall of the trench. In more detail of the image sensor, a trench is formed in a substrate through a STI process, and a channel stop layer is formed over the substrate in the trench. An isolation structure is formed in the trench, and a photodiode is formed in the substrate adjacent to a sidewall of the trench.

Abstract: Imaging devices utilizing sub-wavelength gratings to separate the spectral components of the natural white light are disclosed. This disclosed method and apparatus redirects the light to be collected onto separate photosensors for different wavelengths to provide improved quantum efficiency.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory cell that includes (1) a semiconductor fin enclosure formed on an insulating layer of a substrate; and (2) a ferromagnetic material within the semiconductor fin enclosure. A top surface of the ferromagnetic material is below a top surface of the semiconductor fin enclosure. Numerous other aspects are provided.

Abstract: A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric capacitor formed above the transistor and comprising a lower electrode, a ferroelectric film and an upper electrode, a first hydrogen barrier film formed over the ferroelectric capacitor, an insulator formed over the first hydrogen barrier film, a contact plug disposed in the insulator and electrically connected with the upper electrode, a second hydrogen barrier film disposed between the contact plug and the insulator continuously, and a wiring connected with the contact plug.

Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.

Abstract: In a ferroelectric structure after a first lower electrode film is formed using a first metal nitride, a second lower electrode film is formed on the first lower electrode film using a first metal, a second metal oxide and/or a first alloy. After a ferroelectric layer is formed on the second lower electrode film, a first upper electrode film is formed on the ferroelectric layer using a second alloy. Related devices are also disclosed.

Abstract: A ferroelectric memory includes a substrate, an interlayer dielectric layer composed of at least one layer formed above the substrate, a plurality of ferroelectric capacitors formed above the interlayer dielectric layer, a coating layer that covers the plurality of ferroelectric capacitors, a first opening section provided between the plurality of ferroelectric capacitors, a second opening section that is connected to the first opening section and formed in the coating layer and the interlayer dielectric layer, and a conductive layer provided in one piece inside the first opening section and the second opening section.

Abstract: A nano-elastic memory device and a method of manufacturing the same. The nano-elastic memory device may include a substrate, a plurality of lower electrodes arranged in parallel on the substrate, a support unit formed of an insulating material to a desired or predetermined thickness on the substrate having cavities that expose the lower electrodes, a nano-elastic body extending perpendicular from a surface of the lower electrodes in the cavities, and a plurality of upper electrodes formed on the support unit and perpendicularly crossing the lower electrodes over the nano-elastic bodies.

Abstract: Nonvolatile memory devices and methods of manufacturing the same are provided. The nonvolatile memory devices may include an oxide layer formed of a resistance conversion material, a lower electrode, a nano-wire layer formed of a transition metal on the lower electrode, and an upper electrode formed on the oxide layer. According to example embodiments, a reset current may be stabilized by unifying a current path on the oxide layer.

Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.