Abstract: Techniques are disclosed to select functional parameters and/or operating modes of a circuit based on a time measurement are disclosed. One example integrated circuit includes a threshold detection and timing circuit that is coupled to measure a signal during an initialization period of the integrated circuit from a multifunction capacitor that is to be coupled to a first terminal of the integrated circuit. A selection circuit is coupled to the threshold detection and timing circuit to select a parameter/mode of the integrated circuit in response to the measured signal from the multifunction capacitor during the initialization period of the integrated circuit. The multifunction capacitor is coupled to provide an additional function for the integrated circuit after the initialization period of the integrated circuit is complete.

Abstract: A partial discharge sensing system and method for conducting testing inside an enclosure includes a partial discharge sensor, an access port, and a signal cable. The partial discharge sensor is permanently installed at a test location inside the enclosure. The access port is configured so that an analyzer can be connected to the access port from an exterior of the enclosure. The signal cable operably connects the partial discharge sensor and the access port to enable an analyzer connected to the access port from outside the enclosure to interface with the partial discharge sensor for generating test data.

Abstract: A RF current transformer sensor includes a first sensor portion and a second sensor portion. The first and second sensor portions are configured to define a fixed opening for receiving a test object. The RF current transformer sensor is capable of detecting current pulses between the first sensor portion and the second sensor portion for sensing partial discharges from the test object. Further disclosed is a method of partial discharge sensing.

Abstract: An apparatus for measuring spin polarization via Point Contact Andreev Reflection (PCAR) at a magnet-superconductor junction, with variable magnetic fields and temperature control. A cryostat probe investigates superconducting energy gap and Andreev reflection in superconductor-half metal junctions, in a wide range of magnetic fields and temperature from 2K-300K. The cryostat probe is integrated with a commercial physical properties measurement system. The measurement probe includes a rotary-translation stage with coarse and fine screws that enable a user to make point contacts in a cryogenic, evacuated environment where the point contact junction can be controlled at room temperature by turning a knob. Copper wires are connected as electrical leads from an aluminum housing, descend down to a copper housing, for measurement, when contact is made by tip with a half-metal sample, such as CrO2.

Abstract: A system and method for inspecting a composite structure, such as to assess thermal degradation or resin curing, are provided in which the dielectric constant of the composite structure is determined using a microwave inverse scattering technique. The dielectric constant of the composite structure may be compared to the dielectric constant of one or more sample structures to determine the presence of thermal degradation or improper curing in the structure. In this regard, a system for inspecting a composite structure comprises a transmitter, a receiver, and a controller. The transmitter may be capable transmitting microwave energy directed toward the structure. The receiver may be capable of receiving microwave energy scattered from the structure. The controller may be capable of determining a dielectric constant of the structure using an inverse scattering algorithm and comparing the dielectric constant of the structure to a dielectric constant of at least one sample structure.

Abstract: Methods, systems and devices are described for detecting a measurable capacitance using sigma-delta measurement techniques. According to various embodiments, a voltage is applied to the measurable capacitance using a first switch. The measurable capacitance is allowed to share charge with a passive network. If the charge on the passive network is past a threshold value, then the charge on the passive network is changed by a known amount for a sufficient number of repetitions until the measurable capacitance can be detected. Such a detection scheme may be readily implemented using conventional components, and can be particularly useful in sensing the position of a finger, stylus or other object with respect to a button, slider, touchpad or other input sensor.

Abstract: A bridge sensor emulator includes a first emulation circuit programmable to emulate an output signal of the bridge circuit under 11 conditions each including a different combination of applied stimulus and temperature. A second emulation circuit is programmable to emulate the temperature-sensing device for 3 temperatures. An excitation signal is applied to the first emulation circuit. One rotary switch is coupled to the first emulation circuit to select from it and emulate a bridge output signal. An emulated common mode sensor output voltage is also generated. Another rotary switch is coupled to the second emulation circuit to select from it and emulate one of three temperature output signals. In another embodiment, a microcontroller, nonvolatile memory, and three digital to analog converters are utilized to emulate the bridge sensor for the 11 conditions.

Abstract: An apparatus for providing modulation mapping is disclosed. The apparatus includes a laser source, a motion mechanism providing relative motion between the laser beam and the DUT, signal collection mechanism, which include a photodetector and appropriate electronics for collecting modulated laser light reflected from the DUT, and a display mechanism for displaying a spatial modulation map which consists of the collected modulated laser light over a selected time period and a selected area of the IC.

Abstract: In one preferred embodiment, an apparatus for testing a cable includes an interface for connecting to a connector of the cable, many resistors, a socket, and a meter for testing resistance of the resistors. The interface has many pins, the resistors respectively connected to the pins in series, and the socket is electrically connected to the pins respectively via the resistors. The meter includes two probes, one of the probes is connected to another connector of the cable, and the other one of the probes is plugged into the socket. Because conductors of the cable are respectively connected to the resistors in series, the user can tell whether the cable has a fault according to the resistance indicated by the meter.

Abstract: A probe card, an apparatus and a method of inspecting an object. In the example method, a first inspection current may be divided into a plurality of first divided inspection currents. Each of the first divided inspection currents may be supplied to a different one of a plurality of first chips. A second inspection current may be selectively applied to a second chip other than the first plurality of chips. In an example, the second inspection current may be substantially equal to at least one of the plurality of first divided inspection currents. In a further example, the example probe card and/or the apparatus may perform the example method.

Abstract: Several embodiments of integrated circuit probe card assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates.

Abstract: A wafer holder that can improve throughput by improving heating rate and thermal uniformity of a prober, as well as a wafer prober having the same are provided. The wafer holder has a chuck top conductive layer on a surface of a chuck top, and a heater body at a portion other than the portion where the chuck top conductive layer is formed, wherein maximum outer diameter l of an area where the heater body exists is smaller than diameter L of the chuck top, and the maximum outer diameter l and thickness t of the chuck top are set such that the thickness t and diameter Wl of a wafer to be inspected satisfy the relation of 1+4t>Wl.

Abstract: A wafer holder and a wafer prober including the same are provided in which the positional accuracy of the wafer holder is very high when the wafer holder is moved to a prescribed position in probing, and the positional accuracy are less likely to vary even with repeated movements. The wafer holder in accordance with the present invention includes a chuck top having a chuck top conductive layer on a surface thereof and a support body supporting the chuck top. The weight of the wafer holder is 28000 g or less. Preferably, the weight of the chuck top is 6000 g or less. Preferably, the weight of the support body is 12000 g or less.

Abstract: A wafer holding body used for a wafer prober for testing a semiconductor wafer includes a chuck top having a conductive layer on a surface thereof and a support body supporting the chuck top. The support body has a base portion opposing the chuck top and a side portion extending from the perimeter of the base portion to the chuck top to support the chuck top. A cavity portion is formed between the chuck top and the base portion of the support body. A reflection plate is provided in the cavity portion. A heater unit and a wafer prober includes the wafer holding body.

Abstract: A semiconductor integrated circuit device is provided including a switch to selectively supply a test signal to a pin on the integrated circuit device in response to a switch control signal. A control circuit is also provided to generate the switch control signal.

Abstract: A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing circuit includes a ring buffer into which the respective memory device signal is latched responsive to a first clock signal. The particular buffer into which the memory device signal is latched is determined by a write pointer, which is incremented by the first clock signal. The outputs of the buffers are applied to a multiplexer, which is controlled by a read pointer to couple a memory device signal from one of the buffers to the memory device. The read pointer is incremented by a second clock signal having a timing that is adjustable and may be different from the second clock signal used to increment the read pointer in a clock domain crossing circuit for a different memory device signal.

Abstract: In a method and apparatus for determining one or more electrical properties of a semiconductor wafer or sample, the response of a semiconductor wafer or sample to an applied CV-type electrical stimulus is measured. Utilizing a recursive technique, progressively more accurate values of equivalent oxide thickness CET, maximum capacitance Cox, flatband voltage Vfb and other properties of the semiconductor wafer or sample are determined from the measured response. An equivalent oxide thickness EOT of the semiconductor wafer or sample can be determined as a function of the most accurate value of CET determined based upon convergence of at least one of (1) the last two values of Cox or (2) the last two values of Vfb within a predetermined convergence criteria. One or more of the EOT value and/or values of one or more of CET, Cox or Vfb can then be output in a human detectable form.

Abstract: Systems and methods for sensing obstructions associated with electrical testing of microfeature workpieces are disclosed. An apparatus in accordance with one embodiment includes a first support member configured to releasably carry a microfeature workpiece, a second support member positioned proximate to the first support member and configured to carry an electrical testing device, wherein at least one of the first and second support members is movable toward and away from the other. The apparatus can further include a signal source (e.g., radiation source) positioned proximate to the support member, and a signal sensor (e.g., a radiation sensor) positioned at least proximate to the first support member and the signal source. The signal sensor can be configured to received at least a portion of the signal directed by the signal source and passing proximate to the first support member.

Abstract: According to one embodiment, a printed circuit board for a real-time clock IC includes a plurality of wiring layers sequentially laminated to form one substrata and including at least one layer which forms an oscillator circuit pattern having a crystal oscillator generating a reference signal and an oscillation stabilizing portion which stabilizes and oscillates the reference signal and adjusts the oscillation frequency to a target frequency, and a power supply layer arranged in at least one of a position between the plurality of wiring layers and front and rear surfaces of the substrate, and forming a power supply circuit pattern which supplies electric power to a circuit on the substrate and removing a portion of the power supply circuit pattern which has width not smaller than width of the oscillator circuit pattern in a portion of the power supply circuit pattern which overlaps with the oscillator circuit pattern.

Abstract: Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.

Abstract: A process for testing IC wafer is disclosed. Prior to electrically testing chips on a wafer, the wafer is pre-cut to form a plurality of grooves aligned with the scribe lines on the active surface of the wafer. A step of singulating the wafer is performed to form a plurality of individual chips after completing electrical or reliability test of the chips. Due to the pre-cutting step the chips are still integrated on the wafer for accurately probing and testing. And the testing step can obtain the influence of defects between the test terminals and a UBM layer on the function of the chips.

Abstract: A packaged circuit module. In one embodiment, the packaged circuit module includes an X2Y device having first and second ground terminals, a positive terminal, and a negative terminal. The packaged circuit module also includes a first interface terminal, a second interface terminal, and a bracket. The first interface terminal electrically connects to the positive terminal of the X2Y device and to a first terminal of a motor. The second interface terminal electrically connects to the negative terminal of the X2Y device and to a second terminal of a motor. The bracket connects the first and second ground terminals of the X2Y device and to a grounding structure.

Abstract: A test circuit for a flat panel display device is provided. The test circuit includes a substrate, a plurality of pixel structures, a plurality of signal lines and a plurality of shorting bar sets. The substrate includes at least one scan side, at least one data side and a pixel area. Each pixel structure formed in the pixel area having n sub-pixels, where n is a positive integer. The signal lines are formed on the substrate, and each signal line is connected to a corresponding sub-pixel. Each shorting bar set is formed on at least one of the at least one scan side and the at least one data side, wherein the shorting bar sets are electrically connected to the signal lines.

Abstract: A liquid crystal display (LCD) inspection apparatus for inspecting an LCD panel, includes a worktable to support an LCD panel seated on a front side of the worktable, probe units to be electrically connected to the LCD panel, a backlight unit to emit light toward the LCD panel, a first polarizing plate arranged in front of the LCD panel to polarize the light, and a second polarizing plate arranged between the LCD panel and the backlight unit to polarize the light, and a shutter unit to selectively shut off the light emitted from the backlight unit toward the LCD panel.

Abstract: The liquid crystal display (LCD) inspection apparatus for inspecting an LCD panel includes a worktable which supports the LCD panel to be seated on a front side of the worktable, probe units which are electrically connected to the LCD panel, a backlight unit which supplies light to the LCD panel, an imaging unit which photographs an image of the LCD panel supported by the worktable, a first polarizing plate which is arranged between the imaging unit and the LCD panel to polarize the light, a second polarizing plate which is arranged between the LCD panel and the backlight unit to polarize the light, an illumination unit which emits illumination light to surfaces of the LCD panel, and an image processor which receives the image photographed by the imaging unit, and extracts defect information from the received image.

Abstract: A liquid crystal display (LCD) inspection apparatus is provided which is capable of preventing detection of defects from being omitted or degraded due to formation of stains in a certain region of an LCD panel in an inspection of the LCD panel.

Abstract: An LCD test method and apparatus for reducing the number of channels of a probe unit is provided. An apparatus for testing a liquid crystal display including: a stage on which a liquid crystal panel is placed; a plurality of vertically divided blocks, wherein each of the vertically divided blocks include a plurality of adjacent data lines; a data probe unit that provides test pattern signals respectively to groups of at least two of the plurality of vertically divided blocks of the liquid crystal panel; a plurality of horizontally divided blocks, wherein each of the horizontally divided blocks include a plurality of adjacent gate lines; a gate probe unit that provides scanning signals respectively to the plurality of horizontally divided blocks of the liquid crystal panel; and a controller that provides test pattern signals to the data probe unit and provides scanning signals to the gate probe unit.

Abstract: A liquid crystal display (LCD) inspection apparatus and method are provided. The inspection apparatus and method are capable of automatically and accurately detecting defects of an LCD panel, and providing information of the automatically-detected defects of the LCD panel to the operator, thereby enabling the operator to easily recognize the defects.

Abstract: Disclosed are a liquid crystal display panel and apparatus, which can prevent electrolytic corrosion or other corrosion of on-off pads in a test pad part. The liquid crystal display panel comprises: a pixel part having a plurality of pixels arranged in a matrix at intersections of a plurality of gate lines and a plurality of data lines; a gate pad part having a plurality of gate pads, each of the gate pads connected with the corresponding gate lines to deliver a gate signal; a data pad part having a plurality of data pads, each of the data pads connected with the corresponding data lines to deliver a data signal; a test pad part having at least one or more on-off pads delivering a test signal to the gate lines or the data lines; and a switching device for cutting off the gate signal and/or the data signal so as not to be provided to the on-off pads upon driving the liquid crystal display panel.

Abstract: A single-stage level shifting circuit is used to interface control signals across the boundary between voltage domains with differing positive or ground voltage potentials Asserted states are determined by the difference between the positive voltages potentials and the ground potentials. A lower positive power supply potential is not used to turn OFF PFET coupled to a higher positive power supply potential. Likewise a higher ground power supply potential is not used to turn OF NFETs coupled to a power domain where is significant ground shift. The single stage level shifting circuit has keeper devices that hold asserted states using voltages within the power gated domain.

Abstract: In one embodiment, a system for sharing a static random-access memory (SRAM) table between two or more lookup tables (LUTs) that are equivalent to each other includes at least two basic logic elements (BLEs) each associated with a truth table representing a particular function provided by the BLE. The particular functions provided by the BLEs including equivalency to each other. Each BLE includes an LUT including the truth table associated with the BLE. The LUTs of the BLEs share an SRAM table with each other to obviate the LUTs of the BLEs including SRAM tables separate from each other.

Abstract: An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconnect architecture programmably coupling selected ones of the plurality of inputs, the plurality of outputs, the programmable logic block, the analog circuit block, and the analog-to-digital converter. At least one of the inputs may be programmably configured as one of a digital input programmably coupleable to elements in the programmable logic block or as an analog input to an analog circuit in the analog circuit block.

Abstract: A network structure configures a blocking network having constraint against such a combination of said network input terminal and network output terminal as to make it unfeasible to further connect, when connecting first network input terminals to first network output terminals, second network input terminals to any one of the second network output terminals, and operation elements and the network output terminals are connected so as to minimize a constraint strength between the plurality of network output terminals inputting to the same operation element with respect to the constraint strength defined as the number of network input terminals contained in tuples of network input terminals to which the two network output terminals in the network output terminals can not be simultaneously connected.

Abstract: A shift register circuit having shift registers comprising a first transistor having a gate and a first source/drain for receiving an output signal of a pre-stage shift register, a second transistor having a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to a first clock signal, and a second source/drain coupled to a output, a first pull-down module coupled to the output terminal, for receiving the first clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the first clock signal are at low voltage level, and a second pull-down module coupled to the output and a second clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the second clock signal are at low voltage level.

Abstract: A self-excited inverter circuit, includes: a booster transformer with a secondary coil, a feedback coil, and a primary coil respectively wound thereon, the primary coil including a center tap to which operating power can be supplied; a first N-channel FET having a drain to which is connected one terminal of the primary coil, and having a gate to which is connected one terminal of the feedback coil; and a second N-channel FET having a drain to which is connected the other terminal of the primary coil, and having a gate to which is connected the other terminal of the feedback coil, wherein: using a high voltage drive output generated in the secondary coil when the first and second N-channel FETs are turned on alternately, a discharge tube is driven and turned on; and the first and second N-channel FETs are both formed in a single package.

Abstract: Embodiments of the invention provide methods and apparatuses for restoring a duty cycle of a complementary output signal pair. In one embodiment, the output signal pair is brought in phase with a complementary input signal pair by delaying a complementary intermediate signal pair from which the output signal pair is generated. The intermediate signal pair is switched to a first logic state in response to detecting a crossing point between rising and falling signals of the output signal pair. The intermediate signal pair is switched to a second logic state in response to detecting a crossing point between rising and falling signals of the input signal pair.

Abstract: Various circuit embodiments comprise an input node to receive an input signal for a CMOS transistor stack, a first output node to deliver the input signal to a PMOS pull-up transistor of the CMOS transistor stack, and a second output node to deliver the input signal to an NMOS pull-down transistor of the CMOS transistor stack. A first passive signal path between the input node and the first output node is adapted to pass an effective rising edge of the input signal and delay an effective falling edge of the input signal to a gate of the PMOS transistor. A second passive signal path between the input node and the second output node is adapted to delay the effective rising edge of the input signal and pass the effective falling edge of the input signal to a gate of the NMOS transistor. Other aspects and embodiments are provided herein.

Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

Abstract: Disclosed is an output buffer including a first output buffer for data for receiving a data signal and outputting an output signal from an output terminal, a second output buffer with an output end thereof connected to the output terminal, and a selection circuit. The selection circuit receives a control signal indicating whether de-emphasis enabled or de-emphasis is disabled and performs switching control so that when the control signal indicates that the de-emphasis is disabled, the second output buffer is deactivated, when the control signal indicates that the de-emphasis is enabled, emphasis data obtained on delaying the data signal through a delay circuit is supplied to an input end of the second output buffer, thereby causing the second output buffer to operate as a de-emphasis buffer, and when a test control signal is of a value indicating an amplitude margin test, the data signal is selected to be supplied to the input end of the second output buffer.

Abstract: A differential output circuit includes a bias circuit connected with a first voltage. An input circuit section includes first and second MOS transistors of a first conductive type, and the first and second MOS transistors are connected with the first voltage through the bias circuit, and gates of the first and second MOS transistors receive a differential input signal. Third and fourth MOS transistors of a second conductive type are connected with the first and second MOS transistors through first and second resistance elements, respectively, and connected with a second voltage. A first connection node between the first MOS transistor and the first resistance element is connected with a gate of the fourth MOS transistor, and a second connection node between the second MOS transistor and the second resistance element is connected with a gate of the third MOS transistor.

Abstract: A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% duty cycle, a much more stable and accurate reference signal is established for receiving single-ended data.

Abstract: Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an Nx1 MUX. The Nx1 MUX is controlled by the skew controller. The output of the Nx1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.

Abstract: A thin film transistor array substrate comprises thin film transistors and pixel electrodes formed at respective pixels that are defined by gate lines and data lines that orthogonally intersect each other. The thin film transistor array substrate further comprises a plurality of gate pad units that group a plurality of gate pads extended from the gate lines, and a plurality of data pad units that groups a plurality of data pads extended from the data lines. The thin film transistor array substrate further includes a plurality of gate test terminals connected to the gate pad units and beside at least one side of the respective gate pad units, and a plurality of data test terminals connected to the data pad units and located beside at least one side of the respective data pad units.

Abstract: A comparator circuit includes a first and a second PMOS transistors having sources connected to a first power supply and drains connected to a first node, NMOS transistors having sources connected to a second power supply and drains connected to the first node, a third and a fourth PMOS transistors having sources connected to the first power supply and the drains connected to a second node, and a third and a fourth NMOS transistors having sources connected to the second power supply and drains connected to the second node. A reference voltage and a voltage of a signal to be compared against are applied to gates of the thirst and the third PMOS transistors, and gates of the first and the third NMOS transistors. A comparator unit 1 outputs a comparison result between voltage of the first and the second nodes.

Abstract: A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of the first buffer connects to an external pad of the buffer circuit, and an output of the second buffer connects to the pad via the isolation circuit. The buffer circuit is selectively operative in at least a first mode or a second mode in response to at least a first control signal. The isolation circuit is operative in the first mode to substantially isolate the second buffer from the external pad and is operative in the second mode to connect the output of the second buffer to the external pad.

Abstract: A drain of a NMOS 32 of a canceling circuit 30 is connected to an output node NO to set the source of the above NMOS32 to floating-state. Furthermore, the gate of the NMOS 32 is provided with a signal SB being inverted by an inverter 31. By the above operation, the NMOS 32 conducts the thoroughly opposite operation to one of the NMOS 22 of the driving circuit 20 and the under shoot caused by the above NMOS 22 is canceled by the over shoot caused by the NMOS 32. Consequently, the under shoot or the over shoot arising at the output node NO when the input signal IN is changed can be restrained.

Abstract: A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic control unit, wherein the first flip-flop circuit has two clock input terminals connected to the second and third flip-flop circuits respectively and two control signal input terminals connected to the first and second logic control units respectively. The second and third flip-flop circuits count rising edges and falling edges of an input frequency under control of the first and second flip-flop circuits and accordingly, symmetric output signals are output from the first flip-flop circuit.

Abstract: Methods and apparatuses for generating a power-on-reset signal that is substantially independent of temperature change are disclosed. A reset circuit comprises a voltage generator, a first resistance element, a current generator, and a comparator. The voltage generator is configured for generating a first voltage signal having a negative temperature coefficient. The first resistance element is operably coupled between a supply voltage and a second voltage signal. The current generator is operably coupled to the second voltage signal and configured for sinking a reference current having a positive temperature coefficient and an offset current. The comparator is configured for comparing the first voltage signal to the second voltage signal to generate a reset signal. The present invention further includes semiconductor devices, semiconductor wafers, and electronic systems including the method or apparatus for generating the power-on-reset signal.

Abstract: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.

Abstract: In some embodiments, a PLL with an output to provide a PLL output clock at a target frequency is provided. The PLL comprises a VCO to generate a clock to be used to generate the PLL output clock. Also provided is circuitry to maintain the VCO's bias level at a sufficient level if it is insufficient. Other embodiments may be disclosed herein.