Abstract: Embodiments of the present invention generally provide improved techniques and circuit configurations for a delay-locked loop (DLL) circuit. In one embodiment, a first phase difference between an input clock signal and an output clock signal is measured. Based on the first phase difference, a first phase adjustment setting is stored in a first FIFO and a second phase adjustment setting is stored in a second FIFO. The first phase adjustment setting is applied to adjust a phase of the input clock signal and the adjusted clock signal passes through one or more delay elements. The second phase adjustment setting is applied to further adjust the delayed input clock signal. As a result, the first phase adjustment setting and the second phase adjustment setting are applied correctly with respect to an edge of the clock signal passing through the DLL circuit.

Abstract: A delay-locked loop (DLL) employs an in-loop duty cycle corrector (DCC) to provide accurate multiphase clock generation with 50% duty cycle. Each delay cell can advantageously provide both delay and duty cycle correction functionality. In one embodiment, delay correction can precede duty cycle correction. The bandwidths of the DCC and the DLL can differ by a factor of a decade to achieve fast and stable operation.

Abstract: A clock controller for use with an off-chip driver and including a first delay element, a second delay element, a restore circuit, and an adjustment circuit. The clock controller includes a node receiving a reference clock represented by a least one clock signal. The first delay element is configured to delay one of the at least one clock signals by a first delay time, and the second delay element is configured to delay one of the at least one clock signals by a second delay time. The restore circuit is configured to provide at least a first output clock to the off-chip driver, wherein the off-chip driver provides output data based at least on the first output clock. The adjustment circuit is configured to adjust the first and second time delays to adjust edges of the first output clock such that output data from the off-chip driver aligns with edges of the reference clock, and to adjust the second delay time to maintain the first output clock at a desired duty cycle.

Abstract: A DLL for reducing jitter during a high frequency operation by separately controlling a coarse delay and a fine delay. The DLL includes a multiplexing unit for selectively outputting one of the rising clock and the falling clock; a first delay line for generating a first internal clock and a second internal clock; a second delay line for generating a first clock and a second clock; a delay line control unit for controlling the second delay line; a phase control unit for generating a first DLL clock and a second DLL clock by mixing the first clock and the second clock; and a phase comparing unit for comparing the first DLL clock and the second DLL clock with the rising clock to generate a lock signal for controlling an operation timing of the first delay line and the second delay line.

Abstract: A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock, a plurality of delay components for delaying the input clock to generate a plurality of delay clocks with different phase according to a count value, a phase detector coupled to a final delay components for detecting a phase transition between a final delay clock and the input clock, and a counter coupled to the phase detector and the frequency divider for generating the count value according to the phase transition between the final delay clock and the input clock.

Abstract: A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.

Abstract: A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The first buffer buffers first and second main input signals having phases opposite to each other, outputs first and second main output signals, and controls slew rates of the first and second main output signals using at least one main control signal. The second buffer buffers first and second sub-input signals having phases opposite to each other, outputs first and sub-output signals, and controls slew rates of the first and second sub-output signals using at least one sub-control signal. The output driver generates first and second output signals having opposite phases using at least two control signals and the output signals of the first and second buffers.

Abstract: A duty cycle corrector including a restore circuit configured to receive a differential input clock and a differential feedback clock each having crossings of a first type and a second type and to provide a differential output clock having crossing of the first type based on differential input clock crossings of the first type and crossings of the second type based on differential feedback clock crossings of the first type. A delay element configured to delay the differential output clock by a delay time to provide the differential feedback clock. An adjuster circuit configured to receive the differential input and feedback clocks and to adjust the delay time so as to maintain a duty cycle of the differential output clock substantially at a desired duty cycle.

Abstract: The present invention discloses a flip-flop implemented with metal-oxide semiconductors using a single low-voltage power supply and a control method thereof, wherein an external control signal is input to a power switch in order to turn on the power switch for an active mode or to turn off the power switch for a sleep mode and inputting an external sleep control signal; the power switch is used to control a combinational circuit to enter into the active or the sleep mode, and the combinational circuit is connected to a virtual power supply; an internal clock signal is separately input to a master stage and a slave stage of the flip-flop, and whether to enter into the sleep mode or the active mode is determined by the voltage level of the internal clock signal. In the present invention, all the logic gates of the combinational circuit are formed of low-threshold CMOS's, which enables the present invention to maintain a given operation speed at a lower voltage.

Abstract: Control methods and apparatus are disclosed for operating an inverter at resonant mode, where the inverter adapts its frequency to the resonant tank characteristics before a lamp is struck, and operates at fixed frequency after the lamp is struck. Disclosed embodiments combine the advantages of operation in fixed mode as well as the variable mode.

Abstract: Disclosed is a delay adjustment circuit including a first set of transistors, which are connected between a PMOS transistor forming an inverter and a power supply in parallel and have gates supplied with control signals, respectively, a second set of transistors which are connected between an NMOS transistor forming the inverter, and the ground GND, in parallel and have gates supplied with control signals, respectively, and another inverter receiving an output of the inverter as an input. At least one of the transistors of the first set of transistors and at least one of the transistors of the second set of transistors are set in an on-state.

Abstract: An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by the phase alignment magnitude to generate a first phase delay signal. The clock input is delayed by a phase delay magnitude to generate a second phase signal and the second phase signal is delayed by about the phase delay magnitude to generate a last phase delay signal. A phase difference is detected between the first phase delay signal and the last phase delay signal and adjustments are made to at least one of the phase delay magnitude and the alignment magnitude.

Abstract: Provided are a direct current (DC) offset compensation apparatus and a method thereof. A DC offset compensation apparatus comprises an offset detection block detecting a DC offset, an offset compensation block operating according to an output signal of the offset detection block, and an offset compensation amplifying block controlled according to an output signal of the offset compensation block. Particularly, the offset compensation block comprises a counter that counts polarities of DC offsets for a predetermined period, a controller that comprises first to fourth mode units respectively operating fast down-compensation, regular down-compensation, fast up-compensation, and regular up-compensation modes, and a control device that controls the execution of one selected among the first to fourth mode units based on a value counted by the counter, and a register storing data to control the offset compensation amplifying block based on the one mode unit determined by the controller.

Abstract: A level shift circuit for sustaining the activation and inactivation response of a transistor with respect to an input signal in a preferable manner. The level shift circuit includes a shift circuit for converting an input signal having a first voltage to an output signal having a second voltage that is higher than the first voltage. The voltage generation circuit includes a control voltage generation circuit, for generating control voltage having a generally constant voltage level irrespective of the level of a power supply voltage, and a bias generation circuit. The bias generation circuit generates bias voltage so that the node voltage of the shift circuit is substantially equalized with the control voltage.

Abstract: A quick turn on apparatus and method for a NMOSFET switch are used to maintain the gate voltage of the NMOSFET switch non-zero but not enough to turn on the NMOSFET switch, such that the NMOSFET switch turns on more quickly when it is to be turned on. Seamless transition can be further achieved in a single pole double throw switching circuit by using the quick turn on apparatus and method.

Abstract: An apparatus switching an input signal by a switching transistor in response to a clock includes: (a) A capacitor. (b) A charging circuit coupled for charging the capacitor with a supply voltage in response to the clock. (c) A switching circuit coupled with the capacitor and configured for coupling the switching transistor with the capacitor in response to the clock. (d) A grounding circuit coupled with the switching transistor and a ground locus. The grounding circuit includes a first grounding transistor coupled with the switching transistor and a second grounding transistor. The first grounding transistor has connection loci permitting electrical coupling with the gate, the source, the drain and the bulk portion of the first grounding transistor. The source connection locus and the bulk connection locus are coupled in common. The second grounding transistor couples the first grounding transistor with the ground locus in response to the clock.

Abstract: An electronic network comprises a plurality of nodes that each comprise a current input and a current output, and at least one transistor arranged as a first current mirror and a second current mirror. The first and the second current mirrors are complementary to each other such that an output of the first current mirror is operably connected to an input of the second current mirror. Resistive connections connect the nodes such that the output of one or more of the nodes is operably connected to the input of one or more of the nodes.

Abstract: Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204) of an integrated circuit (200). The voltage controller adjusts the gate signal depending upon whether the circuitry is in an eFuse programming mode or an eFuse resistance measuring mode. The voltage controller may optionally include a voltage tuner (252) for tuning the gate signal to account for operating variations in the programming transistor caused by manufacturing variations.

Abstract: A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.

Abstract: A method and apparatus for generating a variable output voltage from a voltage reference circuit is disclosed. A voltage reference circuit includes a first voltage generator configured for generating a first voltage signal having a negative temperature coefficient and a second voltage generator configured for generating a second voltage signal having a positive temperature coefficient. The voltage reference circuit further includes a current generator configured for supplying a reference current to the first voltage generator and the second voltage generator. A comparator configured for comparing the first voltage signal to the second voltage signal generates a comparison result to modify the reference current with a current change related to the result of the comparison.

Abstract: In CMOS processing, there may be a case in which a resistance element, such as a poly-silicon resistance, or the like, may be formed which has negative temperature characteristics, that is, the characteristics opposite from the characteristics of a typical resistance element. In a constant current circuit using this resistance element, a constant current output less affected by the influence of varying temperature is obtained. To one of the paths of a current mirror circuit from which a constant current is extracted, a serial connection circuit comprising a transistor Q1 for flowing a current I1 having positive temperature characteristics, a resistance element R1 and a bipolar transistor Q6 is connected. Further, in parallel to this serial connection circuit, a temperature compensation circuit comprising a transistor Q8 for flowing a current I2 having negative temperature characteristics and a resistance element R2 is connected.

Abstract: A bias circuit, which generates a bias voltage, has a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node and a second MOS transistor coupled in parallel with the first MOS transistor. The first MOS transistor may have a first ON-state resistance, and the second MOS transistor may have a second ON-state resistance which is lower than the first ON-state resistance. Furthermore, the bias circuit has a resistance circuit coupled between the voltage dividing node and a second reference voltage terminal and a voltage generator coupled with the first node. The voltage generator outputs the bias voltage in dependence upon an electrical potential on the voltage dividing node.

Abstract: An integrated circuit (IC) resonator in which resonator parameters potentially affected by IC fabrication processes are correctable after fabrication. Resonance frequency tuning is effected by forming each feedback capacitor in a pair of integrator circuits to include a variable capacitance device, such as a varactor diode. A tuning signal is applied to the varactor diode to adjust the total capacitance value and, therefore, the resonance frequency. Similarly, the quality (Q) factor of the resonator is adjusted by providing a variable capacitance in an RC (resistance-capacitance) network coupling the output of one of the integrator circuits to the input of the other. The variable capacitance in the RC network permits adjustment of phase in the event that the integrator circuits do not provide a desired 180° total phase shift.

Abstract: An output of a common mode differential amplifier is initialized to a known state, which includes inputting a voltage to a network conductor of an electronic assembly, where the network conductor is coupled to a first input node of a first differential input of the amplifier. The amplifier is on an integrated circuit chip of the assembly and has a self-bias node. Circuitry of the amplifier normally adjusts to obtain an equilibrium voltage on the self-bias node in response to the inputted voltages. To initialize the amplifier output, however, preset circuitry on the integrated circuit chip overrides the normal equilibrium voltage on the self-bias node, forcing the self-bias node to a predetermined voltage regardless of the amplifier input voltages. In response, the amplifier produces an desired initial output state on a first output node of the amplifier.

Abstract: Systems and method for tracking different types of transconductance cells is shown and described. In these multi-cell systems, the addition of one or more tracking control modules allows circuit designers to advantageously incorporate multiple transconductor topologies and their uniquely beneficial characteristics into their designs, without eradicating its centralized multi-cell tuning functionality.

Abstract: A method and apparatus for an ultra-high sensitivity, low cost, passive (no battery) low-power energy harvesting data transmitting circuit energy, such as a RFID (Radio Frequency IDentification) tag integrated circuit “chip.” By using combinations of special purpose design enhancements, the low-power energy harvesting passive data transmitting circuit, such as the RFID tag chip, operates in the sub-microwatt power range. The chip power should be derived from a low-microwatt per square centimeter RF field radiated to the RFID tag antenna from the tag reader (interrogator) or derived from a suitable low signal source, such as a sonic transducer (e.g., a piezoelectric transducer or a low level DC source, such as a bimetallic or chemical source).

Abstract: In a base-bias-control-type high-frequency power amplifier with a plural stage configuration, a rising voltage of a base bias current supplied to an initial stage transistor is made lower than a rising voltage of a base bias current supplied to a second stage transistor by a bias circuit, and a difference between the both voltages is set to be smaller than a base-emitter voltage of an amplifying stage transistor. Also, a rising voltage of a base bias current supplied to a third stage transistor is made equal to the rising voltage of the base bias current supplied to an initial stage transistor. Accordingly, a technology capable of improving the power control linearity can be provided in a high-frequency power amplifier used in a polar-loop transmitter or the like.

Abstract: A radio frequency power amplifier including control electronics for providing control signals for timing of the power amplifier. A first group of the drivers are coupled to the control electronics and a second group of drivers are coupled to the control electronics. The first group of drivers operate in response to the control signals to generate first drive signals and the second group of drivers operate in response to the control signals to generate second drive signals with a phase difference of 180° relative to the first drive signals. A first group of switches energize a first group of primary windings in response to the first drive signals and a second group of switches energize a second group of primary windings in response to the second drive signals. An output summing transformer has a plurality of ferrite cores, the first group of primary windings and the second group of primary windings passing through the ferrite cores.

Abstract: To provide a portable electronic unit that can reduce power consumption. A high-frequency amplification circuit amplifies heart rate information received by an antenna and detects the information by means of a detection circuit. A gain control circuit controls a gain in a gain control amplification circuit in two steps in response to a level of a detection signal of the detection circuit. The gain control amplification circuit amplifies and outputs a detection signal from the detection circuit with a relevant gain. A comparator converts and outputs a digital signal into a waveform. The control circuit controls a display drive circuit and displays a heart rate on a display unit. The control circuit also controls a setup circuit every time the control circuit turns on the high-frequency amplification circuit and brings a gain in the gain control amplification circuit to a maximum value.

Abstract: An input buffer includes a first stage for receiving an input signal and having a first pair of complementary output signals, the first stage including an input circuit for receiving the input signal, an output circuit for generating the first pair of complementary output signals based on the input signal, a resistance feedback circuit connected to the first pair of complementary output signals and generating a feedback signal, and a common mode circuit for balancing the complementary outputs based on the feedback signal.

Abstract: A linearity-improved differential amplification circuit is provided, A linearity-improved differential amplification circuit comprises a main differential amplification unit differentially amplifying a first and a second input signals, a main bias unit biasing the main differential amplification unit, a first current source coupled in series between a power supply voltage terminal and the main bias unit and an auxiliary differential amplification unit differentially amplifying the first and the second input signal and coupled to the main differential amplification unit.

Abstract: The invention concerns controlling automatic gain control for a digital signal receiver. The method includes receiving a digital feedback signal for controlling an amplifier and processing the digital feedback signal to deliver a driving signal to an analog amplifier. Processing the digital feedback signal comprises regulating the evolution of the driving signal so that it is maintained constant during a predetermined period of time after every change.

Abstract: A transistor amplifier circuit has a current to current feedback transformer for neutralization of feedback capacitance and setting the input impedance of the amplifier. IM3 cancellation is implemented by out-of-band terminations at the input, which does not depend on the loading of the output of the amplifier. The IM3 cancellation contributes better linearity, while the capacitance neutralization contributes high and stable gain. These features are more orthogonal than other prior art techniques in terms of gain and linearity over a wide dynamic range. Hence there is less of a trade-off between the desirable properties of high gain and good linearity. Notably they can be implemented to have good efficiency and high levels of integration, which are important for many applications such as wireless transceivers for portable devices or consumer equipment. The amplifier can be a single ended or a differential common emitter amplifier.

Abstract: Methods of and apparatus for distributing power and biasing RF PAs. A power distribution network includes a pre-final amplifier stage power distribution network and a final amplifier stage power distribution network. The pre-final amplifier stage power distribution network includes one or more pre-final amplifier stage power distribution branches, which may be configured to distribute power from one or more pre-final amplifier power supplies to one or more pre-final amplifier stages. Each pre-final amplifier stage power distribution branch comprises a ? C-R-C network coupled to an inductive load. A final amplifier stage power distribution network is configured to distribute power from a final amplifier stage power supply to a final stage of the amplifier circuit.

Abstract: An operational amplifier includes an input stage for producing a a voltage signal in response to an input signal. An output stage includes an output transistor having a source coupled to a supply voltage and a gate coupled to receive the voltage signal. An output cascode transistor has a source coupled to a drain of the output transistor and a drain coupled to an output conductor. A gate control amplifier includes an input stage including a first input transistor having a control electrode coupled to the source of the output cascode transistor and an active load transistor, the input transistor and the active load transistor being coupled to a gate of the output cascode transistor. The gate control amplifier also includes a feedback amplifier having an input coupled to the source of the output cascode transistor and an output coupled to a control electrode of the active load transistor.

Abstract: A cascode connection circuit includes a first field effect transistor (FET) which has a source terminal and a drain terminal, the source terminal being connected to ground; a second FET which has a source terminal and a gate terminal, the source terminal being connected to the drain terminal of the first FET; and a first resistor and a first capacitor connected in series between the source terminal of the first FET and the gate terminal of the second FET. The first FET and the second FET are cascode-connected to each other. The product of the resistance of the first resistor and the capacitance of the first capacitor does not exceed 0.1 times the period of an operating frequency of the circuit.

Abstract: A phase controlling apparatus is disclosed. The phase controlling apparatus controls phases of signals which are output from a plurality of signal sources corresponding to first phase information which indicates a phase of a predetermined signal. The phase controlling apparatus includes a phase information storing section and a phase controlling section. The phase information storing section stores second phase information which indicates a phase of a signal which is output from each of the plurality of signal sources. The phase controlling section changes a phase of a signal which is output from at least one of the plurality of signal sources corresponding to the second phase information stored in the phase information storing means to control the difference of phases of signals which are output from the plurality of signal sources.

Abstract: A high voltage generator includes a high voltage level detector for comparing a boosted high voltage with a reference voltage and generating an oscillator control signal being a first logic level in response to a comparison result; a clock feedback block for receiving the oscillator control signal and an inverse pumping control signal and keeping an oscillator enable signal in the first logic level for a predetermined period; an oscillator for generating a pumping control signal in response to the oscillator enable signal and outputting the inverse pumping control signal to the clock feedback block, wherein the pumping control signal is periodically toggled; and a charge pumping block for generating the boosted high voltage in response to the pumping control signal.

Abstract: A method, algorithm, software, architecture, circuit, and/or system for assisting pull-in of a phase-locked loop (PLL) are disclosed. In one embodiment, a PLL can include: (i) a phase detector that may receive a serial data stream and output a pump control signal; (ii) a charge pump that can receive the pump control signal and substantially determine a frequency control when a precharge signal is de-asserted; (iii) a precharge/filter circuit that may connect to the charge pump and may substantially determine the frequency control when the precharge signal is asserted; and (iv) an oscillator that may connect to the precharge/filter circuit and may provide a recovered clock in response to the frequency control, where the recovered clock may be correlated to a frequency of the serial data stream. The frequency control may be current and/or voltage based, for example. Embodiments of the present invention can advantageously provide a reliable and simplified design approach for pulling-in a PLL lock.

Abstract: An integrated circuit device is provided having a reference ring oscillator circuit having a plurality of stages. Each stage has a logic gate and electrically connecting to a first independent voltage source. The integrated circuit device also has at least one additional ring oscillator circuit having a plurality of stages. Each stage has a logic gate substantially identical to the logic gates of the reference ring oscillator circuit and electrically connecting to a respective at least one second independent voltage source. Each stage also has a FET load driven by the logic gate and electrically connecting to a third independent voltage source. A measured difference in capacitance between the reference ring oscillator circuit per stage and the at least one additional ring oscillator circuit per stage comprises a gate capacitance of a FET load.

Abstract: The invention relates to a microwave tube comprising an electron gun generating an electron beam in a cylindrical microwave structure of the tube. The microwave structure delivers a microwave at one output. A collector for collecting electrons from the beam comprising at least one electrode that is mechanically coupled to the microwave structure via a dielectric, the mechanical coupling forming a radial waveguide for propagating spurious microwave radiation (Pr) from the tube. In order to attenuate the spurious radiation from the tube, the radial waveguide (Wg) includes at least one quarter-wave microwave trap having, at least at the operating frequency F of the tube, an open circuit for the microwave propagating in said radial waveguide for propagating spurious radiation.

Abstract: One aspect relates to an oscillator, and various oscillator embodiments comprise an amplifier and line driver with an input and an output and a transmission line with a predetermined transmission signal time delay. The output is adapted to produce an inverted signal with respect to a signal received at the input. The transmission line has a first end connected to the output and a second end connected to the input. Other aspects and embodiments are provided herein.

Abstract: A semiconductor circuit for reducing flicker noise includes a negative-conductance generator and a body bias voltage supplying circuit. The negative-conductance generator includes a pair of cross-coupled field effect transistors in order to generate negative-conductance, wherein each field effect transistor includes a body. In order to remove flicker noise generated by the pair of the field effect transistors, the body bias voltage supplying circuit supplies a body bias voltage to the body of each of the pair of the field effect transistors so that a forward bias voltage is supplied to the body and source of each of the pair of the field effect transistors. The field effect transistors are preferably NMOS transistors or CMOS transistors. The semiconductor circuit is used in a voltage controlled oscillator (VCO) or a phase-locked loop (PLL).

Abstract: A method, circuit, and/or system for controlling an amplitude and/or limiting or reducing the energy consumed by an LC voltage controlled oscillator (LCVCO). In one embodiment, an oscillator can include: (i) a bias circuit that can provide first and second bias signals; (ii) an oscillator core that can provide a periodic signal with a frequency related to the first bias signal and an amplitude, where the oscillator core can also provide a feedback signal; and (iii) a current/amplitude controller that can control the amplitude by dynamically dusting the first bias signal in response to the feedback signal. Embodiments of the present invention can advantageously provide a reliable and simplified design approach for amplitude control and substantial energy reduction in an oscillator, such as an LCVCO circuit or a Colpitts differential oscillator.

Abstract: A PLL circuit provides a self-selecting divide ratio, which is varied as necessary to lock the circuit to a reference clock which may have several possible frequencies, thereby enabling the VCO to employ a type of oscillator having a superior jitter characteristic. The PLL circuit includes a variable divider which divides the VCO output by a divide ratio value provided by a frequency band select circuit, which provides the divide ratio needed to drive the phase difference between the reference and divided clocks toward zero while the VCO clock output operates within a predetermined frequency range. The self-selecting variable divide ratio allows the VCO's oscillator to have a narrow output frequency range, thereby allowing the use of an oscillator type with a jitter characteristic which may be low enough to meet the requirements of JEDEC, for example.

Abstract: Signaling between two or more ICs use a signaling scheme wherein a reference signal is generated at the driver side and the receiver side. The driver side reference signal is coupled to the receiver side reference signal with a transmission line channel forming a reference channel. Data signal channels are paired with a reference channel between each two adjacent data channels. Adjacent pairs of data signal channels are each separated with an empty wiring channel. The paired data signals are received in one input of a differential receiver. The reference signal of the reference channel between the two paired data channels is coupled to the other input of the two differential receivers. Coupling from the paired data channels to the reference channel appears a common mode noise and is rejected by the differential receivers. The number of channels is reduced from a full differential signaling scheme.

Abstract: A two-port isolator includes a first center electrode and a second center electrode which are wound around a ferrite to which a direct-current magnetic field is applied from permanent magnets, and the ferrite is mounted on a circuit board having built-in matching circuit devices. The ferrite is preferably substantially rectangular-parallelepiped-shaped having first and second principal surfaces that are substantially parallel to each other, and the long-side length of the principal surfaces is about 1.5 to about 5 times the short-side length. The second center electrode is wound between one and four turns around the ferrite.

Abstract: Apparatus and methods are provided that are adapted to match the impedance of an electrical load to an impedance of an electrical signal generator. The invention includes providing a plurality of electrical components adapted to collectively match the impedance of the electrical load to the impedance of the electrical signal generator. The electrical components are arranged symmetrically and concentrically about an axis. Additionally, the invention may also include a first connector adapted to electrically couple the electrical signal generator to the electrical components. Additionally, the invention may also include a second connector adapted to electrically couple the load to the electrical components. Numerous other aspects are provided.

Abstract: A MEM switch is described having a free moving element within in micro-cavity, and guided by at least one inductive element. The switch consists of an upper inductive coil; an optional lower inductive coil, each having a metallic core preferably made of permalloy; a micro-cavity; and a free-moving switching element preferably also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When the chip is not mounted with the correct orientation, gravity cannot be used. In such an instance, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.

Abstract: An RF power divider circuit unequally divides an input signal into first and second signal components of unequal power. The circuit includes a single input port, first and second output ports, and a combination of a plurality of quarter wave transformers and a plurality of resistors coupled between the input port and the first and second output ports.