Abstract: Devices and techniques for applying a resonant action by an applied oscillating magnetic field to a magnetic tunnel junction (MTJ) and an action of an applied DC current across the MTJ to effectuate a switching of the MTJ when writing data to the MTJ.

Abstract: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

Abstract: A memory device including a memory cell, a first circuit, and a second circuit. The memory cell includes phase-change material. The first circuit is configured to provide pulses to the phase-change material and to program each of more than two states into the memory cell. The second circuit is configured to sense the present state of the memory cell and provide signals that indicate the present state of the memory cell. The first circuit programs each of the more than two states into the memory cell based on the signals.

Abstract: A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least two resistance states. The threshold device is configured to switch from a high resistance state to a low resistance state upon application of a voltage and, when the voltage is removed, to re-assume the high resistance state. Additionally, the threshold device can be configured to switch in response to both negative and positive applied voltages across the first and second electrodes. Memory elements having a memory portion and threshold device between first and second electrodes and methods for forming the memory elements are also provided.

Abstract: A memory array has a plurality of memory cells, arranged in a plurality of rows and columns. Each cell has at least four terminals. The array has a plurality of column lines with each column line connected to a first terminal of a different column of cells. The array also has a plurality of first row lines, with each first row line connected to a second terminal of a different row of cells. The array also has a plurality of second row lines, with each second row line connected to a third terminal of a different row of cells. Finally, the array has a plurality of third row lines with each third row line connected to a fourth terminal of a different row of cells. A column decoder is connected to the plurality of column lines. A first row decoder is connected to the plurality of first row lines. A second row decoder is connected to the plurality of second row lines. A third row decoder is connected to the plurality of third row lines.

Abstract: Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.

Abstract: A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time during a multi-bit read operation. The device further comprises a row selecting circuit adapted to select one of the rows and drive the selected row with a word line voltage, and voltage lines transmitting the respective read voltages to the row selecting circuit as the word line voltage. The read voltages are supplied to the respective voltage lines before starting read periods of the multi-bit read operation.

Abstract: Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing multiple series-coupled select gates, each gate can be made using smaller features sizes while achieving the same level of protection against GIDL and other forms of current leakage. By reducing the feature size of the select gates, the footprint of the strings of memory cells can be reduced, thereby facilitating smaller memory device sizing. Further reductions in device sizing may be achieved utilizing a staggered self-aligned bit line contact configuration.

Abstract: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

Abstract: An electrically erasable programmable read-only memory (EEPROM) cell transistor and a method of fabricating the EEPROM cell transistor are provided. The EEPROM cell transistor comprises a semiconductor substrate; a first tunnel oxide layer formed on the semiconductor substrate; and a first floating gate electrode formed on the first tunnel oxide layer and adapted to store charge that tunnels through the first tunnel oxide layer. The EEPROM cell transistor further comprises a second tunnel oxide layer formed on the first floating gate electrode; a second floating gate electrode formed on the second tunnel oxide layer and adapted to store charge that tunnels from the first floating gate electrode through the second tunnel oxide layer, wherein the second floating gate electrode is formed from a phase changeable material; a gate insulating layer formed on the second floating gate electrode; and a control gate electrode formed on the gate insulating layer.

Abstract: In a non-volatile memory device having a relatively high operation performance and a method of manufacturing the same, a substrate may be prepared to include an active region on which a conductive structure is located and defined by a field region in which an isolation layer is formed. A tunnel oxide layer may be formed on the active region of the substrate. A floating gate pattern may be formed on the tunnel oxide layer, and may include a lower part having a first width that is formed on the tunnel oxide layer and an upper part having a second width that is formed on the lower part, where the second width is substantially smaller than the first width. A dielectric layer pattern may be formed on the floating gate pattern, and a control gate pattern may be formed on the dielectric layer pattern. Accordingly, the non-volatile memory device may have an improved efficiency in programming and erasing data.

Abstract: A non-volatile memory is divided into logical zones by the card controller in order reduce the size of the data structures it uses for address translation. Zone boundaries are adjusted to accommodate defects allowed by memory test to improve card yields and to adjust boundaries in the field to extend the usable lifetime of the card. Firmware scans for the presence of defective blocks on the card. Once the locations of these blocks are known, the firmware calculates the zone boundaries in such a way that good blocks are equally distributed among the zones. Since the number of good blocks meets the card test criteria by the memory test criteria, defects will reduce card yield fallout. The controller can perform dynamic boundary adjustments. When defects occur, the controller can perform the analysis again and, if needed, redistributes the zone boundaries, moving any user data.

Abstract: Data move operations in a memory device are described that enable identification of data errors. During a write operation, identified errors are flagged and used to provide an error status during the data move operation. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.

Abstract: The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.

Abstract: A memory controller receives data to be stored in a flash memory by a host system in synchronism with a clock (external clock) to be a reference for an operation of the host system, and outputs the received data in synchronism with an internal clock of the memory controller. The memory controller receives data to be read from the flash memory by the host system in synchronism with the internal clock of the memory controller, and outputs the received data in synchronism with the external clock.

Abstract: The invention provides a metal bit structure of Twin MONOS memory cell with large channel width and its operational method for high-speed applications using a metal bit array.

Abstract: A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming can therefore be reduced. Multiple verify operations are performed on separate bit lines of the page. Bit line coupling can therefore be reduced.

Abstract: Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution may be achieved over prior methods performed concurrently on all word lines of a NAND string.

Abstract: Methods of operating non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells facilitate mitigation of gate-induced drain leakage and program disturb.

Abstract: A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, a source line coupled to one end of the NAND cell unit, and a bit line coupled to the other end of the NAND cell unit, wherein the NAND cell unit is biased in a data write mode as follows: a write voltage Vpgm is applied to a control gate of a selected memory cell in the NAND cell unit; a channel-isolating voltage is applied to control gates of non-selected memory cells disposed on the source line side of the selected memory cell at intervals of a certain number of memory cells; and a write medium voltage Vm lower than Vpgm is applied to control gates of the remaining non-selected memory cells.

Abstract: A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized depending on the placement of the memory cell in the NAND memory cell string. In another embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized to compensate for faster and slower programming word lines/memory cells.

Abstract: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.

Abstract: A reading method of a NAND memory device includes the steps of first connecting a first end terminal of a stack of cells to a reference line, second connecting a second end terminal of the stack of cells to a respective bitline, and charging the bitline to a predetermined bitline read voltage, where one of the steps of first connecting and second connecting is carried out before charging the bitline and the other of the steps of first connecting and second connecting is carried out after charging the bitline. An order of carrying out the steps of first connecting and second connecting is determined based on an address of a selected cell.

Abstract: A nonvolatile semiconductor memory device may include a cell array and a program modulation unit. The cell array may further include a plurality of word lines, a plurality of bit lines, a plurality of cell transistors and a plurality of source lines. The plurality of bit lines may intersect the plurality of word lines. The plurality of cell transistors may be arranged at intersections of the word lines and bit lines, and may have drains and gates connected to the bit lines and the word lines, respectively. The source lines may be connected to sources of the plurality of cell transistors. The program-voltage modulation unit may modulate a program voltage based on a number of cell transistors selected for programming.

Abstract: In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed after the first charge injection. Surrounding charge that deteriorates the data retention characteristic is reduced by use of initial variation occurring immediately after programming (charge loss phenomenon due to binding of injected charge with the surrounding charge in an extremely short time), and then the charge loss due to the initial variation is compensated, to thereby improve the data retention characteristic.

Abstract: According to an embodiment of a method for operating a nonvolatile memory device, one or more non-volatile memory cells in one or more arrays are written by applying a voltage across a dielectric to store charge on charge centers in the high K dielectric, and one or more non-volatile memory cells are erased by applying a voltage across the dielectric to tunnel electrons off of the charge centers. Applying a voltage across a dielectric includes enhancing a resulting electric field using an injector medium and a high K dielectric. Other aspects and embodiments are provided herein.

Abstract: A program operation for a NOR flash memory device is verified by programming data in a memory cell, performing a dummy verify operation on the memory cell, and performing a program verify operation on the memory cell based on a result of the dummy verify operation.

Abstract: A memory system with two voltage sources comprises a controlling chip which includes a built-in DC/DC converter for transforming low voltage to high voltage, used for transforming 1.8/3.3 voltage to 3.3 voltage. This does not only prevent the phenomenon of voltage drifting but improves the stability of the system.

Abstract: A circuit for generating a step-up voltage, in which it can reduce ripples. The circuit includes a high voltage transfer switch, a high voltage switching unit that pumps a high voltage in response to a clock signal and switches the high voltage transfer switch, a high voltage switching controller, which compares a feedback voltage generated by dividing an output signal of the high voltage transfer switch and a variable reference voltage, generates an internal clock signal using the comparison result and the clock signal, and controls the switching of the high voltage transfer switch in response to the comparison result, and a step-up voltage generator that pumps the high voltage in response to the internal clock signal and a plurality of step-up reference voltages and generates an internal step-up voltage. The high voltage transfer switch outputs the internal step-up voltage in response to the output signal of the high voltage switching unit.

Abstract: A method of manufacturing a storage apparatus includes preparing a first substrate on which a plurality of row lines are arranged in parallel, preparing a second substrate on which a plurality of column lines are arranged in parallel, dispensing as a droplet a solution, in which particles are dispersed in a solvent, from a solution supply port to which an electric field is applied, toward a surface of the first substrate or a surface of the second substrate, and arranging the surfaces of the first and second substrates to face each other with a gap such that the column lines cross the row lines, thereby making the particles at crossing portions to be movable between the row lines and the column lines facing each other and between the crossing portions adjacent to each other.

Abstract: A NAND Flash memory device is described that can reduce circuitry noise during program operations. The memory includes bit lines that can be electrically coupled together to charge share their respective voltage potentials prior to performing a discharge operation on the bit lines.

Abstract: A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract: A non-volatile memory device and programming process is described that erases blocks of non-volatile memory cells by the application of differing word line erase voltages to selected word lines during an erase cycle. This facilitates for a faster on average erase operation, a tighter erased cell Vt distribution, an increase in memory device endurance and lifetimes due to a decrease in memory cell overerasure and overstress, and a more accurate match of word line voltages to the specific non-volatile memory array, the specific region or row being programmed, and any changes in programming characteristics due to device use and wear. In one embodiment of the present invention, the differing word line erase voltages are utilized to compensate for faster and slower erasing word lines. In another embodiment, different word line erase voltages are applied based on physical aspects of the word lines of the array.

Abstract: In some embodiments, a string of nonvolatile memory cells may be erased by driving their control gates with erase voltages that may have different levels for different cells. The cells may be divided into two or more groups, and the cells in each group may be driven by the same erase voltage. In another embodiment, a nonvolatile memory device may include a cell array having two groups of memory cells, and the memory cells in different groups may be simultaneously driven with erase voltages having different levels during an erase operation.

Abstract: A flash memory may be reconfigurable so that the memory space arrangement of the flash array may be changed for particular applications. In one embodiment, a command or comment may be received by the flash memory. In response to the command, the flash memory may be reconfigured so that the arrangement of sectors or the organization of the memory within the flash array may be adapted to a specific application. Then, data may be written to the flash array so organized. In some embodiments, the flash array may, thereafter, be reconfigured for still other applications.

Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

Abstract: I describe and claim a device and method for generating develop voltage signals. The device includes a sense amplifier to sense a voltage difference between a plurality of bit lines responsive to a develop voltage signal, and a voltage generator to generate the develop voltage signal responsive to a reference voltage signal and according to an electrical characteristic of at least one transistor associated with the sense amplifier.

Abstract: A reference voltage generating circuit for producing a predetermined reference voltage at an output node includes a depletion-type n-channel field-effect transistor serving as a first field-effect transistor having one node thereof coupled to a power supply voltage, a second field-effect transistor having one node thereof coupled to another node of the first field-effect transistor and having a highly-doped n-type gate, and a third field-effect transistor having one node thereof coupled to another node of the second field-effect transistor, another node thereof coupled to a ground voltage, and a highly-doped p-type gate.

Abstract: A level detector within a back-bias voltage generator includes a toggling unit and a temperature detector. The toggling unit causes an enable signal to be activated when an absolute value of a back-bias voltage is less than an absolute value of a monitoring level. The temperature detector controls the toggling unit for increasing the absolute value of the monitoring level with an increase in temperature with high temperature sensitivity.

Abstract: A semiconductor memory device including a trimmed voltage generator and a method of generating a trimmed voltage in the semiconductor memory device, in which the semiconductor memory device includes a voltage trimming unit, memory cell array, and a trimming current generator. The voltage trimming unit outputs a first trimming current control signal corresponding to a difference between a predetermined internal voltage and an external voltage supplied from outside of the semiconductor memory device in a trimming mode. The memory cell array stores the first trimming current control signal in the trimming mode and outputs a second trimming current control signal corresponding to the first trimming current control signal in a normal mode. The trimming current generator outputs a trimming current corresponding to the first trimming current control signal in the trimming mode and outputs a trimming current corresponding to the second trimming current control signal in the normal mode.

Abstract: Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current source, adjustable current sink, and a voltage converter, all operably coupled to a current sum node. The first current source generates a first current having a temperature coefficient substantially equal to a temperature coefficient of at least one bit cell. The adjustable current source generates a second current that is substantially independent of a temperature change. The adjustable current sink sinks a third current that is substantially independent of a temperature change. The voltage converter is configured for generating a word-line signal having a word-line voltage proportional to a reference current, wherein the reference current comprises the first current, plus the second current, and minus the third current.

Abstract: A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.

Abstract: A circuit that enables a loop-back test by adjusting phases of data and strobe signals at the input and output in an interface wherein the phase relationships between the data and the strobe signal for sampling the data are different between the input and output. In order to test a phase shift circuit 30 and a sampling circuit 40 on the input side, DQ and DQS are outputted with their phases aligned by a phase shift circuit 20 on the output side, DQ and DQS having the same phase are fed to input buffers 16 and 17, respectively, from output buffers 14 and 15, the phase of DQS is shifted by 90 degrees by phase shift circuit 30, and DQ is sampled by sampling circuit 40.

Abstract: An external delayed switch apparatus for cooling fans aims to provide electric power to at least one cooling fan located in a computer to continuously operate to lower temperature when the computer is shut down. The computer has a power supply which includes a standby power system and a main power supply system to provide electric power for computer operation. The external delayed switch apparatus includes a power converter which is electrically connected to an AC power input source and transforms AC power to DC power required by the cooling fan and an external controller which provides an operation parameter to the power converter to determine operation time of the cooling fan driven by the DC power.

Abstract: A memory control device and a memory control method are provided to compensate for additional delay subsequent to the change in environmental factors and to permit a smooth writing operation. The memory control device includes a controller that calculates a number of delay cells that are necessary to delay a system clock for one period as delay information, and a compensation unit that generates a compensation control signal by using the delay information calculated by the controller signal. The compensation unit compensates for an additional delay which is subsequent to a change in environmental factors such as voltage or temperature.

Abstract: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.

Abstract: A unit cell is composed of a memory cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the memory cell transistor. A memory cell block is composed of a plurality of unit cells connected in series. One end of the memory cell block is connected to a bit line via a block selecting transistor. The other end of the memory cell block is connected to a plate line. A redundancy unit cell is composed of a redundancy cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the redundancy cell transistor. A redundancy memory cell block is composed of a plurality of unit cells connected in series, the number of which is smaller than that of the unit cells in the memory cell block.

Abstract: In a storage device having a redundancy remedy function in a block unit having a memory cells array divided in plural blocks, prior to the access operation to individual memory cells in the block, the block address BA for specifying a block is entered, and block redundancy is determined in the entered block address BA, and hence it is not necessary to determine input or redundancy of the block address BA on every occasion of the access operation. As a result, the time to the access operation start to the memory cell can be shortened, and the access speed is enhanced.

Abstract: A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.