Abstract: A hierarchical error correction system and method operable with a computer memory system. In one embodiment, the memory system comprises a plurality of memory modules organized as a number of error correction code (ECC) domains, wherein each ECC domain includes a set of memory modules, each memory module comprising a plurality of memory devices. A first error correction engine is provided for correcting device-level errors associated with a specific memory device and a second error correction engine for correcting errors at a memory module level, wherein the first and second error correction engines are operable in association with a memory controller operably coupled to the plurality of memory modules.

Abstract: In order to easily perform a timing test on a memory interface included in a semiconductor device so as to satisfy a restriction on latency, the present invention provides a semiconductor device with the memory interface including: a clock output terminal that outputs a clock signal associated with an operation of a memory connected to the memory interface; a command terminal that outputs a command signal associated with control of a state of the memory; a data terminal that exchanges a data signal with the memory; and a data strobe terminal that exchanges a data strobe signal for establishing the data signal. This semiconductor device includes a testing terminal that outputs in advance a signal for starting a test on the memory interface apart from the command signal.

Abstract: A semiconductor integrated circuit for intentionally and flexibly changing a monitoring subject bit if debugging is performed during software processing when a status change occurs. A replacement data register and a comparison address register, which are settable from a microprocessor, determine matching of an address input from the microprocessor and a comparison address value. When the addresses match in a test mode, instead of outputting normal status data, a predetermined value of the replacement data register is output in response to a read request from the microprocessor.

Abstract: A semiconductor memory device and a method thereof are provided. The example method may include determining whether a currently tested cell is defective and repairing the currently tested cell, if the currently tested cell is determined to be defective, before determining whether a next tested cell is defective. The example method may be performed by a semiconductor memory device including a built-in self-test (BIST) circuit and a repair control circuit. Alternatively, the example method may be performed by a semiconductor memory device including a BIST circuit, a repair control circuit and a storage device.

Abstract: A semiconductor memory device is provided which can reliably detect a memory cell which has an unstable operation due to a small memory cell current. A bit line drive circuit is provided with respect to each pair of first and second bit lines, and has a configuration which can decrease a potential of a selected one of the pair of first and second bit lines. During a test operation, the first bit line in conduction with an H-side memory holding node of a memory cell is grounded for a predetermined time, thereby reducing a potential difference between the pair of first and second bit lines.

Abstract: Methods and apparatus provide for pre-charging a bit line and a complementary bit line of an SRAM memory cell of the SRAM memory to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the memory cell.

Abstract: Semiconductor memory devices and methods of controlling bitlines of such devices in which bitlines of a memory cell array adjacent to an activated memory cell array are precharged to the same voltage.

Abstract: In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory unit according to a discharging signal and a column selective signal. When the objective memory unit is enabled, the voltage level of the corresponding column line is changed, if the voltage level reaches a threshold voltage level, the auxiliary module enhances the increment of the voltage level of the column line.

Abstract: A charge pump is disclosed, comprising a plurality of sub-charge pumps connected in series, each comprising a charging switch module turned on or off according to a charging clock signal and a capacitor connected between the charging switch module and a reference clock signal. The charge pump further comprises at least one additional switch module connecting to a reference-clock-providing sub-charge pump and a reference-clock-accepting sub-charge pump among the sub-charge pumps to provide the reference clock signal of the reference-clock-accepting sub-charge pump according to an additional clock signal.

Abstract: A NOR flash memory device comprises a memory cell array, a row selection circuit adapted to drive wordlines in the memory cell array with a wordline voltage during an erase operation, and an erase voltage generating circuit adapted to generate an erase voltage as the wordline voltage during the erase operation. The erase voltage generating circuit includes a discharging circuit receiving a high voltage that is regularly maintained irrespective of variations in a power voltage, and discharging the erase voltage supplied from the wordline during an erasing recovery period of the erase operation.

Abstract: A semiconductor module comprises a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device comprises a first electrode. The second semiconductor device comprises a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.

Abstract: A method for detecting a leakage current in a bit line of a semiconductor memory is disclosed. In one embodiment, the method includes isolating the connection of a sense amplifier from a bit line via an isolation transistor, reading out a memory cell to the bit line, waiting until a predetermined delay time has elapsed, so that a leakage current measurably changes the voltage on the bit line within the delay time. The sense amplifier is short circuited with the bit line via the isolation transistor. The voltage on the bit line is collected by the sense amplifier, and compared with a reference voltage so as to detect the leakage current.

Abstract: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

Abstract: A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage level during a precharge period, and one or more bit line sense amplifiers which are connected between the bit line pair and detect a voltage difference of the bit line pair to amplify a level of the bit line pair. The semiconductor memory device includes one or more FINFETs.

Abstract: A sensing margin varying circuit and method thereof are provided. The example sensing margin varying circuit may control the skew of a ready signal and may include a plurality of semiconductor elements which are connected to a plurality of accelerating transistors positioned on a current path between a node outputting the ready signal and a ground voltage, each of the plurality of accelerating transistors selectively controlled so as to adjust a duration of a logic transition of the ready signal. The example method may control the skew of a ready signal and may include selectively controlling a plurality of accelerating transistors positioned on a current path between a node outputting the ready signal and a ground voltage, each of the plurality of accelerating transistors selectively controlled so as to adjust a duration of a logic transition of the ready signal.

Abstract: A flash memory device (1) includes a cover (10), a metal shield (20) received in the cover (10), a printed circuit board (6) accommodated in the metal shield (20), a cap member (30) for shielding the front the portion of the metal shield (20) and a latching device for interconnecting the metal shield (20) and the cover (10). The latching device contains a resilient ring (40) containing an opening (43) for the shield (20) to extend therethrough and a fixing device (50) for abutting against the rear edge of the printed circuit board (6). The cap member (30) contains a Y-shaped outer shell (31) and an inner shell (32) retained in the outer shell (31). The metal shield (20) contains a number of through holes (211) and the inner shell (32) contains a number of fingers (321) for mating with the through holes (211).

Abstract: Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to the column address. The latch circuit specified in accordance with the column address is supplied with the data to be rewritten. The latch circuit specified in accordance with its address latches the data to be rewritten, whereby rewriting of the data is performed. The data of one page after rewritten is written into the page in the memory cell array that corresponds to the page address of a copy destination.

Abstract: A semiconductor memory device has a plurality of banks in which operations are performed for the banks in accordance with a command supplied from an external controller. The semiconductor memory device comprises a latch circuit for latching a bank selection signal indicative of a bank which was precharged last among the banks before execution of an auto refresh command for sequentially refreshing the banks, and a refresh control circuit, responsive to the execution of the auto refresh command, for controlling the order in which the banks are refreshed according to the auto refresh command such that a bank which is selected by the latched selection signal is refreshed last among the banks.

Abstract: A memory control system includes a first memory for accessing a CPU via an address bus and a data bus, an SDRAM for accessing a CPU via the address bus and the data bus, a SDRAM control circuit for outputting a refresh request to the DRAM and a selection unit for selecting a signal line of the address bus and outputting a signal of the signal line corresponding to the refresh request of the SDRAM control circuit to the SDRAM.

Abstract: A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained. This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell. The refresh portion reads and rewrites data from and in the memory cell in a power-down state.

Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Abstract: There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.

Abstract: A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a first sub memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines, respectively, and second select transistors connected to a common source line, and a second sub memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines, respectively, and fourth select transistors connected to the common source line.

Abstract: Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks. Each of the plurality of memory banks may include memory blocks which may be arranged in different addressable orders. If two edge memory blocks are activated in a given one of the plurality of memory banks, a non-edge memory block may be concurrently activated in at least one of remaining memory banks other than the given one memory bank. Accordingly, a number of concurrently activated memory blocks, a voltage required to enable a word line and noise may be reduced. The example semiconductor device may include the example block select decoding circuit, and likewise may perform the example method of activating a word line with an activation of a reduced number of memory blocks.

Abstract: A basic unit block has a plurality of memory cells, a local bit line pair connected to the plurality of memory cells, and a bit line precharge circuit and a transfer gate switch circuit which are connected to the local bit line pair. The local bit line pairs in a plurality of basic unit blocks are connected to a global bit line pair via the transfer gate switch circuit. The global bit line pair constitutes a layered bit line structure together with the local bit line pair. The global bit line pair is laid out to extend in the same direction and is twisted once or more in this extending direction.

Abstract: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.

Abstract: A memory arrangement includes a plurality of switching elements arranged in the form of a binary tree. The memory elements are supplied with data to be stored by the switching elements coupled to the leaves of the binary tree.

Abstract: Example embodiments relate to a semiconductor device and a method of fabricating the same. The device may include a semiconductor substrate including a peripheral region and a cell array region, wherein the substrate in the cell array region may be recessed lower than the peripheral region, a plurality of cell transistor layers stacked in the cell array region, and a plurality of peripheral circuit transistors formed in the peripheral region. The cell transistor layers may be formed in the cell array region at a lower level than the peripheral region.

Abstract: A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.

Abstract: Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B0 to B3 in a sector, in which a block address BA for selecting one of blocks B0 to B3 is held in block address buffer (BAB) 3. Holding operation is executed prior to reading or writing operation, and hence in subsequent reading operation or writing operation, re-input is not needed. Depending on the held block address BA, any one of selection signals YDn (n=0 to 3) is selected, and any one block is selected depending on the selection signal YDn. This state is maintained until the block address BA held in the block address buffer (BAB) 3 is rewritten, and therefore it is not required to enter or decode the block address BA on every occasion of reading and/or writing operation, so that the access operation can be executed promptly and at low current consumption.

Abstract: A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of an internal clock and generates a third count value. A first buffer uses the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after a first predetermined period. A second buffer uses the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after the first predetermined period.

Abstract: A duty cycle detector including a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a clock signal having a first duty cycle and to provide a first oscillating signal having a first period proportional to the first duty cycle. The second circuit is configured to receive an inverted clock signal that is the inverse of the clock signal and having a second duty cycle and to provide a second oscillating signal having a second period proportional to the second duty cycle. The third circuit is configured to provide first output signals that indicate the first duty cycle of the clock signal based on a first phase difference between the first oscillating signal and the second oscillating signal.

Abstract: According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location.

Abstract: Example embodiments of the present invention may include a printed circuit board, a method of manufacturing the printed circuit board, and a memory module/socket assembly. Example embodiments of the present invention may increase the number of contact taps on a memory module, in addition, a force required to insert the memory module into a module socket may be decreased.

Abstract: In one embodiment taught herein, a memory module selectively uses its write data mask input as a status output on which it provides status signaling to an associated memory controller. The memory module configures its data mask input as a status output at one or more times not conflicting with write operations. Correspondingly, the memory controller configures its write data mask output as a status input at such times, for receipt of status signaling from the memory module. In one embodiment, the memory module maintains a status register related to one or more operating conditions of the module, such as temperature, and signals status information changes to the memory controller by driving the module's data mask input. In response to such signaling, the memory controller initiates a read of the module's status register to obtain updated status information, and takes appropriate action, such as by changing the module's refresh rate.

Abstract: A composition for and a method of promoting the flow of a concrete slurry through a conduit is provided. The composition is preferably a liquid polymer mixture including water and polyacrylamide polymers. The composition, when mixed with a suitable quantity of water, is useful, in a method of priming a pump, and in pumping concrete slurry, and improves the flow of the slurry through a conduit.

Abstract: A tip adapted to be mounted to the downstream end of an extruder screw. The tip includes a nose section and an extruder screw mount section. The nose section includes an upstream face and a first and second downstream faces. The upstream face has a major plane that is substantially perpendicular to the longitudinal axis of the tip, is substantially flat, and has a substantially circular perimeter. The first and second downstream faces have major planes that are substantially flat. The major plane of the first downstream face is at an angle to the major plane of the second downstream face whereby they meet at a juncture located at the outer end of the tip. The extruder screw mount section includes means for attaching the tip to the extruder screw.

Abstract: Provided are a method and apparatus for continuously blending a chemical solution for use in semiconductor processing. The method involves the step of mixing a first chemical stream with a second chemical stream in a controlled manner to form a stream of a solution having a predetermined formulation. The apparatus allows one to practice the above method. The method and apparatus can accurately provide chemical solutions of desired concentration in a continuous manner. The invention has particular applicability in semiconductor device fabrication.

Abstract: An apparatus for dissolving a solid material in a liquid including a container for receiving the solid material and the liquid. A turbidimeter measures the turbidity of the liquid in the container. A blender stirs the liquid in the container until the turbidity thereof, as measured by the turbidimeter, falls below a predetermined level. A sensor gauges the level of liquid in the container and causes a valve to admit liquid into the container when the liquid level falls below a set point.

Abstract: An apparatus and method for combining multiple materials into a stream. The multiple materials may include both a major material and one or more minor materials. The minor materials are added using inlet tubes. The major and minor materials are added at transient or steady state flow rates, depending upon a command from a control signal. The apparatus and method utilize a control system which does not have flow control valves, flow control feedback loops or a dynamic mix tank. The actual flow rates track the commanded flow rates, but deviate by an error. The claimed arrangement provides a time-based error believed to be unobtainable in the prior art.

Abstract: An apparatus and method for combining multiple materials. The multiple materials may include both a major material and one or more minor materials. The major and minor materials are added at transient or steady state flow rates, depending upon a command from a control signal. The actual flow rates track the commanded flow rates, but deviate by an error. The claimed arrangement provides an instantaneous and time-based error believed to be unobtainable in the prior art.

Abstract: A mixer for analytical application mixes a container of fluid without a magnetic stir bar. A device for testing a liquid for particles can use the mixer. The mixing can occur in a sealed container, and liquid can be transmitted to the device from the sealed container.

Abstract: The Fresh Fruit Juice Blender is the only juice blender that mixes the fruit with the water manually without electrical current. The pieces of fruit are cut up and placed in the bottom of the blender. The internal are then placed in the blender and by manually moving the internal chopper up and down the fruit pieces are chopped up into a fruit mulch therefore blending with the water creating a fruit drink. The amount of chopping and blending will determine the strength of the drink. This is the only Manual Juice Blender that has a manual up and down manual chopper attached as part of the internal mechanism for creating a fruit drink. The blades attached to the manual shaft create the pulp and juice during the up and down movement from the cut up fruit pieces, allowing them to agitate upwards to the water. This blending with the water creates the fruit drink.

Abstract: A reaction block for mounting various round bottom flasks upon a laboratory, magnetic hot plate stirrer. An aluminum inner flask holder effectively conducts heat and does not interfere with a magnetic flux. A solid heat insulating material substantially surrounds and is spaced from the flask holder, in order to keep the reaction block at a safe temperature and provide easy gripping surface regions that extend completely around its circumference.

Abstract: A fluidic micromixer comprises a plurality of fluid inlets in communication with a mixing chamber, the plurality of fluid inlets being adapted to introduce into the chamber a corresponding plurality of distinct fluid streams. The mixing chamber comprises at least one surface patterned to define hydrophobic and hydrophilic regions spaced apart along a principal direction of fluid flow within the chamber from the fluid inlets to a fluid outlet, the regions being adapted to induce fluid flow in a direction transverse to the principal direction of fluid flow to mix the fluid streams. At least one of the hydrophobic regions may comprise microstructures patterned on the at least one surface. Also disclosed are a method for fabricating the micromixer, a method of mixing a plurality of fluid streams by vortex mixing or instability mixing, and a system comprising the micromixer, fluid reservoirs and a pump for generating flow of fluids from the reservoirs to the micromixer.

Abstract: A timepiece for the top of a surfboard comprising; a polymer pliable member which can be temporary attached to the top of a surfboard by surface adhesion; and an LCD timepiece affixed to the pliable member, said pliable member having a plurality of folds and snaps such that said pliable member can be formed into a wristwatch band.

Abstract: To provide a timepiece with calendar mechanism compactly constituting a drive mechanism for driving a plurality of date indicators and including the date indicators having date characters which are large and easy to see. A timepiece with calendar mechanism of the invention includes a first date indicator and a second date indicator for indicating a position of 1 of a date, a third date indicator for indicating a position of 10 of the date and a program wheel & pinion capable of respectively rotating the first date indicator, the second date indicator, the third date indicator intermittently based on operation of a drive mechanism. The date can be indicated by one of first date characters of the first date indicator and one of third date characters of the third date indicator, and the date can be indicated by one of second date characters of the second date indicator and one of the third date characters of the third date indicator.

Abstract: To provide a timepiece with calendar mechanism compactly constituting a drive mechanism for driving a plurality of date indicators and including the date indicators having date characters which are large and easy to see. A timepiece with calendar mechanism of the invention includes a first date indicator 512 and a second date indicator 522 for indicating a position of 1 of a date, a third date indicator 532 for indicating a position of 10 of the date and a program wheel 540 capable of respectively rotating the first date indicator 512, the second date indicator 522, the third date indicator 532 intermittently based on operation of a drive mechanism. The date can be indicated by one of first date characters of the first date indicator and one of third date characters of the third date indicator 532, and the date can be indicated by one of second date characters of the second date indicator 522 and one of the third date characters of the third date indicator 532.

Abstract: A timer device includes a timer housing. An electronic countdown circuit is disposed within the timer housing. The electronic countdown circuit is programmed to include at least one mode of operation. A display device is attached to the timer housing and in electronic communication with the electronic countdown circuit. The display device includes an LCD display and at least one flashable LED light. A power source is in electrical communication with the electronic circuit. At least one switch is in electrical communication with the electronic countdown circuit. The switch is adapted to select the mode of countdown operation.

Abstract: A method and system are disclosed for retrieving data from rotating media such as an optical disk, and storing that data in an image file or files which contain not only the data but also physical information about the media, including the angular location of each data sector along the rotating media's spiral track. The image file or files can then be copied onto a variety of diverse media, including semiconductor media (RAM, ROM, etc.), a hard disk residing on a computer, optical or magnetic media (CD-ROM, DVD, BD-ROM, HD-DVD, floppies, etc.), and the like.