Abstract: A flat panel display lowering an on-current of a driving thin film transistor (TFT), maintaining high switching properties of a switching TFT, maintaining uniform brightness using the driving TFT, and maintaining a life span of a light emitting device while the same voltages are applied to the switching TFT and the driving TFT without changing a size of an active layer. The flat panel display has a light emitting device, a switching thin film transistor including a semiconductor active layer having at least a channel area for transferring a data signal to the light emitting device, and a driving thin film transistor including a semiconductor active layer having at least a channel area for driving the light emitting device so that a predetermined current flows through the light emitting device according to the data signal, the channel areas of the switching TFT and the driving TFT having different directions of current flow.

Abstract: A method of manufacturing an electro-optical device, the electro-optical device having an electro-optical element formed by laminating a first electrode, an electro-optical layer, and a second electrode in sequence on a base body, the method of manufacturing the electro-optical device, including the steps of: forming an ultraviolet absorbing layer on the substrate by a vapor deposition method so as to cover the electro-optical element; and forming a gas barrier layer by a vapor deposition method using plasma so as to cover the ultraviolet absorbing layer.

Abstract: The present invention provides a nitride semiconductor device. The nitride semiconductor device comprises an n-type nitride semiconductor layer formed on a nitride crystal growth substrate. An active layer is formed on the n-type nitride semiconductor layer. A first p-type nitride semiconductor layer is formed on the active layer. A micro-structured current diffusion pattern is formed on the first p-type nitride semiconductor layer. The current diffusion pattern is made of an insulation material. A second p-type nitride semiconductor layer is formed on the first p-type nitride semiconductor layer having the current diffusion pattern formed thereon.

Abstract: A semiconductor driver circuit has a plurality of output bumps that are connected to respective electrodes for energizing electroluminescent devices by electric current supplied through the electrodes. The output bumps are arranged in a plurality of output bump rows. Each of the output bump rows includes a plurality of the output bumps.

Abstract: A plurality of LEDs are mounted on a substrate aggregation, a transparent layer is formed on the substrate aggregation. The transparent layer between adjacent divisions is removed to form an individual transparent layer and to form a groove around the individual transparent layer. The groove is filled with a reflector material to form a reflector layer. The reflector layer and the substrate are cut so as to form a reflector film on the outside wall of the individual transparent layer, thereby forming a plurality of LED devices.

Abstract: A semiconductor light emitting device is provided which comprises a metallic support plate 1; a semiconductor light emitting diode chip 2 mounted on a support surface 13a defined on an upper surface 13 of support plate 1; wiring conductors 4 mounted on side and upper surfaces 12, 13 of support plate 1 via insulators 6; and a plastic encapsulant 3 for sealing side and upper surfaces 12 and 13 of support plate 1 and a part of wiring conductors 4. As support plate 1 comprises at least one projection 16 extending from side surface 12 of support plate 1 through a notch 3a formed in plastic encapsulant 3 for outward exposure, heat from diode chip 2 can be efficiently diffused to the outside through projections 16 of support plate 1 extending through notch 3a of plastic encapsulant 3 for outward exposure, when heavy current flows through diode chip 2 through wiring conductors 4 for stronger lighting.

Abstract: The invention relates to a light source comprising a light-emitting element, which emits light in a first spectral region, and comprising a luminophore, which comes from the group of alkaline-earth orthosilicates and which absorbs a portion of the light emitted by the light source and emits light in another spectral region. According to the invention, the luminophore is an alkaline-earth orthosilicate, which is activated with bivalent europium and whose composition consists of: (2-x-y)SrOx(Ba, Ca)O (1-a-b-c-d)SiO2 aP2O5 bAl2O3 cB2O3 dGeO2: y Eu2+ and/or (2-x-y)BaO x((Sr, Ca)O (1-a-b-c-d)SiO2 aP2O5 bAl2O3 cB2O3 dGeO2: y Eu2+. The desired color (color temperature) can be easily adjusted by using a luminophore of the aforementioned type.

Abstract: A device for protecting I/O lines using low capacitance steering diodes (1200) and PIN or NIP diodes (1202), (1203) is disclosed. A low capacitance diode arrangement configured as steering diodes protect a signal line or input/output (I/O) port (1201) from high voltage transients by diverting or directing the transient to either the positive side of the power supply line (1204) or to ground (1205).

Abstract: An avalanche photodiode has improved low-noise characteristics, high-speed response characteristics, and sensitivity. The avalanche photodiode includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, a semiconductor multiplication layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a semiconductor light-absorbing layer interposed between the semiconductor multiplication layer and the second conductivity type semiconductor layer. The avalanche photodiode further comprises a multiplication suppressing layer which suppresses multiplication of charge carriers in the semiconductor light-absorbing layer, has a thickness of 0.6 ?m or less, and is located between the semiconductor light-absorbing layer and the second conductivity type semiconductor layer. The thickness of the semiconductor light-absorbing layer is 0.5 ?m or more.

Abstract: A semiconductor device has a sapphire substrate, a semiconductor layer made of GaN provided on the sapphire substrate, a multilayer film provided on the semiconductor layer, and an electrode in ohmic contact with the multilayer film. The multilayer film has been formed by alternately stacking two types of semiconductor layers having different amounts of piezopolarization or different amounts of spontaneous polarization and each containing an n-type impurity so that electrons are induced at the interface between the two types of semiconductor layers. This allows the contact resistance between the electrode and the multilayer film and a parasitic resistance in a current transmission path to be reduced to values lower than in a conventional semiconductor device.

Abstract: An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.

Abstract: In a semiconductor device an electric field is controlled in direction or angle relative to a gate, or a channel to adjust a gain coefficient of a transistor. In some embodiments, there are provided a first gate forming a channel region in a rectangle or a parallelogram, and a second gate forming a channel region substantially containing a triangle between the channel region formed by the first gate and each of a source region and a drain region. In some embodiments, there is included a channel region formed by the first gate that is sandwiched by the channel region formed by the second gate, all the channel regions together substantially forming a rectangle or a parallelogram. As such, a semiconductor device allowing a gain coefficient ? of an MOS transistor to be modulated by voltage in an analog manner can readily be produced by conventional processing technology and incorporated into any conventional LSIs configured by a CMOS circuit.

Abstract: An image sensor provided with: a plurality of photodiodes arranged on a surface of a semiconductor substrate, the photodiodes each including a first region of a first conductivity type provided on the semiconductor substrate, a second region of a second conductivity type provided on the first region, the second conductivity type being different from the first conductivity type, and a signal extraction region of the second conductivity type provided on the second region; and an isolation region which electrically isolates the second regions of each adjacent pair of photodiodes from each other, the isolation region including a first trench provided between the second regions of the adjacent photodiodes and an oxide film provided on the first trench in the vicinity of surfaces of the second regions and having a greater width than the first trench.

Abstract: A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is formed at least partially below the surface of the substrate and a photodiode is adjacent to the gate. The photodiode comprises a doped surface layer of a first conductivity type, and a doped region of a second conductivity type underlying the doped surface layer. The doped surface layer is at least partially above a level of the bottom of the gate.

Abstract: Disclosed is a solid state image pickup device including a Si substrate, a conductive pattern such as transfer-accumulation electrodes and a buffer wiring formed above the Si substrate, an insulating film provided above the Si substrate in the state of covering the conductive pattern, and a shunt wiring composed of a metallic pattern formed above the insulating film in the state of being connected to the buffer wiring via a contact window formed in the insulating film. The portion of the shunt wiring in the vicinity of the bottom surface of the contact window contains at least one of silicon metal oxide or silicon metal nitride.

Abstract: A solid-state imaging device of a three-transistor pixel configuration having no selection transistor has a problem of a non-selection hot carrier white point, which is specific to this apparatus. A bias current during a non-reading period of pixels is made to flow to a pixel associated with an immediately previous selection pixel, for example, the immediately previous selection pixel itself. As a result, dark current only for one line occurs in each pixel, and the dark current for one line itself can be reduced markedly. Consequently, defective pixels due to non-selection hot carrier white points can be virtually eliminated.

Abstract: A transistor switch for a system operating at high frequencies is provided. The transistor switch comprises a graded channel region between a source region and a drain region, the graded channel region configured for providing a low resistance to mobile negative charge carriers moving from the source region to the drain region, wherein the graded channel comprises at least two doping levels.

Abstract: In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.

Abstract: A solid-state imaging device is provided in which noise to an image signal is restrained and miniaturization is facilitated in a peripheral circuit formation region. A solid-state imaging device includes a pixel formation region 4 and a peripheral circuit formation region 20 formed in the same semiconductor substrate; in the peripheral circuit formation region 20 a first element isolation portion is formed of an element isolation layer 21 in which an insulation layer is buried in a semiconductor substrate 10; in the pixel formation region 4 a second element isolation portion made of an element isolation region 11 formed inside the semiconductor substrate 10 and an element isolation layer 12 projecting upward from the semiconductor substrate 10 is formed; and a photoelectric conversion element 16 (14, 15) is formed extending to a position under the element isolation layer 12 of the second element isolation portion.

Abstract: In a piezoelectric element having a piezoelectric film sandwiched between a lower electrode and an upper electrode, the lower electrode and/or the upper electrode and the piezoelectric film comprise perovskite oxide and a contact interface between the lower electrode and/or the upper electrode and the piezoelectric film does not exist and a region where crystals of the lower electrode and/or the upper electrode and crystals of the piezoelectric film are mixed exists between the lower electrode and/or the upper electrode and the piezoelectric film.

Abstract: A ferroelectric material for forming a ferroelectric that is described by a general formula ABO3, includes an A-site compensation component which compensates for a vacancy of an A site, and a B-site compensation component which compensates for a vacancy of a B site.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor structure formed above the semiconductor substrate and comprising a first electrode, a second electrode provided below the first electrode, a third electrode provided below the second electrode, a first dielectric film provided between the first electrode and the second electrode, and a second dielectric film provided between the second electrode and the third electrode, an insulating film covering the capacitor structure and having a first hole reaching the first electrode, a second hole reaching the second electrode, and a third hole reaching the third electrode, a first conductive connection electrically connecting the first electrode and the third electrode and having portions buried in the first and third holes, and a second conductive connection formed-separately from the first conductive connection and having a portion buried in the second hole.

Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

Abstract: A silicon-on-insulator (SOI) memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs.

Abstract: A nonvolatile semiconductor memory device has a cell which includes a drain diffusion region and a source diffusion region formed on a surface layer of a semiconductor substrate; a first insulating film formed between the source diffusion region and the drain diffusion region; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; a first control gate formed on the second insulating film; a third insulating film formed on the first control gate and a sidewall thereof and on a sidewall of the floating gate; and a second control gate formed on the first control gate with the third insulating film interposed therebetween.

Abstract: A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.

Abstract: A semiconductor device has a structure that reduces the parasitic capacitance by using a film with a low relative dielectric constant as the side wall material of the gate. The material with a low relative dielectric constant is preferably a material whose relative dielectric constant is less than the relative dielectric constant of an oxide film, i.e., less than about 3.9.

Abstract: An integrated circuit device includes a substrate that has a trench formed therein. An isolation layer is disposed in the trench and covers a first sidewall portion of the trench. A gate electrode is disposed on a second sidewall portion of the trench.

Abstract: High side extended-drain MOS driver transistors (T2) are presented in which an extended drain (108, 156) is separated from a first buried layer (120) by a second buried layer (130), wherein an internal or external diode (148) is coupled between the first buried layer (120) and the extended drain (108, 156) to increase the breakdown voltage.

Abstract: Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.

Abstract: A method of manufacturing a semiconductor device substrate is disclosed, which comprises forming a mask layer patterned on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer deposited thinner on the semiconductor substrate than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.

Abstract: A semiconductor contact connection structure and the method for forming the same are disclosed. The connection structure has a first semiconductor device formed on an insulator substrate. A non-conducting gate interconnect layer is formed on the insulator substrate for connecting to a gate of a second semiconductor device, and a silicide layer formed on the gate interconnect layer and an active region of the first semiconductor device for making a connection thereof.

Abstract: To control the uneven distribution of current density and reduce the area of an ESD protection circuit in an SCR-type ESD protection device. An N-type well 11, and P-type wells 12a and 12b disposed oppositely and adjacent to the N-type well 11, with the N-type well 11 interposed between them, are formed on the surface of a semiconductor substrate. A high concentration N-type region 15a is formed on the surface of the P-type well 12a, a high concentration N-type region 15b is formed on the surface of the P-type well 12b, and each of them is grounded. Further, a high concentration P-type region 14a is formed, oppositely to the high concentration N-type region 15a, on the surface of the N-type well 11, and a high concentration P-type region 14b is formed, oppositely to the high concentration N-type region 15b, on the surface of the N-type well 11, and each of them is connected to an I/O pad.

Abstract: A semiconductor device includes a substrate, MOS transistors in the substrate, and a dielectric layer on the MOS transistors. Contact holes are formed through the dielectric layer to provide electrical connection to the MOS transistors. An etch-stop layer is between the MOS transistors and the dielectric layer. The etch-stop layer includes a first layer of material having a first residual stress level and covers some of the MOS transistors, and a second layer of material having a second residual stress level and covers all of the MOS transistors. The respective thickness of the first and second layers of material, and the first and second residual stress levels associated therewith are selected to obtain variations in operating parameters of the MOS transistors.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

Abstract: A first region 11 functioning as a transistor includes a drain region 111, a body region 112 formed over the drain region 111, a source region 113A formed over the body region 112 and a trench formed through the body region 112 and having a gate electrode 120 buried therein. A source region 113B is formed over the body region 112 extending in a second region 12.

Abstract: A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.

Abstract: A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each particle is covered with a second material (e.g., silver oxide) and formed of a third material (e.g., silver). The second material functions as a barrier against passage of electric charges, and the third material has a function of retaining electric charges. The third material is introduced into the medium by, for example, a negative ion implantation method.

Abstract: A method for making circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor includes a gate insulating structure comprised of a first conducting oxide layer comprised of indium oxide compounds positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer.

Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape.

Abstract: A method used to form a semiconductor device comprises forming a polysilicon layer, forming a conductive barrier layer on the polysilicon layer, then forming a conductive nitride layer on the conductive barrier layer. Next, a conductive amorphous layer is formed on the conductive barrier layer, and an elemental metal layer is formed on the conductive amorphous layer. Without the conductive amorphous layer the elemental metal layer would form on the conductive nitride layer as a small grained, high resistance layer, while it forms on the conductive amorphous layer as a large grained, low resistance layer. A semiconductor device which may be formed using this method is also described.

Abstract: A semiconductor light-receiving device includes a plurality of first conductive type second semiconductor layers formed on a first surface of a first conductive type semiconductor substrate apart from each other. Each of the first conductive type second semiconductor layers is surrounded by a second conductive type third semiconductor layer with a first semiconductor layer therebetween. The first semiconductor layer has a lower impurity concentration than the second semiconductor layers. By completely depleting the first semiconductor layer occupying a large area within the light-receiving surface, the light entering the light-receiving surface is enabled to contribute to a photoelectric current while reducing the light absorption in the second semiconductor layers, so that the sensitivity characteristics of the semiconductor light-receiving device can be made superior and the production cost can be lowered.

Abstract: An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to control the imaging operations. The data-input can be based upon variations in light color, value, intensity, and patterning, or any combinations of the foregoing, for the download of information to the device.

Abstract: A cubic element of photonic crystal is integrally formed on the surface of a photo-detection element, and a portion of the photonic crystal cubic element is irradiated with ultraviolet rays thereby to change the refractive index of the portion of the cubic element that has been irradiated with ultraviolet rays. Alternatively, by causing globular particles having different refractive indices to eject on the surface of the photo-detection element from an ink-jet apparatus having a nozzle provided with a temperature control part by controlling temperature of the nozzle to form a laminate of globular particle layers having different refractive indices, a photonic crystal lens is integrally formed on the surface of the photo-detection element.

Abstract: It is an object of the invention to provide an improved solid image-pickup device which is compact in size and low in production cost. The solid image-pickup device is so formed that its semiconductor substrate has on its surface an image-pickup area having a plurality of light sensors arranged thereon. A transparent plate having the same shape and the same size as those of the semiconductor substrate when viewed as a plan view is bonded to the surface of the semiconductor substrate. A plurality of bonding pads are formed on the surface of the semiconductor substrate and arranged around the image-pickup area. Further, a plurality of through holes are formed through the semiconductor substrate, extending from the lower surfaces of the bonding pads to the back surface of the semiconductor substrate. An insulating film is tightly attached to the inner surface of each of the through holes, while another insulating film is tightly attached to the back surface of the semiconductor substrate.

Abstract: A primary object of the present invention is to provide a photoelectric conversion apparatus with less leak current in a floating diffusion region. In order to obtain the above object, a photoelectric conversion apparatus according to the present invention includes a photodiode for converting light into a signal charge, a first semiconductor region having a first conductivity type, a floating diffusion region formed from a second semiconductor region having a second conductivity type for converting the signal charge generated by the photodiode into a signal voltage, the second semiconductor region being formed in the first semiconductor region, and an electrode formed above the first semiconductor region through an insulating film and having an effect of increasing a concentration of majority carriers in the first semiconductor region, in which the electrode is not formed above a depletion region formed from the second semiconductor region.

Abstract: The present invention provides an integrated circuit. The integrated circuit has a plurality of chip areas. The integrated circuit also has a plurality of temperature sensors, at least one per chip area. The temperature sensors generate a voltage proportional to the measured temperature. A voltage comparator compares the voltage output of the plurality of temperature sensors. The voltage comparator is further employable to generate a signal if the difference between the voltages generated by the plurality of temperature sensors exceeds a threshold.

Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.