Patents Issued in March 6, 2007
  • Patent number: 7187205
    Abstract: A storage element (10) includes a first latch (12) and a second latch (14). The first latch (12) is coupled to a first power supply voltage terminal for receiving a first power supply voltage. The second latch (14) is coupled to a second power supply voltage terminal. The second power supply voltage terminal for receiving a second power supply voltage that is lower than the first power supply voltage. During a normal mode of operation, the second power supply voltage is not provided to the second latch. During a low power mode of operation data is transferred from the first latch to the second latch and the first latch is powered down. The data is retained by the second latch while in low power mode.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: March 6, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, David R. Bearden, Arthur R. Piejko
  • Patent number: 7187206
    Abstract: Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently to achieve multiple power levels and multiple levels of pre-emphasis while maintaining a substantially constant propagation delay in a signal path of the serial link transmitter. Further aspects include providing a bypass path in the prebuffer stage circuitry to implement a controllable idle state in the segments and tail current and resistive load elements in the prebuffer circuitry as sectioned portions for slew rate control capability. Also included is provision of a control element with pre-emphasis delay circuitry in the transmitter signal path to allow inversion of a last delayed bit of the pre-emphasis delay circuitry to achieve a polarity change of a pre-emphasis weight.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: March 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Clements, Carrie E. Cox, Hayden C. Cranford, Jr.
  • Patent number: 7187207
    Abstract: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: March 6, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Matthew D. Rowley
  • Patent number: 7187208
    Abstract: A low voltage positive emitter coupled logic (LV-PECL) buffer fabricated in the complimentary oxide metal silicon (CMOS) process. The LV-PECL buffer in CMOS is operable for a wide frequency range from DC to frequencies as high as 800 MHZ in 0.5 um process. Synchronized feedforward logic is utilized without the need for a feedback loop. N-MOSFET's, which are faster than P-MOSFET's, are used for the implementation of switched current sources. The switched current sources deliver a pull-up current variable in time and as a result have more than two values. The pull-up current is sharply increased in value during the output waveform transition times in an impulse manner.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: March 6, 2007
    Assignee: Phaselink Semiconductor Corporation
    Inventor: Pierre Paul Guebels
  • Patent number: 7187209
    Abstract: A domino register including an evaluation circuit, a write circuit, an inverter, a keeper circuit, and output logic. The evaluation circuit pre-charges a first node and evaluates a logic function for controlling a state of the first node when the clock signal goes high. The write circuit drives a second node high if the first node is low and drives the second node low if the first node stays high during evaluation. The inverter inverts the second node to control the state of a third node. The keeper circuit keeps the second node high while the third node and clock signals are both low and keeps the second node low while the third and first nodes are both high. The high and low paths of the keeper circuit are otherwise disabled, including when the write circuit changes state. Thus, the write circuit does not have to overcome a keeper device.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: March 6, 2007
    Assignee: VIA Technologies, Inc.
    Inventor: Raymond A. Bertram
  • Patent number: 7187210
    Abstract: A P-domino register includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to a pulsed clock signal, and evaluates a logic function according to the states of at least one data signal and the pulsed clock signal, where the domino stage pre-charges a pre-charged node low when the pulsed clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the pulsed clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the pulsed clock signal is low, where a setup state of the at least one data signal is provided to the domino stage when the pulsed clock signal is high.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: March 6, 2007
    Assignee: Via Technologies, Inc.
    Inventors: James R. Lundberg, Raymond A. Bertram
  • Patent number: 7187211
    Abstract: A P-domino latch includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal, and evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node low when the approximately symmetric clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the approximately symmetric clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the approximately symmetric clock signal is low, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is low.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: March 6, 2007
    Assignee: Via Technologies, Inc.
    Inventors: James R. Lundberg, Raymond A. Bertram
  • Patent number: 7187212
    Abstract: A system and method is disclosed for providing a fast turn on bias circuit that permits a fast transition from an idle “power down” state to an active “power up” state in current mode logic (CML) transmitter output circuits. The invention comprises a capacitor coupled to a bias transistor and a charge switch circuit for controlling the operation of the capacitor. The capacitor has a value of capacitance that is equal in magnitude and opposite in sign to the Miller coupling capacitance in the bias transistor. The capacitor compensates for the Miller coupling capacitance within the bias transistor in less than ten nanoseconds. This permits a CML transmitter to more quickly restart the transmission of data after an active state has been initiated.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: March 6, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Alan E. Segervall, Laurence D. Lewicki
  • Patent number: 7187213
    Abstract: The present invention provides a semiconductor circuit capable of effectively applying a filter function to both of L-level noise superimposed during originally H signal periods and H-level noise superimposed during originally L signal periods. An input signal branches off into two and one of them is inputted through signal inverting means to a first delay circuit including a first capacitor. The other is inputted to a second delay circuit including a second capacitor. An output signal from the first delay circuit and an output signal from the second delay circuit are inputted to separate input terminals of a flip-flop.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: March 6, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Yoshida, Kazuhito Fujii
  • Patent number: 7187214
    Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: March 6, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho
  • Patent number: 7187215
    Abstract: Embodiments of the current-mode track and hold circuit comprise a cascode input stage, a dynamic biasing stage, a cascode output stage, and a switch operable to interconnect the input stage and the output stage. The input stage is connected to receive an input current. The dynamic biasing stage is connected to receive a scaled version of the input current as a dynamic biasing current and dynamically biases the input stage in response to the dynamic biasing current. Dynamically biasing the track-and-hold circuit in response to a dynamic biasing current that is a scaled version of the input current significantly increases the maximum peak-to-peak voltage swing allowed at the input of the track-and-hold circuit and enables a corresponding increase in signal-to-noise ratio. These benefits are obtained at the expense of only a small increase in power consumption.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: March 6, 2007
    Assignee: Agilent Technologies
    Inventor: Brian D. Setterberg
  • Patent number: 7187216
    Abstract: A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: March 6, 2007
    Assignee: Silicon Laboratories Inc.
    Inventors: Lizhong Sun, Douglas F. Pastorello, Richard J. Juhn, Axel Thomsen
  • Patent number: 7187217
    Abstract: A clock frequency divider is provided which has first through Pth (where P is an integer) sub-counters, each capable of counting M+1 clock pulses and provided in parallel, and first through Pth clock signals are provided to the sub-counters, which has same period as a reference clock signal and are sequentially shifted by 1/P of the period of the reference clock signal. Of the first through Pth sub-counters, when the Nth sub-counter (where N is an arbitrary number from 1 to P) finishes counting a prescribed number M of reference clock pulses, all the other sub-counters are initialized, or, at least the (N+1)th sub-counter is initialized.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: March 6, 2007
    Assignee: Fujitsu Limited
    Inventor: Masazumi Marutani
  • Patent number: 7187218
    Abstract: A reset generator circuit has an oscillator circuit and a delay circuit having a clock signal input, which is connected to an output of the oscillator circuit. The delay circuit can be activated by a control signal at a control input and is designed for outputting a first signal after a first time period and for outputting a second signal after a time period after the outputting of the first signal. The reset generator circuit comprises a generator circuit designed for outputting a reset signal in the event of detection of the first signal up to the detection of the second signal. Furthermore, the reset generator circuit contains a comparison device designed for a comparison of a supply potential with a potential threshold value and for outputting the control signal in the event of the potential threshold value being exceeded. The delay circuit and the generator circuit can be controlled by the comparison device.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: March 6, 2007
    Assignee: Infineon Technologies AG
    Inventor: Timo Gossmann
  • Patent number: 7187219
    Abstract: A system and method for providing a clock-independent reset signal based on supply voltage threshold levels is described. The trip points or predefined voltage levels where the power-on-reset circuit behavior reverses (which controls the reset signal) is determined by the dimensions of the transistors selected for the voltage dividers. The system and method described allows for a clock-independent stable power-up phase while consuming a very small area of a circuit board and, in particular, on integrated circuits.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: March 6, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Alf Olsen
  • Patent number: 7187220
    Abstract: Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: March 6, 2007
    Assignee: Nvidia Corporation
    Inventors: Jonah M. Alben, Sean Jeffrey Treichler, Adam E. Levinthal
  • Patent number: 7187221
    Abstract: A method for adjusting the relative phases of two signals includes receiving first and second signals, which may, for example, be derived from a differential clock signal. A duty cycle error between the first signal and the second signal is detected by comparing a phase component of the first signal with a phase component of the second signal. This duty cycle error can then be corrected by delaying the second signal by an amount based upon a result derived from the comparing.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: March 6, 2007
    Assignee: Infineon Technologies AG
    Inventors: Joonho Kim, Jung Pill Kim, Alessandro Minzoni
  • Patent number: 7187222
    Abstract: A CML master-slave latch incorporates logic into its master latching circuitry to incorporate a multiplexing function into the flip-flop. The multiplexing logic makes use of the pull-up loads and current source of the master latching circuitry. In this manner the pull-up loads and current source typically required for a stand-alone multiplexor are eliminated. Subsequently, the size of the present hybrid master-slave latch is smaller and consumes less power than a traditional combination of an independent multiplexor and master-slave latch. Since the master latching circuitry feeds only into the slave latching circuitry, the pull-up loads and the current sources of the master latching circuitry and slave latching circuitry may be optimized separately for achieving faster performance or less power consumption.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: March 6, 2007
    Assignee: Seiko Epson Corporation
    Inventors: David Meltzer, Muralikumar A. Padaparambil
  • Patent number: 7187223
    Abstract: In one embodiment, a comparator is provided with a first differential input stage that receives an input voltage and a reference voltage and produces a first differential output, and a second differential input stage that has differential inputs and produces a second differential output. A comparator stage produces a comparator output in response to the first and second differential outputs. The comparator also has a hysteresis control circuit, the components of which include 1) a resistor and a hysteresis regulating voltage input, coupled between the differential inputs of the second differential input stage, 2) first and second current generators, and 3) at least one switch, under control of the comparator output, to alternately enable different combinations of the first and second current generators, thereby inducing a first or a second current through the resistor.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: March 6, 2007
    Assignee: Avago Technologies ECBU (IP) Singapore Pte. Ltd.
    Inventors: Kok-Soon Yeo, Lian-Chun Xu, Chee-Keong Teo, John Julius de Leon Asuncion, Wai-Keat Tai
  • Patent number: 7187224
    Abstract: Embodiments of the present invention relate to a circuit that varies the delay time of a clock signal in response to a frequency of the clock signal. The circuit may include a sensor and a delay circuit. The sensor may output a determination of the frequency of the clock signal. The delay time of the delay circuit may be responsive to the determination of a frequency of the clock signal. Accordingly, when the frequency of a clock signal varies, a delay of that clock signal can be varied to accommodate for the change in frequency.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: March 6, 2007
    Assignee: Intel Corporation
    Inventor: Moty Mehalel
  • Patent number: 7187225
    Abstract: This invention provides an electronic control unit is capable of suppressing electromagnetic noise having a frequency band used in a portable wireless apparatus, and capable of exhibiting a noise resistance property against electromagnetic noise. The electronic control unit including a constant voltage power supply circuit portion, an analog signal inputting circuit portion, and a conversion processing circuit portion, an analog sensor and a driving power supply being connected to the outside, and the unit being connected to the analog sensor through a power supply line and a signal line, in which the analog signal inputting circuit portion includes a current limiting circuit portion, an integrating circuit portion, a current limiting resistor, a signal noise absorbing circuit, and a first bypass capacitor, and capacitance (C1) and parasitic inductance (L1) of the first bypass capacitor are set in a range of 7×106<1/[2??(L1×C1)]<35×106.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: March 6, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masaharu Yuhara, Yasuhiro Shiraki, Kazuhito Okishio, Hiroshi Nakamura, Hisato Umemaru, Yoshimitsu Takahata, Yasuaki Gotoh
  • Patent number: 7187226
    Abstract: An anti-cross conduction driver control circuit and method prevent the occurrence of race conditions and avoid cross-conduction between series-connected power devices, typically MOSFETs, controlled in accordance with the present invention. Individual state machines are connected across the inputs and outputs of each power device driver, and are arranged to accurately determine when the driver has completed a task requested of it. Each state machine produces a “lockout” signal based on driver status, which is used to inhibit the operation of the opposite driver under prescribed conditions, and to thereby prevent cross-conduction between the series-connected power devices.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: March 6, 2007
    Assignee: Analog Devices, Inc.
    Inventor: Jonathan M. Audy
  • Patent number: 7187227
    Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: March 6, 2007
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yohtaro Umeda, Atsushi Kanda
  • Patent number: 7187228
    Abstract: An antifuse, which has a programmable material disposed between two conductive elements, is programmed using multiple current pulses of opposite polarity. The first pulse has a current that is insufficient to fully program the antifuse, i.e., produce a desired level of resistance. In one embodiment the first pulse is current limited. The first pulse advantageously drives a conductive filament from one conductive element through the antifuse material, which may be, e.g., amorphous silicon. The conductive filament from the first pulse, however, has a limited cross sectional area. A programming pulse having the same voltage with opposite polarity and a current with increased magnitude is used to drive material from the other conductive element into the antifuse material, which increases the cross sectional area of the conductive filament thereby reducing resistance. Additional programming pulses, as well as current limited pulses, may be used if desired.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: March 6, 2007
    Assignee: Quicklogic Corporation
    Inventors: Rajiv Jain, Richard J. Wong
  • Patent number: 7187229
    Abstract: An active filter for reducing the common mode current in a pulse width modulated drive circuit driving a load, said drive circuit comprising an a-c source, a rectifier connected to said a-c source and producing a rectified output voltage connected to a positive d-c bus and a negative d-c bus, a PWM inverter having input terminals coupled to said positive d-c bus and negative d-c bus and having a controlled a-c output, a load driven by said a-c output of said PWM inverter, a ground wire extending from said load, and a current sensor for measuring the common mode current in said drive circuit in said ground wire, said current sensor producing an output current related to said common mode current, said active filter comprising a first and second MOSFET transistor, each having first and second main electrodes and a control electrode, and an amplifier driving a respective one of the transistors; said first electrode of said first and second transistor coupled to a common node, said second electrodes of said first
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: March 6, 2007
    Assignee: International Rectifier Corporation
    Inventor: Brian R. Pelly
  • Patent number: 7187230
    Abstract: The present invention provides a method for using transferred-impedance filtering in RF (radio frequency) receivers (e.g., inside of a mobile communication device), wherein said filtering can be done with MOS-switches transferring impedance of a regular RC or RCL circuit to RF frequency filtering inside an RFIC (radio frequency integrated circuit).
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: March 6, 2007
    Assignee: Nokia Corporation
    Inventor: Sami Vilhonen
  • Patent number: 7187231
    Abstract: Apparatus, methods and articles of manufacture for multiband transmitter power amplification are provided wherein one or more amplifying devices, of which at least one may be one or more current sources, have impedances matched for different input and output frequencies by way of various impedance matching circuits.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: March 6, 2007
    Assignees: M/A-COM, Inc., M/A-COM Eurotec, B.V.
    Inventors: Finbarr J. McGrath, Eugene Heaney, Pierce J. Nagle, Andrei V. Grebennikov
  • Patent number: 7187232
    Abstract: A feed forward amplifier and method of amplification are disclosed. The amplifier output is used to generate a pilot signal via feedback using uncancelled noise in the amplifier output. An automatic level control circuit maintains the pilot signal at a substantially constant level when the detected uncancelled noise in the amplifier output is above a threshold level. The generated pilot signal strength is allowed to vary when the detected uncancelled noise in the amplifier output is below the threshold and disappears automatically when the amplifier is aligned.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: March 6, 2007
    Assignee: Powerwave Technologies, Inc.
    Inventors: Richard Neil Braithwaite, Matthew J. Hunton
  • Patent number: 7187233
    Abstract: An audio amplifier system includes at least a pair of DC power supplies, a floating bridge current gain output section, and a differential voltage gain input section that draws operating current from the DC power supplies through floating DC current regulators. The included current regulators reject power supply noise and modulation and provide a floating current path for establishing positive and negative operating voltages for the voltage gain section. Cross-coupled interstage loading enables nearly rail-to-rail output voltage swing while providing local feedback around the output section for reduced distortion and improved output load control. The floating current regulators in the circuit exhibit enhanced performance as a result of suppressed operating voltage fluctuations.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: March 6, 2007
    Inventor: Joseph Norman Berry
  • Patent number: 7187234
    Abstract: A linearizer for an amplifier includes an adaptation controller having M monitor signals as inputs. The controller outputs M control settings. The adaptation controller determines M uncorrelated adjustment settings from the M monitor signal inputs. Using the M uncorrelated adjustment settings, the controller adjusts the M control settings for the linearizer.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: March 6, 2007
    Assignee: Andrew Corporation
    Inventors: James K. Cavers, Thomas Johnson
  • Patent number: 7187235
    Abstract: The static bias current of the output stage circuit of the class AB rail-to-rail operational amplifier is controlled by the external bias control signals. The class AB rail-to-rail operational amplifier receives the external bias control signals and controls the bias voltage of the output stage circuit, and thus the static bias current of the output stage circuit may be controlled. The class AB rail-to-rail operational amplifier may further include a frequency compensation circuit for compensating high frequency characteristics of the operational amplifier.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: March 6, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyeong-Tae Moon
  • Patent number: 7187236
    Abstract: An operational amplifier input stage provides a symmetrical rail-to-rail input common-mode voltage without turning off either pair of complementary differential input transistors. Secondary, or surrogate, transistor pairs assume the function of the complementary differential transistors. The circuit also maintains essentially constant transconductance, constant slew rate, and constant signal-path supply current as it provides rail-to-rail operation.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: March 6, 2007
    Assignee: UT-Battelle, LLC
    Inventors: Charles Lanier Britton, Jr., Stephen Fulton Smith
  • Patent number: 7187237
    Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: March 6, 2007
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Todd E. Humes, Ronald A. Oliver, William T. Colleran, Scott A. Cooper
  • Patent number: 7187238
    Abstract: An amplifier circuit includes a first multiple gate field-effect transistor having a source terminal, a drain terminal, at least one signal gate terminal for receiving an input signal and at least one control gate terminal for receiving a control signal, and a second multiple gate field-effect transistor having a source terminal, a drain terminal, at least one signal gate terminal connected to the signal gate terminal of the first multiple gate field-effect transistor, and a control gate terminal connected to the control gate terminal of the first multiple gate field-effect transistor, the signal gate terminal of the second multiple gate field-effect transistor being connected to that source terminal/drain terminal of the second multiple gate field-effect transistor which is closer to the signal gate terminal of the second multiple gate field-effect transistor.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: March 6, 2007
    Assignee: Infineon Technologies AG
    Inventor: Robert Thalhammer
  • Patent number: 7187239
    Abstract: A multi-band low noise amplifier capable of operating in a plurality of band modes includes a plurality of input amplifiers respectively corresponding to the plurality of band modes and an output amplifier. Each input amplifier includes a receiving port for receiving a corresponding input signal in the band mode. The output amplifier includes at least a lowest-impedance port being a lowest-impedance node of the multi-band low noise amplifier and an output port for outputting the input signal processed by the output amplifier. The output amplifier is coupled to the plurality of input amplifiers at the lowest-impedance port.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: March 6, 2007
    Assignee: Mediatek Incorporation
    Inventor: En-Hsiang Yeh
  • Patent number: 7187240
    Abstract: An integrated electronic circuit comprises at least first and second variable resonator elements that can be tuned by means of an electric signal (Vtune) and that are arranged on the same silicon substrate, and that are respectively integrated into a Master circuit and a Slave circuit. Each resonator element is associated with a first inductive partner element set in the vicinity of the resonant and antiresonant frequencies; and with a second capacitive partner element, at least one of said partner elements being adjustable by means of said electric signal (Vtune). Controlling both partner elements could be done either by means of an adjustable capacitor, as a varactor, or by means of an inductor, passive or active, fixed or variable.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: March 6, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Andreia Cathelin, Stephane Razafimandimby, Didier Belot, Jean-François Carpentier
  • Patent number: 7187241
    Abstract: A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: March 6, 2007
    Assignee: Silicon Laboratories Inc.
    Inventors: Jerrell Hein, Axel Thomsen
  • Patent number: 7187242
    Abstract: Charge current in a charge pump of a phase locked loop is equalized by controlling one of the direct current sources with a feedback signal derived from the common mode voltage of a fully differential phase locked loop filter.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: March 6, 2007
    Assignee: Zarlink Semiconductor AB
    Inventor: Magnus Karl-Olof Karlsson
  • Patent number: 7187243
    Abstract: A delay circuit according to embodiments of the present invention capable of operating over a wide range of frequencies is presented. Embodiments of the invention minimize or eliminate parasitic capacitance at the output terminals that arise from switching elements used to selectively add capacitive elements to the circuit to vary the operating frequency range. A ring oscillator using embodiments of the delay circuit according to the present invention is also presented. A sequence of an integral number of delay circuits according to the present invention is coupled in series to form a ring oscillator. In some embodiments the delay circuit or a ring oscillator incorporating the delay circuit may be fabricated as an integrated circuit.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: March 6, 2007
    Assignee: Asahi Kasei Microsystems Co. Ltd.
    Inventor: Yoshiaki Konno
  • Patent number: 7187244
    Abstract: An oscillator for a power converter control outputs a pulse train based on a charging time of a capacitor linked to a variable current source. A digital to analog converter (DAC) controls the variable current source in conjunction with a switch to determine the charging time of the capacitor. By varying the digital DAC input, the charging time of the capacitor is modified, thereby modifying the frequency of the pulse train. A comparator compares the capacitor voltage to a toggled threshold, which switches depending on whether the capacitor is charging or discharging. The comparator output supplies the pulse train that can be used in a half bridge switching arrangement for the power converter, which can also serve as an electronic ballast for a lamp.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: March 6, 2007
    Assignee: International Rectifier Corporation
    Inventors: Thomas J. Ribarich, Peter Green, Muthu Subaramanian
  • Patent number: 7187245
    Abstract: Circuits and methods for controlling the amplitude of oscillation of a crystal. In one example, a circuit may include a peak detector; a first voltage-to-current converter; a first current-to-voltage converter coupled with the first voltage-to-current converter; a second voltage-to-current converter; a second current-to-voltage converter coupled with the second voltage-to-current converter; and a differential amplifier; wherein a ratio between a size of first voltage-to-current converter and a size of the second voltage-to-current converter is used to control the gain of the circuit.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: March 6, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventor: Mike McMenamy
  • Patent number: 7187246
    Abstract: In the case of a voltage-controlled LC oscillator (4), the effects of supply voltage fluctuations are reduced according to the invention, due to the fact that a stabilized voltage source (3) is assigned to the LC oscillator (4), which supplies the LC oscillator (4) with a stabilized voltage. This in particular is the case if the LC oscillator (4) is integrated together with other circuit components in a semiconductor and heavy noise or strong disturbances occur on supply voltage lines (1, 2). Advantageously, the stabilized voltage source (3) is formed by an operational amplifier (6), after which a driver transistor (5) is positioned, whereby the operational amplifier is subjected to a reference voltage (7).
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 6, 2007
    Assignee: Infineon Technologies AG
    Inventor: Christoph Sandner
  • Patent number: 7187247
    Abstract: A variable capacitance network is disclosed, comprising a plurality of capacitance arms connected in parallel with each other between first and second terminals of the network. Each capacitance arm has a varactor and a series capacitor in series with the varactor A control input applies a common control signal to the junctions between the varactors and their associated series capacitors, to allow for simultaneous control of each varactor.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: March 6, 2007
    Assignee: Intel Corporation
    Inventors: Colin Leslie Perry, Stephen John Parry, Alessandro F. Deidda, Christopher R. Shepherd
  • Patent number: 7187248
    Abstract: A differential oscillator circuit, including an oscillator having a first side and a second side and bias circuitry for applying a bias voltage to the first and second sides of the oscillator wherein the bias circuitry is arranged such that, upon start-up, the bias voltage is not applied to the second side of the oscillator until after the first side of the oscillator by a delay period.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: March 6, 2007
    Assignee: Sony United Kingdom Limited
    Inventor: Peter Wardlow Shadwell
  • Patent number: 7187249
    Abstract: In one aspect, a signal path is described. The signal path has a nominal impedance over a specified bandwidth and interconnects a port of a microwave circuit package and a microwave component mounted in the microwave circuit package. The signal path includes an inductive transition and first and second capacitive structures. The inductive transition extends from a first point on the signal path to a second point on the signal path and has an excess impedance above the nominal impedance. The first and second capacitive structures respectively shunt the first and second points on the signal path to compensate the excess impedance of the inductive transition. The inductive transition and the first and second capacitive structures approximate a filter having an impedance substantially matching the nominal impedance over the specified bandwidth.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: March 6, 2007
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Dean B. Nicholson, Reto Zingg, Keith W. Howell, Eric R. Ehlers
  • Patent number: 7187250
    Abstract: A coupler (10) having a first line (1) and a second line (2) also comprises a resonant structure (3) including a capacitor (5) and an inductor (4). The coupler (10) thus delivers a coupling signal S31 that is substantially frequency independent over a frequency domain above the resonance frequency of the resonant structure (3). Also, the signal S31 has a high degree of directivity. The coupler (10) can be provided as part of an integrated electronic component, such as a multilayer substrate, a thin-film module or an IC. It can be applied in an electronic device (100) between a power amplifier (101) and an antenna (103). The coupling signal S31 will thus be provided to a controlling circuit (102).
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: March 6, 2007
    Assignee: NXP B.V.
    Inventors: Marion Kornelia Matters-Kammerer, Theodoor Gertrudis Silvester Maria Rijks, Marco Matters
  • Patent number: 7187251
    Abstract: A direct current (DC) isolated phase inverter and a ring hybrid coupler including the DC isolated phase inverter is provided. The ring hybrid coupler including the DC isolated phase inverter comprising: a first, second, third and fourth transmission line arm; a first port connected to the first arm, second port connected to the second arm, third port connected to the third arm and fourth port connected to the fourth arm; and a DC phase inverter inserted within one of the first, second, third and fourth arms, wherein the DC phase inverter comprises: a transmission line comprising a plurality of signal and ground traces, wherein the plurality of signal and ground traces are interchanged; and a plurality of capacitors disposed in series with the ground traces, wherein the plurality of capacitors isolate the DC phase inverter from a device connected to the transmission line.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: March 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Mohan K. Chirala, Brian A. Floyd, Thomas M. Zwick
  • Patent number: 7187252
    Abstract: In the present technique for transmitting and delaying radio frequency signal transmission, an RF delay filter (102) is provided with at least one high permittivity material coaxial delay element (104) with each having an input port (114) and an output port (116). Multiple coaxial delay elements are operably coupled by a quarter-wave microstrip transmission line (230) to offset any frequency mismatch at the band edges of the delay elements. A series of capacitors (126, 128) are also included at each port of the coaxial elements to compensate for any resultant parasitic inductance.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: March 6, 2007
    Assignee: Motorola, Inc.
    Inventors: William H. Cantrell, Dale R. Anderson, William R. Meszko
  • Patent number: 7187253
    Abstract: A film bulk acoustic-wave resonator encompasses (a) a substrate having a cavity, (b) a bottom electrode partially fixed to the substrate, part of the bottom electrode is mechanically suspended above the cavity, (c) a piezoelectric layer disposed on the bottom electrode, a planar shape of the piezoelectric layer is defined by a contour, which covers an entire surface of the bottom electrode in a plan view, (d) a top electrode on the piezoelectric layer, (e) an intermediate electrode located between the substrate and the piezoelectric layer, and at the contour of the piezoelectric layer, the intermediate electrode is connected to the bottom electrode in the inside of the contour, and (f) a bottom electrode wiring connected to the intermediate electrode extending from the contour to an outside of the contour in the plan view, wherein a longitudinal vibration mode along a thickness direction of the piezoelectric layer is utilized.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: March 6, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenya Sano, Naoko Yanase, Kazuhiko Itaya, Takaaki Yasumoto, Ryoichi Ohara, Takashi Kawakubo, Takako Motai
  • Patent number: 7187254
    Abstract: Multiple thin film bulk acoustic resonators (10, 11) configured in series (10) and parallel (11) within a coplanar waveguide line structure provides a compact ladder filter. The resonators (10, 11) are formed over an opening (28) in a substrate (20) and connected to associated circuitry by one or more transmission lines formed on the substrate (20). The arrangement of the resonators (10, 11) between the ground and signal lines of a coplanar line structure provides a means of minimising the area of the filter. Embedding a ladder filter within the coplanar transmission line structure eliminates the need for wire bonds, thus simplifying fabrication. Embodiments for 2×2, and hither order filters are described.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: March 6, 2007
    Assignee: TDK Corporation
    Inventors: Qingxin Su, Paul B. Kirby, Eiju Komuro, Masaaki Imura, Roger W. Whatmore