Patents Issued in March 8, 2007
  • Publication number: 20070051926
    Abstract: The transparent conductive film 1 includes laminated transparent conductive thin films 10 and 20 of at least two layers. The transparent conductive thin film of the uppermost layer is an amorphous oxide thin film composed of gallium, indium, and oxygen, a gallium content ranges from 49.1 atom % to 65 atom % with respect to all metallic atoms, a work function is 5.1 eV or more, and a surface resistance is 100 ?/? or less. The transparent conductive base material includes a transparent substrate and the transparent conductive film 1 formed one or both surfaces of the transparent substrate.
    Type: Application
    Filed: December 28, 2004
    Publication date: March 8, 2007
    Inventors: Tokuyuki Nakayama, Yoshiyuki Abe
  • Publication number: 20070051927
    Abstract: The present invention provides a process for simply and easily producing fine metal particles or fine metal oxide particles in the form of a dry powder which can be used as extremely fine particles in a good dispersion state without causing coagulation for a long time even if not stored in a dispersion solvent.
    Type: Application
    Filed: October 20, 2004
    Publication date: March 8, 2007
    Inventors: Daisuke Itoh, Masayuki Ueda, Noriaki Hata, Yorishige Matsuba
  • Publication number: 20070051928
    Abstract: A mixture of inherently conductive polymers and non-ionic waterborne polymers is disclosed. A preferred mixture is lignosulfonic acid-grafted polyaniline and a breathable polyurethane. Coatings of the mixture can be used as anti-fouling marine coatings; anti-static fabrics, coatings and packaging; batteries; conductive inks; conductive adhesives; EMI/RFI shielding articles, radar or microwave absorption articles, and sensors.
    Type: Application
    Filed: November 10, 2004
    Publication date: March 8, 2007
    Applicant: PolyOne Corporation
    Inventor: Stephen Horton
  • Publication number: 20070051929
    Abstract: An article of manufacture marked with compositions comprising rare earth metal compounds which, due to their luminescence when irradiated with UV light, are suitable in particular for the marking of security-relevant items, such as documents or data carriers.
    Type: Application
    Filed: November 8, 2006
    Publication date: March 8, 2007
    Applicant: Honeywell International Inc.
    Inventors: Thomas Potrawa, Joachim Schulz
  • Publication number: 20070051930
    Abstract: Provided are a near-infrared-absorbing glass having high transmittance in a visible light region, an excellent near infrared absorption property, excellent climate resistance, etc., and is suitable for use as/in a near-infrared-absorbing element such as a near-infrared-absorbing filter, and a near-infrared-absorbing element to which the above near-infrared-absorbing glass is applied, and the near-infrared-absorbing glass contains, by cationic %, 25 to 45% of P5+, 1 to 10% of Al3+, 15 to 30% of Li+, 0.1 to 10% of Mg2+, 0.1 to 20% of Ca2+, 0.1 to 20% of Sr2+, 0.1 to 20 Ba2+ and 1 to 8% of Cu2+ and contains, as anionic components, 25 to 50 anionic % of F? and O2?.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 8, 2007
    Applicant: HOYA CORPORATION
    Inventor: Yoichi Hachitani
  • Publication number: 20070051931
    Abstract: A light-emitting material is provided allowing a light-emitting body having an excellent low-excitation characteristic and high brightness to be obtained by using a light-emitting material containing a light-emitting base material that emits light through radiative transition of electrons in material atoms, the light-emitting base having nanoparticles added thereto and dispersed therein, the light-emitting material also allowing a reduction in excitation energy and an increase in brightness to be simultaneously achieve, thereby allowing, for a wide range of light-emitting bodies, a reduction in excitation energy and a significant improvement in brightness to be achieved in a simple structure. Also provided is a light-emitting body having the light-emitting material and a light-emitting method.
    Type: Application
    Filed: June 16, 2005
    Publication date: March 8, 2007
    Applicants: MITSUBISHI HEAVY INDUSTRIES, LTD., Japan Nuclear Cycle Development Institute
    Inventors: Mikio Toda, Toshiro Nishi, Nobuki Oka, Hiroyuki Tsutaya, Kuniaki Ara, Hioaki Ohira, Kazuya Kurome, Naoki Yoshioka
  • Publication number: 20070051932
    Abstract: The present invention relates to a cylinder apparatus for a hydraulic lift jack with a transmission device, in which a transmission device is installed to adjust an ascending and descending velocity of the lift jack by pumping the fluids so that the ascending velocity of the lift jack can be increased progressively at high velocity when the load has not been applied, and the ascending velocity of the lift jack can be increased strongly at low velocity when the load has been applied, at the time of the ascending and descending operations of the lift jack.
    Type: Application
    Filed: October 27, 2005
    Publication date: March 8, 2007
    Inventor: Tae-Hong Ha
  • Publication number: 20070051933
    Abstract: A force applying apparatus includes a housing that supports a drive motor. A first extendable member is telescopically received in the housing and moves between a retracted position within the housing and an extended position axially of the housing. A second extendable member is telescopically received in the first extendable member and moves between a contracted position within the first extendable member and an expanded position axially of the first extendable member. The motor drives a ring gear that advances the first extendable member, and a ball nut is mounted in the end of the first extendable member to advance the second extendable member. A spline helps retain the first and second extendable members against rotation but a detent assembly selectively releases the first extendable member for rotation. The apparatus may be used to lift and level a recreational vehicle. A method implemented by this structure is also claimed.
    Type: Application
    Filed: June 24, 2004
    Publication date: March 8, 2007
    Inventor: Richard Rincoe
  • Publication number: 20070051934
    Abstract: A removable plate is affixed to a gate structure to define the rest position of the gate. The plate is affixed to the gate structure, either to a swinging gate member or to a rail support, preferably by one or more bolts. In a first preferred embodiment, the plate is affixed to the swinging gate member for abutting engagement with a backing plate on the rail. In a second preferred embodiment, the plate includes an L-shaped slot for each bolt so that the plate may be removed from abutting engagement with the backing plate while remaining affixed to the swinging gate member.
    Type: Application
    Filed: September 4, 2005
    Publication date: March 8, 2007
    Applicant: FABENCO, INC.
    Inventor: David LaCook
  • Publication number: 20070051935
    Abstract: A phase change random access memory (PRAM), and a method of operating the PRAM are provided. In the PRAM comprising a switching element and a storage node connected to the switching element, the storage node comprises a first electrode, a second electrode, a phase change layer between the first electrode and a second electrode, and a heat efficiency improving element formed between the first electrode and the phase change layer. The heat efficiency improving element may be one of a carbon nanotube (CNT) layer, a nanoparticle layer, and a nanodot layer, and the nanoparticle layer may be a fullerene layer.
    Type: Application
    Filed: February 23, 2006
    Publication date: March 8, 2007
    Inventors: Sang-mock Lee, Yoon-ho Khang, Jin-seo Noh, Dong-seok Suh
  • Publication number: 20070051936
    Abstract: A phase change memory cell includes a phase change region of a phase change material, a heating element of a resistive material, arranged in contact with the phase change region and a memory element formed in said phase change region at a contact area with the heating element. The contact area is in the form of a frame that has a width of sublithographic extent and, preferably, a sublithographic maximum external dimension. The heating element includes a hollow elongated portion which is arranged in contact with the phase change region.
    Type: Application
    Filed: April 6, 2006
    Publication date: March 8, 2007
    Applicant: STMicroelectronics S.r.I.
    Inventors: Fabio Pellizzer, Enrico Varesi, Agostino Pirovano
  • Publication number: 20070051937
    Abstract: The present invention aims at providing a structure in which a high p-type carrier concentration of 1×1017 cm?3 or more is obtained in a material in which, although it shows normally p-type conductivity, a carrier concentration smaller than 1×1017 cm?3 is only obtained. Also, the present invention aims at providing highly reliable semiconductor element and device each of which has excellent characteristics such as light emitting characteristics and a long lifetime. Each specific layer, i.e., each ZnSe0.53Te0.47 layer (2ML) is inserted between host layers, i.e., Mg0.5Zn0.29Cd0.21Se layers (each having 10ML (atomic layer) thickness) each of which is lattice matched to an InP substrate. In this case, each specific layer in which a sufficient carrier concentration of 1×1018 cm?3 or more is obtained when a single layer is inserted at suitable intervals.
    Type: Application
    Filed: August 8, 2006
    Publication date: March 8, 2007
    Inventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Hitoshi Nakamura
  • Publication number: 20070051938
    Abstract: A two-dimensional carrier is generated in the vicinity of an interface that is a hetero interface between a semiconductor layer and a semiconductor layer. Two concave portions are formed so as to extend from a primary surface as far as the interface. An electrode that is made of metal and provides a Schottky junction with the semiconductor layers is formed on a bottom surface and a side surface of the concave portion. An electrode that is made from metal and provides a low resistance contact with the semiconductor layers and is also in low resistance contact therewith is formed on the bottom surface and side surface of the concave portion. As a result, a semiconductor device is provided in which contact resistance between the electrodes and the semiconductor layers is reduced and high frequency characteristics are improved.
    Type: Application
    Filed: August 25, 2005
    Publication date: March 8, 2007
    Applicant: SANKEN ELECTRIC CO., LTD.
    Inventors: Koji Otsuka, Shinichi Iwakami
  • Publication number: 20070051939
    Abstract: In the semiconductor laser or electro-absorption optical modulator that includes strained quantum well layers as active layers, making laser characteristics or modulator characteristics adequate has seen the respective limits since band structures, especially, ?Ec and ?Ev, have been unable to be adjusted independently. This invention is constructed by stacking an n-type InGaAlAs-GRIN-SCH layer 3, an MQW layer 4, a p-type InGaAlAs-GRIN-SCH layer 5, a p-type InAlAs electron-stopping layer 6, and others, in that order, on an n-type InP wafer 1; wherein the MQW layer 4 includes InGaAlAs-strained quantum well layers and InGaAlAsSb-formed barrier layers each having strain of an opposite sign to the strain applied to the quantum well layers.
    Type: Application
    Filed: August 25, 2005
    Publication date: March 8, 2007
    Inventors: Kouji Nakahara, Makoto Kudo, Shigehisa Tanaka, Masataka Shirai
  • Publication number: 20070051940
    Abstract: Organic memory unit and driver circuit therefor The invention relates to organic memory units and driver circuits therefor. The organic memory units have a layer of bistably switchable material or comprise a circuit in which two OFETs are connected in series and one OFET is connected in parallel with a capacitor on the low potential side thereof such that the capacitor is connected in parallel with the discharge OFET and is charged by the second OFET.
    Type: Application
    Filed: January 14, 2004
    Publication date: March 8, 2007
    Inventors: Wolfgang Clemens, Walter Fix, Axel Gerlt, Andreas Ullmann
  • Publication number: 20070051941
    Abstract: The invention relates to a photovoltaic device, uses of the photovoltaic device, combinations of this photovoltaic device with circuits and to a method of generating electricity from light using this photovoltaic device.
    Type: Application
    Filed: July 20, 2004
    Publication date: March 8, 2007
    Applicant: Sony Deutschland GmbH
    Inventors: Michael Duerr, Gabriele Nelles, Akio Yasuda
  • Publication number: 20070051942
    Abstract: Nanoscale or mesoscale structures are fabricated on the surface of a substrate (e.g. silicon) by the aggregation of atomic clusters (e.g. antimony or bismuth) into V-grooves. These structures, preferably in the form of nanowires, are used as etching masks for the subsequent etching of the substrate. In an embodiment the V-grooves are metallised (e.g. with titanium or gold) prior to the deposition of the clusters. In this case the use of the nanostructures (e.g. antimony or bismuth) as an etching mask results in the formation of nanostructures of the underlying metal (e.g. titanium or gold). In this way the dimensions of the nanowires are transferred into the underlying metal film and the method allows fabrication of nanowires from materials (e.g. titanium or gold) that cannot be deposited as clusters.
    Type: Application
    Filed: September 23, 2004
    Publication date: March 8, 2007
    Applicant: NANOCLUSTER DEVICES LIMITED
    Inventors: Simon Brown, James Partridge
  • Publication number: 20070051943
    Abstract: A thin film transistor is provided, which includes: a gate electrode (124); a gate insulating layer (140) formed on the gate electrode; a semiconductor layer (154) formed on the gate insulating layer and disposed opposite the gate electrode; a source electrode (173) and a drain electrode (175) that are formed at least in part on the semiconductor layer and face each other, a passivation layer (180) formed on the source electrode, the drain electrode, and a portion of the semiconductor layer that is not covered with the source electrode and the drain electrode; and a shielding electrode (196) formed on the passivation layer and disposed on a region between the source electrode and the drain electrode.
    Type: Application
    Filed: October 13, 2004
    Publication date: March 8, 2007
    Inventors: Seong-Young Lee, Jong-Woong Chang
  • Publication number: 20070051944
    Abstract: The present invention relates to the improvement of phosphorescent organic electro-luminescent devices by using materials of the formula (1), preferably triazines, pyrimidines, pyridazines and pyrazines, in the hole-blocking layer.
    Type: Application
    Filed: November 24, 2004
    Publication date: March 8, 2007
    Inventors: Horst Vestweber, Anja Gerhard, Philipp Stobel
  • Publication number: 20070051945
    Abstract: An organic light-light conversion device excellent in device characteristics, comprising a light sensing unit having a layer including a photo-conductive organic semiconductor developing a photo-current multiplication phenomenon by light irradiation, and a light emitting unit having a layer including an electroluminescent organic semiconductor emitting light by current injection, characterized in that at least one of the photo-conductive organic semiconductor and an electroluminescent organic semiconductor is polymer semiconductor. An imaging intensifier consisting of a plurality of arranged above organic light-light conversion devices. An optical sensor provided with a means of measuring and outputting voltages applied to the above organic light-light conversion device and to the opposite ends of a layer including the electroluminescent organic semiconductor.
    Type: Application
    Filed: December 16, 2004
    Publication date: March 8, 2007
    Inventors: Kenichi Nakayama, Masaaki Yokoyama, Masato Ueda
  • Publication number: 20070051946
    Abstract: Organic light-emitting diode with a layer arrangement which comprises an electrode, a counter electrode and an organic layer sequence arranged between the electrode and the counter electrode, where the organic layer sequence is arranged on a metal substrate and one or several organic transport layers containing in each case an admixture for increasing the electric conductivity and which are formed with at least one of the features from the following group of features: charge carrier transporting and charge carrier injecting.
    Type: Application
    Filed: June 27, 2006
    Publication date: March 8, 2007
    Applicant: NOVALED AG
    Inventors: Karsten Walzer, Teja Roch, Qiang Huang, Karl Leo
  • Publication number: 20070051947
    Abstract: Provided is a semiconductor device including: a substrate; a layer containing one or more kinds of polymer compounds on the substrate; and an organic semiconductor layer in contact with the layer containing the one or more kinds of polymer compounds, in which at least one kind of the one or more kinds of polymer compounds is a polymer compound having one or more secondary or tertiary aliphatic amino groups, wherein the one or more aliphatic amino groups of the polymer compound having the aliphatic amino groups are bound to at least one of a side chain or a branched chain, and wherein said the layer containing the one or more kinds of polymer compounds contains polysiloxane compounds. With the constitution, a semiconductor device excellent in crystallinity and orientation can be provided.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 8, 2007
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Tomonari Nakayama, Akane Masumoto, Shintetsu Go, Toshinobu Ohnishi
  • Publication number: 20070051948
    Abstract: A test structure (200, 200?) having an array (224) of test devices (220) for detecting and studying defects that can occur in an integrated circuit device, e.g., a transistor (144), due to the relative positioning of one component (100) of the device with respect to another component (108) of the device. The test devices in the array are of a like kind, but vary in their configuration. The differences in the configurations are predetermined and selected with the intent of forcing defects to occur within at least some of the test devices. During testing, the responses of the test devices are sensed so as to determine whether or not a defect has occurred in any one or more of the test devices. If a defective test device is detected, the corresponding wafer (204) may be subjected to physical failure analysis for yield learning.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 8, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan Fales, Jerome Lasky
  • Publication number: 20070051949
    Abstract: A semiconductor device and related testing methods and configurations are provided to enable parallel (simultaneous) testing of multiple chips on a stacked multiple chip semiconductor device. Each chip in the device is configured to selectively output test results to one or more unique contacts on a substrate of the device.
    Type: Application
    Filed: September 6, 2005
    Publication date: March 8, 2007
    Inventors: Peter Schneider, Dawn Cutler
  • Publication number: 20070051950
    Abstract: A method for generating test patterns utilized in manufacturing a semiconductor device includes creating mini-data concerning a partial area pattern used in designing the semiconductor device, subjecting the mini-data to data processing in accordance with a condition of a manufacturing process of the semiconductor device, thereby creating processed mini-data, extracting a marginless point in the processed mini-data where a process margin is less than a predetermined threshold in a manufacturing process of the semiconductor device, determining a class of the marginless point in accordance with a criticality and a category of the marginless point, determining a parameter and a range of the parameter used for the marginless point in accordance with the class of the marginless point, and generating a plurality of test patterns to which different values of the parameter are respectively applied within the range.
    Type: Application
    Filed: September 7, 2006
    Publication date: March 8, 2007
    Inventors: Sachiko Kobayashi, Atsuhiko Ikeuchi
  • Publication number: 20070051951
    Abstract: A test methodology is provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. A resistor is formed on a region of dielectric isolation material formed in a semiconductor substrate. The MIM capacitor is formed over the resistor and separated therefrom by dielectric material. A metal thermometer, formed from the same material as the plates of the MIM capacitor, is placed above the resistor and in close proximity to the capacitor. High current is forced through the resistor, causing both the metal thermometer and the MIM capacitor to heat up along with the resistor. The change in resistance of the metal thermometer is monitored. Using the known temperature coeffecient of resistance (TCR) for the metal used to form both the capacitor and the thermometer, changes in the measured resistance of the metal thermometer are converted to temperature.
    Type: Application
    Filed: November 3, 2006
    Publication date: March 8, 2007
    Inventors: Prasad Chaparala, Barry O'Connell, Jonggook Kim
  • Publication number: 20070051952
    Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.
    Type: Application
    Filed: October 25, 2004
    Publication date: March 8, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Keitaro Imai
  • Publication number: 20070051953
    Abstract: The invention relates to an active matrix structure and method for manufacturing the active matrix structure for a display device, wherein the structure includes: providing a matrix substrate with a number of row lines and a number of column lines, with each point of intersection between one of the row lines and one of the column lines being assigned a passage through the matrix substrate for generating a pixel, depositing a layer of p-silicon on the matrix substrate, for each pixel, creating an n+-doped region in the p-silicon, which n+-doped region is provided from the passage as far as a free surface of the p-silicon layer, and creating a p+-doped region within the n+-doped region such that a layer of the n+-doped region remains, and applying a layer made of a matrix material which has particles of electronic ink contained therein, or an organic light-emitting diode layer on a free surface of the final structure resulting from step c).
    Type: Application
    Filed: February 21, 2006
    Publication date: March 8, 2007
    Inventor: Ludger Marwitz
  • Publication number: 20070051954
    Abstract: An exemplary thin film transistor (TFT) array substrate includes a glass substrate (430), a semiconductor layer (440) formed on the glass substrate, a gate insulating layer (407) formed on the semiconductor layer, and a plurality of gate electrodes (410) and common electrodes (411) formed on the gate insulating layer. A portion of the gate insulating layer corresponding to the common electrode includes introduced impurities to enhance a dielectric constant thereof. A method for manufacturing the TFT array substrate is also provided.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 8, 2007
    Inventor: Shuo-Ting Yan
  • Publication number: 20070051955
    Abstract: A thin film transistor array substrate has a gate electrode of the thin film transistor, a gate line connected to the gate electrode, and a gate pad connected to the gate line; a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, a data pad connected to the data line, a storage electrode formed and superimposed with the gate line; a semiconductor pattern formed in low part of the substrate; a transparent electrode pattern including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode covering the data pad; and a protection pattern and a gate insulation pattern stacked in a region other than the region where the transparent electrode pattern is formed.
    Type: Application
    Filed: November 9, 2006
    Publication date: March 8, 2007
    Inventors: Soon Yoo, Youn Chang, Heung Cho
  • Publication number: 20070051956
    Abstract: A thin film transistor having a substrate, a gate insulating layer, a double-gate structure, a first lightly doped region, and a second lightly doped region. The substrate has a source region and a drain region disposed on its opposite sides, a heavily doped region between source region and drain region, a first channel region between heavily doped region and source region and a second channel region between heavily doped region and drain region. The gate insulating layer covers the substrate. The double-gate structure has a first gate and a second gate disposed on gate insulating layer above the first and the second channel region, respectively. The first lightly doped region is disposed between second channel region and heavily doped region and the second lightly doped region between second channel region and drain region. The length of second lightly doped region is greater than that of first lightly doped region.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 8, 2007
    Inventors: Chih-Jen Shih, Chun-Hsiang Fang, Te-Hua Teng, Chia-Chien Lu
  • Publication number: 20070051957
    Abstract: Protrusions called ridges are formed on the surface of a crystalline semiconductor film formed by a laser crystallization method or the like. A heat absorbing layer are formed below a semiconductor film. When the semiconductor film is crystallized by laser, a temperature difference is produced between a semiconductor film 1010 positioned above a heat absorbing layer 1011 and a semiconductor film 1013 of the other region to produce a difference in thermal expansion at the boundary of the outside end 1015 of the heat absorbing layer. This difference produces a strain to form a surface wave. The surface wave starting at the outer periphery of the heat absorbing layer is formed in the vicinity of the heat absorbing layer. When the semiconductor layer is solidified after it is melted, the protrusions of the surface wave remain as protrusions after the semiconductor film is solidified.
    Type: Application
    Filed: October 26, 2006
    Publication date: March 8, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Setsuo Nakajima, Ritsuko Kawasaki
  • Publication number: 20070051958
    Abstract: According to the present invention, which is a display device in which a light-emitting element where an organic substance generating luminescence referred to as electroluminescence or a medium including a mixture of an organic substance and an inorganic substance is sandwiched between electrodes is connected to a TFT, the invention is to manufacture a display panel by forming at least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask layer for forming a predetermined pattern is formed by a method capable of selectively forming a pattern. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object and by forming a conductive layer or an insulating layer is used as a method capable of selectively forming a pattern.
    Type: Application
    Filed: October 25, 2004
    Publication date: March 8, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Keitaro Imai
  • Publication number: 20070051959
    Abstract: Failure light emission of an EL element due to failure film formation of an organic EL material in an electrode hole 46 is improved. By forming the organic EL material after embedding an insulator in an electrode hole 46 on a pixel electrode and forming a protective portion 41b, failure film formation in the electrode hole 46 can be prevented. This can prevent concentration of electric current due to a short circuit between a cathode and an anode of the EL element, and can prevent failure light emission of an EL layer.
    Type: Application
    Filed: November 3, 2006
    Publication date: March 8, 2007
    Inventors: Toshimitsu Konuma, Junya Maruyama
  • Publication number: 20070051960
    Abstract: A backlight module includes a base, a plurality of point light sources distributed on the base and a light guide plate. Each of the point light sources includes a transparent cover and a light-emitting unit received in the cover. The transparent cover includes an inwardly curved light emitting top surface for emitting light from the light-emitting unit. The light guide plate includes an incidence surface disposed facing the point light sources, and an emission surface opposite to the incidence surface. The incidence surface includes a plurality of light diffusion areas spatially corresponding to the respective point light sources.
    Type: Application
    Filed: April 10, 2006
    Publication date: March 8, 2007
    Applicant: HON HAI Precision Industry CO., LTD.
    Inventor: Tai-Cherng Yu
  • Publication number: 20070051961
    Abstract: A nitride semiconductor light-emitting device wherein a substrate or nitride semiconductor layer has a defect concentration region and a low defect density region other than the defect concentration region. A portion including the defect concentration region of the nitride semiconductor layer or substrate has a trench region deeper than the low defect density region. Thus by digging the trench in the defect concentration region, the growth detection is uniformized, and the surface planarity is improved. The uniformity of the characteristic in the wafer surface leads to improvement of the yield.
    Type: Application
    Filed: May 27, 2004
    Publication date: March 8, 2007
    Applicants: SHARP KABUSHIKI KAISHA, SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takeshi Kamikawa, Yoshika Kaneko, Kensaku Motoki
  • Publication number: 20070051962
    Abstract: The present invention is a semiconductor structure for light emitting devices that can emit light with multiple wavelengths, in particular, in the blue to ultraviolet region of the electromagnetic spectrum. The structure comprises an active portion positioned between a p-type gallium nitride (GaN) layer and an n-type gallium nitride (GaN) layer. The active portion includes an MQW emitting light with long wavelength and an MQW emitting light with short wavelength. There is another group of strain induces thickness fluctuation layers (SITFL) positioned between the active portion and the n-type gallium nitride (GaN) layer. The semiconductor structure itself is based on a sapphire substrate. A low temperature buffer layer is positioned between the sapphire substrate and the n-type gallium nitride (GaN) layer. There is still another undoped gallium nitride (GaN) layer positioned between n-type gallium nitride (GaN) layer and the low temperature buffer layer.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 8, 2007
    Inventor: Mu-Jen Lai
  • Publication number: 20070051963
    Abstract: A light source is based on a combination of silicon and calcium fluoride (CaF2). The silicon and the calcium fluoride need not be pure, but may be doped, or even alloyed, to control their electrical and/or physical properties. Preferably, the light source employs interleaved portions, e.g., arranged as a multilayer structure, of silicon and calcium fluoride and operates using intersubband transitions in the conduction band so as to emit light in the near infrared spectral range. The light source may be arranged so as to form a quantum cascade laser, a ring resonator laser, a waveguide optical amplifier.
    Type: Application
    Filed: September 6, 2005
    Publication date: March 8, 2007
    Inventor: Yifan Chen
  • Publication number: 20070051964
    Abstract: A dense array of semiconductor devices having an array of micro-reflectors, the micro-reflectors having characteristics that enhance dense packing of the array in balance with collection and collimation of the array's radiant output.
    Type: Application
    Filed: May 12, 2006
    Publication date: March 8, 2007
    Inventors: Mark Owen, Duwayne Anderson
  • Publication number: 20070051965
    Abstract: A CNT field emitting light source (20) is provided. The light source includes an anode (202), an anode substrate (201), a cathode (214), a cathode substrate (208), a fluorescent layer (203) and a sealing means (205). The anode is configured on the anode substrate, and the cathode is configured on the cathode substrate. The anode and the cathode are oppositely configured to produce a spatial electrical field when a voltage is applied therebetween. The cathode includes an emitter layer (206), capable of emitting electrodes bombarding the cathode and matters attached thereupon when activated and controlled by the spatial electric field, and a conductive layer (207), sandwiched between the cathode substrate and the emitter layer for providing an electrically connection therebetween. The fluorescent layer is configured on a surface of the anode oppositely facing the emitter layer, so as to produce fluorescence when bombarded by electrodes emitted from the emitter layer.
    Type: Application
    Filed: May 18, 2006
    Publication date: March 8, 2007
    Applicants: Tsinghua University, HON HAI Precision Industry CO., LTD.
    Inventors: Bing-Chu Du, Jie Tang, Liang Liu, Cai-Lin Guo, Pi-Jin Chen, Zhao-Fu Hu, Shou-Shan Fan
  • Publication number: 20070051966
    Abstract: A light emitting diode includes an LED element, a fluorescent material provided so as to cover the LED element, a substrate on which the LED element is mounted and made of ceramics or silicon, and a pair of electrode pads which are electrically connected to the LED element on the substrate.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 8, 2007
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Mitsutoshi Higashi, Akinori Shiraishi, Hideaki Sakaguchi, Yuichi Taguchi
  • Publication number: 20070051967
    Abstract: An adapted LED is provided comprising a short-wavelength LED and a re-emitting semiconductor construction, wherein the re-emitting semiconductor construction comprises at least one potential well not located within a pn junction. The potential well(s) are typically quantum well(s). The adapted LED may be a white or near-white light LED. The re-emitting semiconductor construction may additionally comprise absorbing layers surrounding or closely or immediately adjacent to the potential well(s). In addition, graphic display devices and illumination devices comprising the adapted LED according to the present invention are provided.
    Type: Application
    Filed: October 27, 2006
    Publication date: March 8, 2007
    Inventors: Thomas Miller, Michael Haase, Terry Smith, Xiaoguag Sun
  • Publication number: 20070051968
    Abstract: A nitride-based semiconductor light-emitting device having excellent reliability and long lifetime, and a method of manufacturing the same are provided. A nitride-based semiconductor light-emitting element chip, in which a nitride-based semiconductor layer and a first electrode are formed on a surface of an electrically conductive substrate and a second electrode is formed on a rear surface of the electrically conductive substrate, is mounted on a submount, and the submount having the nitride-based semiconductor light-emitting element chip mounted thereon is further mounted on a stem to form a nitride-based semiconductor light-emitting device.
    Type: Application
    Filed: April 18, 2004
    Publication date: March 8, 2007
    Inventors: Shuichiro Yamamoto, Atsushi Ogawa, Masaya Ishida, Takeshi Kamikawa
  • Publication number: 20070051969
    Abstract: A group III-V nitride-based semiconductor substrate having a group III-V nitride-based semiconductor thick film with a same composition in the entire film. The thick film has a first region with a predetermined impurity concentration and a second region with an impurity concentration lower than the first region.
    Type: Application
    Filed: December 21, 2005
    Publication date: March 8, 2007
    Inventors: Yuichi Oshima, Masatomo Shibata
  • Publication number: 20070051970
    Abstract: A nanowire electronmechanical device with an improved structure and a method of fabricating the same prevent burning of two nanowires which are switched due to contact with each other while providing stable on-off switching characteristics.
    Type: Application
    Filed: April 21, 2006
    Publication date: March 8, 2007
    Inventors: Jae-Eun Jang, Seung-nam Cha, Yong-Wan Jin, Byong-Gwon Song
  • Publication number: 20070051971
    Abstract: A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed in the substrate and a gate, the gate being formed above an active zone. A dielectric layer is formed on the transistor, the dielectric layer covering the gate. The dielectric layer is then etched while leaving it remaining at least on the gate so that the gate is electrically insulated from other elements formed above the dielectric layer. This etching is preferably carried out using a mask which was used for fabricating the gate and a mask which was used for fabricating the insulating zone.
    Type: Application
    Filed: August 25, 2006
    Publication date: March 8, 2007
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Paul Ferreira
  • Publication number: 20070051972
    Abstract: A main thyristor (1) has a recovery protection which is integrated into a drive thyristor (2) whose n-doped emitter (25) is electrically connected to a main thyristor control terminal (140). Moreover, the p-doped emitter (28) of the drive thyristor (2) is electrically connected to the p-doped emitter (18) of the main thyristor (1). Various optional measures for realizing a recovery protection are provided in this case. A method for producing a thyristor system having a main thyristor and a drive thyristor, the drive thyristor (2) having anode short circuits (211) involves introducing particles (230) into a target region (225) of the semiconductor body (200) of the drive thyristor (2), the distance between the target region (225) and a front side (201) of the semiconductor body (200) opposite to the rear side (202) being less than or equal to the distance between the p-doped emitter (28) and the front side (201).
    Type: Application
    Filed: August 8, 2006
    Publication date: March 8, 2007
    Inventors: Hans-Joachim Schulze, Franz Niedernostheide, Uwe Kellner-Werdehausen, Reiner Barthelmess
  • Publication number: 20070051973
    Abstract: A semiconductor device including: a bulk semiconductor substrate; an access transistor; a thyristor formed on the bulk semiconductor substrate connecting to the access transistor; an element separating region to separate the region for the access transistor and the region for the thyristor from each other; and a wiring layer connecting one of the diffused layers of the access transistor and the cathode of the thyristor together through a connecting hole, the impurity region at the anode side of the thyristor being composed of a p-type impurity region, an n-type impurity region, p-type impurity region, and an n-type impurity region, which are formed sequentially in the depthwise direction, with the lowermost n-type impurity region receiving the same voltage as that applied to the anode at the time of data holding.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 8, 2007
    Applicant: Sony Corporation
    Inventor: Ikuhiro Yamamura
  • Publication number: 20070051974
    Abstract: The power conversion apparatus uses the semiconductor device. Said semiconductor device includes a first group of power semiconductor elements at least one of which is electrically connected between a first potential and a third potential, a second group of power semiconductor elements at least one of which is electrically connected between a second potential and the third potential, and a third group of power semiconductor elements at least one of which is electrically connected between the first potential and the third potential. The second group is disposed between the first group and third group. Thereby, a low-loss semiconductor device having both inductance reducibility and heat generation balancing capability and also an electric power conversion apparatus using the same is provided.
    Type: Application
    Filed: August 10, 2006
    Publication date: March 8, 2007
    Applicant: Hitachi, Ltd.
    Inventors: Katsunori Azuma, Toshiaki Morita, Hiroshi Hozoji, Kazuhiro Suzuki, Toshiya Satoh, Osamu Otsuka
  • Publication number: 20070051975
    Abstract: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.
    Type: Application
    Filed: November 3, 2005
    Publication date: March 8, 2007
    Inventors: Christophe Figuet, Mark Kennard