Patents Issued in March 8, 2007
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Publication number: 20070051976Abstract: An energy selective radiation sensor 10 has a photodetector 11 and a transfer gate 12 for controlling transfer of charge from the photodetector to a first sense node 13. A first readout circuit 14, 15, 16 is provided for reading out charge from the first node. In use a first charge accumulated in the photodetector from a first predetermined portion 81; 91 of an energy spectrum of a radiation source is transferred to the first sense node 13. A second charge is accumulated in the photodetector from a second predetermined portion 82; 92 of the energy spectrum. The first charge is readout from the first sense node with the readout circuit, the second charge transferred to the first sense node and likewise readout. In embodiments of the invention, a second sense node 532; 632 and second transfer gate 522; 622 are provided and the first charge is read out through a first sense node 531; 631 and the second charge through the second sense node 532; 632.Type: ApplicationFiled: August 31, 2006Publication date: March 8, 2007Applicant: E2V Technologies (UK) LimitedInventors: Ian Moody, Raymond Bell
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Publication number: 20070051977Abstract: A nitride semiconductor device comprises: a substrate body including a conductive substrate portion and a high resistance portion; a first semiconductor layer of a nitride semiconductor provided on the substrate body; a second semiconductor layer provided on the first semiconductor layer; a first main electrode provided on the second semiconductor layer; a second main electrode provided on the second semiconductor layer; and a control electrode provided on the second semiconductor layer between the first main electrode and the second main electrode. The second semiconductor layer is made of a nondoped or n-type nitride semiconductor having a wider bandgap than the first semiconductor layer. The first main electrode is provided above the conductive portion and the second main electrode is provided above the high resistance portion.Type: ApplicationFiled: August 22, 2006Publication date: March 8, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Masaaki Onomura, Akira Tanaka, Koichi Tachibana, Masahiko Kuraguchi, Takao Noda, Tomohiro Nitta, Akira Yoshioka
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Publication number: 20070051978Abstract: The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.Type: ApplicationFiled: August 17, 2006Publication date: March 8, 2007Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventors: Juro Mita, Katsuaki Kaifu
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Publication number: 20070051979Abstract: A semiconductor device includes a plurality of electrodes arranged on a compound semiconductor layer grown on a substrate, and a surface protection film that protects a surface of a semiconductor layer on the compound semiconductor layer between the electrodes. A refractive index of the surface protection film is controlled so that a stress caused by the surface protection film on the surface of the semiconductor layer is minimized.Type: ApplicationFiled: August 29, 2006Publication date: March 8, 2007Applicant: The Furukawa Electric Co, Ltd.Inventors: Hiroshi Kambayashi, Nariaki Ikeda, Seikoh Yoshida
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Publication number: 20070051980Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.Type: ApplicationFiled: August 23, 2005Publication date: March 8, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wade Hodge, Alvin Joseph, Rajendran Krishnasamy, Qizhi Liu, Bradley Orner
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Publication number: 20070051981Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.Type: ApplicationFiled: September 7, 2005Publication date: March 8, 2007Applicant: THE BOEING COMPANYInventor: Berinder Brar
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Publication number: 20070051982Abstract: A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and bit lines generally perpendicular to the word lines, with a word line pitch of less than 2 F. In one embodiment, the word lines are made of polysilicon spacers.Type: ApplicationFiled: July 18, 2006Publication date: March 8, 2007Applicant: Saifun Semiconductors Ltd.Inventors: Ilan Bloom, Boaz Eitan, Rustom Irani
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Publication number: 20070051983Abstract: A driving circuit of a liquid crystal display panel includes a substrate, a plurality of driver IC chips located on the substrate, a current supplier, and a first conductive wire set. The first conductive wire set has a plurality of conductive wire segments for connecting the driver IC chips in parallel to the current supplier. Furthermore, the conductive wire segments each have a form, such that paths formed of the conductive wire segments from the current supplier to the respective driver IC chips have an equal resistance, and, accordingly, each of the driver IC chips obtain the same input voltage. Hence, a problem of band mura is avoided.Type: ApplicationFiled: August 24, 2005Publication date: March 8, 2007Inventors: Ming-Zen Wu, Chien-Chih Jen
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Publication number: 20070051984Abstract: A rewiring substrate strip and a method of producing a rewiring substrate strip is disclosed. In one embodiment, the rewiring substrate strip has several semiconductor component positions for semiconductor components. The semiconductor component positions are arranged in rows and columns. In this arrangement, several semiconductor component positions are combined to form one component group. The semiconductor components of a component group are arranged with respect to one another in such a manner that an individual semiconductor component is rotated by 90° with respect to four adjacent semiconductor components.Type: ApplicationFiled: April 19, 2005Publication date: March 8, 2007Applicant: INFINEON TECHNOLOGIES AGInventor: Peter Ossimitz
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Publication number: 20070051985Abstract: A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred out of the wells. A clear window region overlies a fixed potential gradient region, decreasing in potential away from the control gates. This region enables a wide band of photons to be sensed by the photosensitive silicon of the CCD. The decreasing potential levels facilitate high charge transfer efficiency (i.e., high CTE) from pixel to pixel via the control or transfer gates. By applying particular voltages to the control gates, charge can be quickly and efficiently transferred between pixels.Type: ApplicationFiled: August 10, 2006Publication date: March 8, 2007Inventor: Mark Wadsworth
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Publication number: 20070051986Abstract: An image sensor is provided. The image sensor includes a substrate having a plurality of cell regions, photodiodes formed in the cell regions of the substrate an antireflection layer, a color filter layer, a planarization layer, and a plurality of microlenses. The antireflection layer is formed above the substrate including the photodiodes and incorporates at least two insulating layers with different refractive indexes. The color filter layer is formed on the antireflection layer and corresponds to the photodiodes of the cell regions. The planarization layer is formed on the color filter layer. The plurality of microlenses is formed on the planarization layer and correspond to the photodiodes of the cell regions.Type: ApplicationFiled: August 18, 2006Publication date: March 8, 2007Inventor: Kim Sik
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Publication number: 20070051987Abstract: Provided is a digital micromirror device (DMD). The DMD includes a first metal line, a second metal line, a third metal line, and a mirror. The first metal line is formed to have a predetermined line width and a predetermined thickness, and the second metal line is formed to have the same width and thickness as the first metal line. The third metal line is formed to have its own predetermined line width and predetermined thickness, and the mirror rotates according to a voltage applied to the first, second and third metal lines to reflect light incident thereto.Type: ApplicationFiled: September 8, 2006Publication date: March 8, 2007Inventor: Yun Yoon
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Publication number: 20070051988Abstract: A solid-state imaging device that includes: a pixel array section configured by an array of a unit pixel, including an optoelectronic conversion section that subjects an incoming light to optoelectronic conversion and stores therein a signal charge, a transfer transistor that transfers the signal charge stored in the optoelectronic conversion section, a charge-voltage conversion section that converts the signal charge provided by the transfer transistor into a signal voltage, and a reset transistor that resets a potential of the charge-voltage conversion section; and voltage setting means for setting a voltage of a well of the charge-voltage conversion section to be negative.Type: ApplicationFiled: August 29, 2006Publication date: March 8, 2007Inventor: Fumihiko Koga
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Publication number: 20070051989Abstract: A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the trench photosensor.Type: ApplicationFiled: November 7, 2006Publication date: March 8, 2007Inventor: Howard Rhodes
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Publication number: 20070051990Abstract: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes: a semi conductor substrate of a first conductivity type having a photodiode region and a transistor region defined therein; a gate electrode formed above the transistor region of the semiconductor substrate with a gate insulating layer interposed therebetween; a first impurity region formed of the first conductivity type in the semiconductor substrate below the gate electrode and having a higher concentration of first conductivity type ions than the semiconductor substrate; and a second impurity region formed of a second conductivity type in the photodiode region of the semiconductor substrate.Type: ApplicationFiled: August 21, 2006Publication date: March 8, 2007Inventor: Lim Hyuk
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Publication number: 20070051991Abstract: Provided are a CMOS image sensor and a method for fabricating the same. The CMOS image sensor including: a metal pad formed on a pad region of a substrate; an insulation layer formed on the entire surface of the substrate, and having a metal pad opening part to expose a predetermined portion of the surface of the metal pad; a plurality of first microlenses formed a predetermined distance from each other above the insulation layer in a unit pixel region of the substrate; and a plurality of second microlenses formed on the entire surface of the unit pixel region including the first microlenses.Type: ApplicationFiled: August 22, 2006Publication date: March 8, 2007Inventor: Han Hun
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Publication number: 20070051992Abstract: Provided are a CMOS image sensor and a fabricating method thereof. The CMOS image sensor includes a device isolation layer, a plurality of photodiode regions, an interlayer insulating layer, a refracting layer, a planarizing layer, a color filter layer, and a plurality of microlenses. The refracting layer, with a higher refractive index than that of the interlayer insulating layer, is formed through the interlayer insulating layer on portions of the device isolation layer, to divide the interlayer insulating layer and give the divided portions thereof the characteristics of a waveguide.Type: ApplicationFiled: September 8, 2006Publication date: March 8, 2007Inventor: Sun Jung
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Publication number: 20070051993Abstract: A method of forming a thin film transistor is provided. First, an amorphous silicon layer is formed on a substrate. Next, a first gate insulating layer is formed on the amorphous silicon layer. Then, an annealing process is performed so that the amorphous silicon layer is melted and re-crystallized to form a poly silicon layer. Next, the first insulating layer and the poly silicon layer are patterned to form an island. Then, a gate electrode is formed on the island. Finally, a source region and a drain region are formed inside the poly silicon layer of the island. After the annealing process is performed, the boundary between the poly silicon layer and the gate insulating layer becomes denser, so that the current leakage of the thin film transistor can be reduced.Type: ApplicationFiled: September 8, 2005Publication date: March 8, 2007Inventors: Ming-Che Ho, Yun-Pei Yang, Po-Chih Liu, Chia-Chien Lu
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Publication number: 20070051994Abstract: A dynamic random access memory (DRAM) device has dual-gate vertical channel transistors. The device is comprised of pillar-shaped active patterns including source regions contacting with a semiconductor substrate, drain regions formed over the drain regions, and channel regions formed between the source and drain regions. The active patterns are disposed in a cell array field. On the active patterns, bit lines are arranged to connect the drain regions along a direction. Between the active patterns, word lines are arranged intersecting the bit lines. Gat insulation films are interposed between the word lines and active patterns.Type: ApplicationFiled: August 31, 2006Publication date: March 8, 2007Inventors: Ki-Whan Song, Jong-Duk Lee, Byung-Gook Park, Hoon Jeong
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Publication number: 20070051995Abstract: A MOS transistor cell having a salicide structure has a plurality of gate wires each formed as a straight line with a constant width. Each of the gate wires includes a P-channel gate terminal and an N-channel gate terminal. The P-side ends and the N-side ends of the gate wires are connected by means of respective two gate wire connecting portions at a boundary portion between the MOS transistor cell and another adjacent MOS transistor cell.Type: ApplicationFiled: September 7, 2006Publication date: March 8, 2007Inventors: Masahiko Kumashiro, Tadashi Tanimoto
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Publication number: 20070051996Abstract: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.Type: ApplicationFiled: October 26, 2006Publication date: March 8, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiangdong Chen, Geng Wang, Yujun Li, Qiqing Ouyang
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Publication number: 20070051997Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.Type: ApplicationFiled: August 31, 2005Publication date: March 8, 2007Inventors: Gordon Haller, Sanh Tang, Steve Cummings
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Publication number: 20070051998Abstract: A semiconductor memory device with a dielectric structure and a method for fabricating the same are provided. The dielectric structure includes: a first dielectric layer having a dielectric constant of approximately 25 or higher; a second dielectric layer including a material having a crystallization rate lower than the first dielectric layer and formed over the first dielectric layer; and a third dielectric layer including a material substantially identical to that of the first dielectric layer and formed over the second dielectric layer.Type: ApplicationFiled: March 22, 2006Publication date: March 8, 2007Inventors: Deok-Sin Kil, Kwon Hong, Seung-Jin Yeom
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Publication number: 20070051999Abstract: A ferroelectric capacitor having a three-dimensional structure, a nonvolatile memory device having the same, and a method of fabricating the same are provided. The ferroelectric capacitor may include a trench-type lower electrode, at least one layer formed around the lower electrode, a ferroelectric layer (PZT layer) formed on the lower electrode and the at least one layer and an upper electrode formed on the ferroelectric layer. The at least one layer may be at least one insulating interlayer and the at least one layer may also be at least one diffusion barrier layer. The at least one layer may be formed of an insulating material excluding SiO2 or may have a perovskite crystal structure excluding Pb.Type: ApplicationFiled: September 5, 2006Publication date: March 8, 2007Inventors: Sang-min Shin, Young-soo Park, June-mo Koo, Byoung-jae Bae, I-hun Song, Suk-pil Kim
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Publication number: 20070052000Abstract: A nonvolatile memory device and method for fabricating the same are provided. The nonvolatile memory device includes an active region; a source region formed in the active region; a source line formed on the source region and electrically connected with the source region, to cross over the active region; word lines aligned at each sidewall of the source line to cross over the active region in parallel with the source line; and a charge storage layer interposed between the word lines and the active region. Since the word lines are formed at both sides of the source line using an anisotropic etch-back process, without photolithography, the area of a unit cell can be reduced.Type: ApplicationFiled: December 30, 2005Publication date: March 8, 2007Inventor: Sang Lee
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Publication number: 20070052001Abstract: A nonvolatile semiconductor memory device and a method of fabricating the same are provided. The nonvolatile memory device may include a switching device and a storage node connected to the switching device. The storage node may comprise a lower electrode, a data storing layer, and an upper electrode. The data storing layer may include a first region where a current path is formed at a first voltage, and a second region surrounding the first region where a current path is formed at a second voltage, greater than the first voltage. The first region may be positioned to contact the upper electrode and the lower electrode.Type: ApplicationFiled: August 11, 2006Publication date: March 8, 2007Inventors: Seung-eon Ahn, Jung-bin Yun, In-kyeong Yoo, Dong-chul Kim, Tae-hoon Kim
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Publication number: 20070052002Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.Type: ApplicationFiled: June 15, 2005Publication date: March 8, 2007Inventors: Shibly Ahmed, Jun Kang, Hsiao-Han Thio, Imran Khan, Dong-Hyuk Ju, Chuan Lin
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Publication number: 20070052003Abstract: A method for producing a memory with high coupling ratio is provided. First, a shallow trench isolation is formed on a substrate to define an active area. Second, a spacer is formed at the sidewall of the shallow trench isolation. Third, the shallow trench isolation is etched such that the top of the spacer is higher than the surface of the shallow trench isolation. Fourth, a tunnel oxide is formed on the active area. Finally, a floating gate is formed on the tunnel oxide.Type: ApplicationFiled: November 15, 2005Publication date: March 8, 2007Inventors: Chih-Ping Chung, Chun-Nan Lin, Chung-Yi Chen, Hung-Kwei Liao
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Publication number: 20070052004Abstract: A method of manufacturing nano crystals disclosed herein is applicable to the fabrications of memory device and solar cell. The method of manufacturing nano crystals at least comprises steps of: providing a substrate with a thin film formed thereon, and transforming the thin film into the nano crystals by laser annealing, wherein a thickness of the thin film is equal to or less than about 50 ?, and a wavelength of the laser selected for laser annealing is equal to or less than about 500 nm.Type: ApplicationFiled: December 28, 2005Publication date: March 8, 2007Inventors: Chih-Wei Chao, Mao-Yi Chang, I-Chang Tsao
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Publication number: 20070052005Abstract: The present invention provides a method of manufacturing a flash memory device. The method includes forming a gate oxide layer on a semiconductor substrate, forming a floating gate including protrusions and depressions on its surface by patterning polysilicon deposited on the gate oxide layer, depositing a dielectric layer on the floating gate and the gate oxide layer, and forming a control gate by patterning polysilicon deposited on the dielectric layer.Type: ApplicationFiled: December 30, 2005Publication date: March 8, 2007Inventor: Sang-Woo Nam
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Publication number: 20070052006Abstract: To prevent the extraction of electrons from the floating gate during a read operation. A semiconductor memory device comprises a selection gate 3a provided in a first region on a substrate 1 through an insulating film 2, a floating gate 6a provided in a second region adjacent to the first region through an insulating film 5, a first and second diffusion regions 7a and 7b provided in a third region adjacent to the second region, and a control gate 11 provided over the floating gate 6a through an insulating film 8, the control gate 11 intersects with the selection gate 3a at different levels, a third diffusion region 21 is provided in a fourth region located near an extending part of the selection gate 3a on the surface of the substrate, the floating gate 6a is formed in the form of a side wall, and it has a round part 6b at the top on the side directed to the side wall surface of the selection gate 3a.Type: ApplicationFiled: September 5, 2006Publication date: March 8, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Tsuneaki Hikita
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Publication number: 20070052007Abstract: A non-volatile memory device (e.g., a split gate type device) and a method of manufacturing the same are disclosed. The memory device includes an active region on a semiconductor substrate, a pair of floating gates above the active region, a charge storage insulation layer between each floating gate and the active region, a pair of wordlines over the active region and partially overlapping the floating gates, respectively, and a gate insulation film between each wordline and the active region. The method may prevent or reduce the incidence of conductive stringers on the active region between the floating gates, to thereby improve reliability of the memory devices and avoid the active region resistance from being increased due to the stringer.Type: ApplicationFiled: September 5, 2006Publication date: March 8, 2007Inventor: Jin Jung
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Publication number: 20070052008Abstract: A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.Type: ApplicationFiled: November 15, 2005Publication date: March 8, 2007Inventors: Chih-Ping Chung, Chun-Nan Lin, Chung-Yi Chen, Hung-Kwei Liao
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Publication number: 20070052009Abstract: A phase change random access memory (PRAM) element is provided that is driven by a MOSFET. The MOSFET includes, for example, a source region, a drain region, and a gate electrode disposed between the source region and the drain region. An insulator layer (e.g., oxide layer) separates the gate electrode from contact with the region of the substrate between the source and drain regions. A first electrode contact is coupled to the drain region of the MOSFET at one end and terminates at a surface. The surface of the first electrode contact is coated with a phase change material. A second electrode contact is provided having a surface coated with a layer of phase change material. The PRAM element includes at least one columnar member formed from a phase change material interposed between the phase change material layer of the first electrode and phase change material layer of the second electrode.Type: ApplicationFiled: September 5, 2006Publication date: March 8, 2007Applicant: The Regents of the University of CaliforniaInventors: Ya-Hong Xie, Tae-Sik Yoon, Zuoming Zhao
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Publication number: 20070052010Abstract: The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.Type: ApplicationFiled: September 5, 2005Publication date: March 8, 2007Inventors: Tzu-Hsuan Hsu, Erh-Kun Lai, Hang-Ting Lue, Chia-Hua Ho
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Publication number: 20070052011Abstract: A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.Type: ApplicationFiled: August 24, 2005Publication date: March 8, 2007Inventor: Arup Bhattacharyya
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Publication number: 20070052012Abstract: A vertical nano-wire transistor is formed on a substrate out of a vertical pillar having active regions of opposing conductivity in opposite ends of the pillar. In one embodiment, the source region is a p+ region in the substrate under the pillar and the drain region is an n+ region at the top of the pillar. A surround gate is formed around the pillar. The transistor operates by electron tunneling from the source valence band to the gate biasing induced n-type channels along the sidewalls of the pillar to the drain region, thus resulting in a drain current.Type: ApplicationFiled: August 24, 2005Publication date: March 8, 2007Inventor: Leonard Forbes
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Publication number: 20070052013Abstract: A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench.Type: ApplicationFiled: June 9, 2006Publication date: March 8, 2007Inventors: Hyun-Ki Kim, Jung-Hwa Lee, Ji-Young Kim
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Publication number: 20070052014Abstract: A trench IGBT is disclosed which includes a semiconductor substrate having formed therein a set of cell trenches formed centrally and a set of annular guard trenches concentrically surrounding the cell trenches. The cell trenches receive cell trench conductors via cell trench insulators for providing IGBT cells. The guard trenches receive guard trench conductors via guard trench insulators for enabling the IGBT to withstand higher voltages through mitigation of field concentrations. Capacitive coupling conductors overlie the guard trench conductors via a dielectric layer, each for capacitively coupling together two neighboring ones of the guard trench conductors. The capacitive coupling conductors are easily adjustably variable in shape, size and placement relative to the guard trench conductors for causing the individual guard trench conductors to possess potentials for an optimal contour of the depletion layer.Type: ApplicationFiled: August 21, 2006Publication date: March 8, 2007Applicant: Sanken Electric Co., Ltd.Inventor: Tetsuya Takahashi
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Publication number: 20070052015Abstract: Aiming at realizing high breakdown voltage and low ON resistance of a semiconductor device having the super-junction structure, the semiconductor device of the present invention has a semiconductor substrate having an element forming region having a gate electrode formed therein, and a periphery region formed around the element forming region, and having an field oxide film formed therein; and a parallel p-n layer having n-type drift regions and p-type column regions alternately arranged therein, formed along the main surface of the semiconductor substrate, as being distributed over the element forming region and a part of the periphery region, wherein the periphery region has no column region formed beneath the end portion on the element forming region side of the field oxide film and has p-type column regions as at least one column region formed under the field oxide film.Type: ApplicationFiled: September 6, 2006Publication date: March 8, 2007Applicant: NEC ELECTRONICS CORPORATIONInventors: Yoshinao Miura, Hitoshi Ninomiya
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Publication number: 20070052016Abstract: In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the present invention, for example, a MOS transistor, a P type diffusion layer 5 as the back gate region, and an N type diffusion layer 8 as a drain region, are formed in an N type epitaxial layer 4. In the P type diffusion layer 5, an N type diffusion layer 7 as a source region and a P type diffusion layer 6 are formed. The P type diffusion layer 6 is formed by performing ion implantation twice so as to correspond to a shape of a contact hole 15. Moreover, impurity concentrations in surface and deep portions of the P type diffusion layer 6 are controlled. By use of this structure, a device size is reduced, and an operation of a parasitic NPN transistor is suppressed.Type: ApplicationFiled: August 11, 2006Publication date: March 8, 2007Inventors: Seiji Otake, Ryo Kanda, Schuichi Kikuchi
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Publication number: 20070052017Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.Type: ApplicationFiled: April 27, 2006Publication date: March 8, 2007Inventor: Masatomi Okanishi
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Publication number: 20070052018Abstract: An integrated device includes two sections, such as a DFB laser and an EAM modulator, having a semi-insulating separation region therebetween. The separation region is of a material acting as a trap on electrons and configured to impede current flow between the two sections due to holes. The separation region may be of a material acting as a trap both on electrons and holes. Alternatively, the separation region is of a material that acts as a trap on electrons and is provided over a p-type substrate common to the two sections.Type: ApplicationFiled: July 31, 2006Publication date: March 8, 2007Inventors: Michele Agresti, Cesara Rigo, Marco Vallone
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Publication number: 20070052019Abstract: A transistor device having a metallic source electrode, a metallic drain electrode, a metallic gate electrode and a channel in a deposited semiconductor material, the transistor device comprising: a first layer comprising the metallic gate electrode, a first metal portion of the metallic source electrode and a first metal portion of the metallic drain electrode; a second layer comprising a second metal portion of the metallic source electrode, a second metal portion of the metallic drain electrode, the deposited semiconductor material and dielectric material between the semiconductor material and the metallic gate electrode; and a third layer comprising a substrate, wherein the first, second and third layers are arranged in order such that the second layer is positioned between the first layer and the third layer.Type: ApplicationFiled: July 9, 2004Publication date: March 8, 2007Inventor: John Rudin
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Publication number: 20070052020Abstract: A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal regions separately formed on the doped a-Si region and above the gate electrode, and isolated from the a-Si region; a passivation layer formed on the gate insulation layer and covering the source, drain and data-line (DL) metal regions; and a conductive layer formed on the passivation layer. The passivation layer has a first, second and third vias for respectively exposing the partial surfaces of the source, drain and DL metal regions. The first, second and third vias are filled with the conductive layer, so that the DL and source metal regions are connected via the conductive layer.Type: ApplicationFiled: March 31, 2006Publication date: March 8, 2007Inventors: Chi-Wen Chen, Ting-Chang Chang, Po-Tsun Liu, Kuo-Yu Huang, Jen-Chien Peng
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Publication number: 20070052021Abstract: It is an object of an invention disclosed in the present specification to provide a transistor having low contact resistance. In the transistor, a semiconductor film including an impurity element imparting P-type or N-type conductivity, an insulating film formed thereover, and an electrode or a wiring that is electrically connected to the semiconductor film through a contact hole formed at least in the insulating film are included; the semiconductor film has a first range of a concentration of the impurity element (1×1020/cm3 or less) that is included in a deeper region than predetermined depth, and a second range of a concentration of the impurity element (more than 1×1020/cm3) that is included in a shallower region than the predetermined depth; and a deeper region than a portion in contact with the electrode or the wiring in the semiconductor film is in the first range of the concentration of the impurity element.Type: ApplicationFiled: August 14, 2006Publication date: March 8, 2007Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Atsuo Isobe, Keiko Saito, Tomohiko Sato
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Publication number: 20070052022Abstract: A thin film transistor (TFT), a method of fabricating the same, and a display device including the TFT, are provided. In the TFT, a channel region is connected to a gate electrode so that the influence of a substrate bias is reduced or eliminated. Thus, the threshold voltage of the TFT is reduced, a subthreshold slope can be improved, and a large drain current can be obtained at a low gate voltage.Type: ApplicationFiled: August 25, 2006Publication date: March 8, 2007Inventors: Byoung-Keon Park, Byoung-Deog Choi, Myeong-Seob So
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Publication number: 20070052023Abstract: A thin film transistor and a method of fabricating the same are disclosed. The method includes: sequentially depositing an amorphous silicon layer, a capping layer, and a metal catalyst layer; annealing the entire layer to crystallize the amorphous silicon layer into a polysilicon layer; removing the capping layer; and, when the capping layer is perfectly removed to make a contact angle of the polysilicon layer within a range of about 40 to about 80°, forming a semiconductor layer using the polysilicon layer.Type: ApplicationFiled: August 24, 2006Publication date: March 8, 2007Inventors: Tae-Hoon Yang, Ki-Yong Lee, Jin-Wook Seo, Byoung-Keon Park
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Publication number: 20070052024Abstract: Provided are a nano semiconductor sheet, a thin film transistor (TFT) using the nano semiconductor sheet, and a flat panel display using nano semiconductor sheet. The nano semiconductor sheet has excellent characteristics, can be manufactured at room temperature, and has good flexibility. The nano semiconductor sheet includes: a first film and a second film disposed on at least one side of or inside of the first film, and includes a plurality of nano particles arranged substantially in parallel to each other. In addition, provided are a method of manufacturing a nano semiconductor sheet and methods of manufacturing a TFT and a flat panel display using the nano semiconductor sheet. The method of manufacturing a nano semiconductor sheet, includes: forming first polymer micro-fibers having a plurality of nano particles arranged substantially in parallel; preparing a first film; and arranging a plurality of the first micro-fibers on at least one side of or inside of the first film.Type: ApplicationFiled: August 26, 2006Publication date: March 8, 2007Inventors: Sang-Min Lee, Nam-Choul Yang
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Publication number: 20070052025Abstract: Provided is a thin film transistor comprising a channel layer comprised of an oxide semiconductor containing In, M, Zn, and O, M including at least one selected from the group consisting of Ga, Al, and Fe. The channel layer is covered with a protective film.Type: ApplicationFiled: August 29, 2006Publication date: March 8, 2007Applicant: CANON KABUSHIKI KAISHAInventor: Hisato Yabuta