Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulating film formed on a channel region between the source/drain regions, a gate electrode formed on the gate insulating film, and a sidewall insulating film formed on a sidewall surface of the gate electrode, wherein the gate electrode is made of SiGe, the sidewall insulating film is an insulating film obtained by oxidizing the sidewall surface of the gate electrode, and the sidewall insulating film contains silicon oxide as a main component.

Abstract: A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: The invention provides an ESD protection structure, compatible with the bipolar-CMOS-DMOS (BCD) processes, which provides an enhanced protection performance and better heat dissipation performance. The design of the ESD structures in present invention takes advantage of bipolar punch characteristics of the parasitic bipolar structure to bypass the ESD current, thus significantly reducing the trigger voltage and increasing the ESD protection level. In addition, the ESD protection circuit of the present invention can improve heat dissipation by avoid current crowding near the surface.

Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.

Abstract: It is made possible to easily set a protection voltage even when a semiconductor device to be protected includes a gate insulating film having a low dielectric breakdown voltage.

Abstract: An electrostatic discharge (ESD) device with latch-up immunity is provided. The ESD device has an equivalent SCR structure when a supply voltage is not applied thereto and has an equivalent PN diode structure when the supply voltage is applied thereto, thus freeing the ESD device from the latch-up phenomenon.

Abstract: A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven switching elements which are connected to each other in push-pull configuration and driven at their gate terminals by the load drive control signal. The buffer circuit has an output terminal which is connected to a connection point between ends of controlled electrodes of the gate driven switching elements, and a power source terminal and a ground connection terminal respectively connected to the remaining ends of the other controlled electrodes of the gate driven switching elements. A ground connection side element of a pair of gate driven switching elements has a set of MOS transistors which are connected across the connection point and the ground connection terminal.

Abstract: A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.

Abstract: An image sensor in which the metal interconnects are coated with an anti-reflective coating is disclosed. The top, bottom and sides of the metal interconnects may be coated to reduce reflection from all directions. The thickness of the coating is chosen to suppress reflection of light of certain wavelengths incident at certain expected angles. In particular, the thickness of the coating may be chosen to reduce reflections from neighboring pixels. The metal may be coated in multiple layers of anti-reflective coating to suppress multiple wavelengths of light or multiple angles of incidence.

Abstract: Transistors and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having a first gate electrode comprising a first thickness, and an NMOS transistor having a first gate electrode comprising a second thickness, wherein the first thickness is greater than the second thickness. The first gate electrode and the second gate electrode preferably comprise the same material, and may comprise TiSiN, TaN, or TiN, as examples. The thickness of the first gate electrode and the second gate electrode set the work function of the PMOS and NMOS transistors.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A semiconductor device includes a first transistor and a second transistor. The first transistor comprises at least one first gate electrode including a first metal layer. The second transistor comprises at least one second gate electrode including the first metal layer. The at least one first gate electrode or the at least one second gate electrode includes a second metal layer disposed over the first metal layer.

Abstract: A semiconductor device that suppresses variation and a drop in the breakdown voltage of transistors. In the semiconductor device in which a logic transistor and a high-breakdown-voltage transistor are formed on one Si substrate, an insulating film which has an opening region and which is thick around the opening region is formed on a low concentration drain region formed in the Si substrate on one side of a gate electrode of the high-breakdown-voltage transistor. The insulating film around the opening region has a two-layer structure including a gate insulating film and a sidewall insulating film. When ion implantation is performed on the low concentration drain region beneath the opening region to form a high concentration drain region, the insulating film around the opening region prevents impurities from passing through.

Abstract: A semiconductor device includes a silicon region including Si, and a silicide film provided on the silicon region, the silicide film comprising a compound of Si with Ni, Co, Pd, or Pt and including Er.

Abstract: A transistor structure such as a FinFET is formed in a semiconductor substrate with a surface contour having an upper surface at least partially bounded by sidewalls of trenches in the semiconductor substrate. First and second source/drain regions are arranged along the upper surface of the surface contour, with a recess structure between the first and second source/drain regions. The recess structure extends further into the semiconductor substrate than the first and second source/drain regions such that a channel within the semiconductor substrate between the first and second source/drain regions extends around the recess structure. The effective length of the channel is a function of the depth of the recess structure. A gate electrode is arranged along at least one of the sidewalls adjacent the channel. The effective channel width is a function of the depth to which the gate electrode is formed.

Abstract: A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wher

Abstract: In order to provide a semiconductor device having good quality by keeping the relative permittivity of a High-K insulation film in a high state, or to provide a method for manufacturing a semiconductor device in which the relative permittivity of the High-K insulation film can be kept in a high state, a semiconductor device is disclosed that includes a silicon substrate, a gate electrode layer, and a gate insulation film between the silicon substrate and the gate electrode layer. The gate insulation film is a high relative permittivity (high-k) film being formed by performing a nitriding treatment on a mixture of a metal and silicon. The High-K film itself becomes a nitride so as to prevent SiO2 from being formed.

Abstract: Example embodiments relate to a multilayer gate electrode, a semiconductor device having the same and methods of fabricating the same. Other example embodiments relate to a semiconductor device with a multilayer gate electrode which is relatively stable at higher temperatures, has improved resistance characteristics and improved reliability, and methods of fabricating the same. The multilayer gate electrode may include a polycrystalline semiconductor layer on the gate insulating layer and doped with conductive type impurities, an ohmic contact layer on the polycrystalline semiconductor layer and including tungsten (W1?x) and non-tungsten metal (Mx, x=about 0.01 to about 0.55), a metal barrier layer on the ohmic contact layer and a refractory metal layer on the metal barrier layer.

Abstract: Scrolling input arrangements are presented including: a flexible membrane; a number of capacitive sensors mechanically integrated with the flexible membrane, the capacitive sensors radially disposed with respect to a first axis that is perpendicular with respect to the flexible membrane; an integrated circuit mechanically coupled with the flexible membrane and electronically coupled with the capacitive sensors, the integrated circuit configured to process a number of electronic signals from the capacitive sensors to provide a scrolling function; and a connection region on the flexible membrane for electronically coupling the scrolling input arrangement with an electronic device.

Abstract: A passive nanomagnet alignment method is described to self-align a membrane to another surface. The membrane and the surface each have a plurality of nanomagnets patterned on it, wherein the nanomagnets are magnetized based on an applied external magnetic field. The membrane is brought into close proximity and coarse alignment to the surface by a positioning mechanism (e.g., an actuation force), such that the nanomagnets on the membrane attract to and self-align with the nanomagnets on said surface based on the nanomagnet magnetizations.

Abstract: A pressure sensor includes a base substrate silicon fusion bonded to a cap substrate with a chamber disposed between the base substrate and the cap substrate. Each of the base substrate and the cap substrate include silicon. The base substrate includes walls defining a cavity and a diaphragm portion positioned over the cavity, wherein the cavity is open to an environment to be sensed. The chamber is hermetically sealed from the environment.

Abstract: Highly corrosion resistant electrically conductive contact systems suitable for semiconductor pressure sensor devices exposed to acidic, elevated temperature environments, such as automotive exhaust gas environments, are disclosed. The preferred embodiment (10) comprises a platinum top layer (26), and a tantalum lower layer (24). Both are highly electrically conductive layers and exhibit corrosion resistance to acidic environments. The top layer of the metallization also provides a suitable material for the external connectivity (e.g., wire bonding, solder bumping, chip-chip fusion). The lower layer of the metallization also serves as an adhesion layer between the top metal and lower layers, typically silicon based glasses and in some cases serves as a diffusion barrier.

Abstract: A semiconductor structure having a III-V substrate; a first III-V donor layer having a relatively wide bandgap disposed over the substrate; a III-V channel layer having a relatively narrow bandgap disposed on the donor layer; a second III-V donor layer disposed on the channel layer having a relatively wide bandgap. The first III-V donor provides both tensile strain to compensate compressive strain in the channel layer and carriers to the channel layer.

Abstract: An integrated opto-electric sensor includes a wavenumber matching structure that is integrated onto a silicon substrate, and a first conductive electrode that is adjacent to one of a lightly doped and an undoped region in the silicon substrate to form a Schottky junction. A dielectric is positioned adjacent to the first conductive electrode, and a second conductive electrode is formed at the silicon substrate. The first conductive electrode and the second conductive electrode provide coupling for a detected signal that is provided in response to illumination of the wavenumber matching structure by an optical signal.

Abstract: A method and apparatus for a backside thinned image sensor with an integrated lens stack.

Abstract: A photoelectric conversion layer comprising a compound represented by the following formula (1): wherein R1 to R10 each independently represents a hydrogen atom or a substituent; L represents a monovalent group or a divalent or polyvalent connecting group; m is 0 or 1; and n represents an integer of from 1 to 4.

Abstract: Inorganic-based nanoparticles, such as nanoparticles based on silicon dioxide, are used in order to produce protective layers for semiconductor chips having scratch-resistant properties. The nanoparticles are preferably processed to form a sol, which is applied onto the semiconductor chips to be coated and subsequently converted by sintering into the protective layer.

Abstract: A CMOS image sensor including a light-receiving element, at least one transistor, a first dielectric layer, a reflective layer, a second dielectric layer, a protective layer, a material layer, a transparent material layer, an optical filter, and a converging element is described. The light-receiving element and the transistor are disposed respectively inside the light sensing region and the transistor region. The first dielectric layer is disposed on the substrate, covering the transistor and the light-receiving element. The reflective layer is disposed on the first dielectric layer inside the light sensing region. The second dielectric layer is disposed on the first dielectric layer outside of the reflective layer. The material layer is disposed on the first dielectric layer inside of the reflective layer. The optical filter is disposed on the transparent material layer and the converging element is disposed on the optical filter inside the light sensing region.

Abstract: A CMOS imager having reduced dark current and methods of forming the same. A nitrided gate oxide layer having approximately twice the thickness of a typical nitrided gate oxide is provided over the photosensor region of a CMOS imager. The gate oxide layer provides an improved contaminant barrier to protect the photosensor, contains the p+ implant distribution in the surface of the p+ pinned region of the photosensor, and reduces photon reflection at the photosensor surface, thereby decreasing dark current.

Abstract: A red pixel having a capacitor formed over the photo-conversion region of the pixel. The capacitor can be used by other pixels as a common capacitor. The capacitor is coupled to floating diffusion region shared by a plurality of pixels. The plurality of pixels also share readout circuitry.

Abstract: A solid-state imaging device includes: a semiconductor substrate; and a signal processing section provided on a backside of the semiconductor substrate. The semiconductor substrate has; a first impurity region of a first conductivity type, the first impurity region storing a signal charge produced through photoelectric conversion by a photoelectric conversion section formed in a surface portion of the semiconductor substrate; a second impurity region of the first conductivity type formed below the first impurity region; and a first gate electrode penetrating the semiconductor substrate in a thickness direction of the semiconductor substrate, the first gate electrode transferring the signal charge stored in the first impurity region to the second impurity region. The signal processing section receives the signal charge transferred to the second impurity region.

Abstract: A Schottky diode includes an isolation region of a first conductivity type and an anode region of a second conductivity type isolated by the isolation region, the anode region including a lightly doped deep anode region of the second conductivity type and an increased dopant region of the second conductivity type, the increased dopant region including a shallow surface dopant spike region of the second conductivity type at a surface of the anode region. A heavily doped anode contact region of the second conductivity type electrically contacts the anode region, and a metal silicide cathode region is disposed in the surface dopant spike region. The peak dopant surface concentration is high enough to produce a predetermined saturation current density. The dopant concentration in the increased dopant region is sufficiently high to suppress the current gain of a parasitic bipolar transistor enough to adequately suppress operation of the parasitic bipolar transistor.

Abstract: A semiconductor component having a drift path (2) which is formed in a semiconductor body (1), is composed of a semiconductor material of first conductance type. The drift path (2) is arranged between at least one first and one second electrode (3, 4) and has a trench structure in the form of at least one trench (18). A dielectric material which is referred to as a high-k material and has a relative dielectric constant ?r where ?r?20 is arranged in the trench structure such that at least one high-k material region (5) and one semiconductor material region (6) of the first conductance type are arranged in the area of the drift path (2).

Abstract: A single, controlled etch step can be used to form a sharp tip feature along a sidewall of an etch feature. An etch process is used that is selective to a layer of tip material relative to the substrate upon which the layer is deposited. A lag can be created in the etch, such that the etch rate is slower near the sidewall. The sharp tip feature is formed from the same layer of material used to create the etch feature. The sharp tip feature can be used to decrease the minimum critical dimension of an etch process, such as may be due to the minimum resolution of a photolithographic process. The novel tip feature also can be used for other applications, such as to create a microaperture for a photosensitive device, or to create a micromold that can be used to form objects such as microlenses.

Abstract: One or more vertical DMOS transistors, such as trench FETS, are formed between opposing floating poly-filled trench portions. The opposing trench portions may include two parallel trenches, rectangular trenches, hexagonal trenches, octagonal trenches, circular trenches, or other shapes. The floating trench portions are capacitively coupled to assume a potential somewhere between the high drain voltage (below the trenches) and the body voltage (near the top of the trenches). The floating trench portions will have a potential below the drift region and deplete the drift region. The depletion regions caused by the opposing trench portions will merge under the gate with a sufficiently high drain voltage. The electric field lines in the drift region will be shaped to increase the breakdown voltage of the device.

Abstract: A semiconductor layer with laterally variable doping, and a method for producing it are disclosed. The trenches here are no longer filled up completely with doped semiconductor material. Instead, a doped balancing layer is deposited in a sense as a lining on the walls of the trenches. The doped balancing layer has a defined layer thickness that remains constant over an entire depth of the trenches. Furthermore, both a dopant concentration and the layer thickness of the balancing layer are adjusted such that a complete charge required for compensation is already contained in the balancing layer. The trenches here can advantageously have an arbitrarily great berm angle. The invention is especially advantageous in a peripheral region of semiconductor components with high depletion voltage strength.

Abstract: An LC tank structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

Abstract: An electric fuse includes a wide interconnect and a narrow interconnect. The electric fuse has a juxtaposed region in which a plurality of straight line portions are juxtaposed with each other by folding the wide interconnect and the narrow interconnect has a narrower width than that of the wide interconnect, and, at the same time, is connected to the wide interconnect outside the juxtaposed region.

Abstract: A semiconductor device is provided which includes a pair of metal interconnections (B, C) provided above a semiconductor substrate (10), a program layer (20) provided over the pair of metal interconnections (B, C) and in which an opening (21) may be selectively formed in the program layer (20) on the basis of programming information, and a read circuit (40) reading the programming information by determining whether such an opening (21) is formed in the program layer (20) by utilizing an electrostatic capacitance between the pair of metal interconnections (B, C). The program layer (20) may be made of a material having a dielectric constant higher than that of air or the program layer (20) may be made of a conductor or a material having a dielectric constant lower than that of air.

Abstract: A semiconductor device comprising a substrate and a ferroelectric capacitor formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film interposed between the lower and upper electrodes. The ferroelectric capacitor having sidewalls receded from sidewalls of the upper electrode.

Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.

Abstract: In the semiconductor device of the present invention, an active region is formed in an upper surface of a semiconductor substrate, and is surrounded by a trench filled with an oxide. A through-hole electrode electrically connected to the active region extends from the upper surface of the semiconductor substrate to a lower surface thereof. A bottom end of the through-hole electrode juts out of an insulating film covering the lower surface of the semiconductor substrate. Accordingly, a jutting portion of the through-hole electrode is embedded in the bonding material when the semiconductor device is mounted on a mounting board, and thus the connection reliability therebetween is improved.

Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.

Abstract: An integrated conductor arrangement comprises a substrate with a top side, at least one tubular conductor trench provided in the substrate below the top side of the substrate and a conductor. The conductor comprises at least one tubular conductor layer and is integrated in the conductor trench.

Abstract: A semiconductor device package comprising a semiconductor device and an electrically conductive lead frame at least partially covered by a molding compound. The electrically conductive lead frame includes a plurality of leads disposed proximate a perimeter of the package and a die pad disposed in a central region formed by the plurality of leads. The die pad includes a first die pad surface disposed at the first package face, and a second die pad surface opposite the first die pad surface. The semiconductor device is attached to a central region of the second die pad surface, and a portion of the second die pad surface extending outward from the die is roughened to improve adhesion of the die pad to the molding compound. In other aspects, grooves are disposed in the first and/or second die pad surfaces to further promote adhesion of the die pad and to prevent moisture from permeating into the vicinity of the semiconductor chip.

Abstract: It is configured to comprise a semiconductor chip 110, a resin member 106 for forming a cavity 109 in which this semiconductor chip 110 is installed, and wiring 105 constructed of pattern wiring 105b formed so as to be exposed to a lower surface 106a of this resin member 106 and also connected to the semiconductor chip 110 and a post part 105a in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to a front surface 106b of the resin member 106.

Abstract: A semiconductor device includes: a semiconductor element; a metallic plate having a heat radiation surface; a terminal connecting to the element; and a resin mold covering the element, the plate and the terminal. The metallic plate provides an electrode of the semiconductor element. The heat radiation surface is capable of radiating heat generated in the element. The heat radiation surface and a part of the terminal are exposed from the resin mold. The resin mold includes a concavity/convexity portion between the heat radiation surface and the part of the terminal in order to lengthen a creepage distance therebetween. The concavity/convexity portion is disposed on a surface of the resin mold.

Abstract: A semiconductor chip 23 is mounted on an island section 22 in a lead frame composed of a lead having the island section 22, a ground-bonding lead section 28 and a lead 21a each continuing in sequence, and other lead terminal sections 21b to 21d, and then a grounding electrode 24a and other electrodes 24b to 24d for the semiconductor chip are respectively wire-bonded to the lead 21a and other lead terminals 21b to 21d by gold wires 25a to 25d before being embedded in a resin to form a package 27. The lead with the semiconductor chip 23 mounted thereon is structured so that the ground-bonding lead section 28 continuing to both the lead 21a and the island section 22 are absent on both the sides of the wire-bonding region 28a with respect to the island section 22 in the longitudinal section along the grounded gold wire 25a.

Abstract: After a light emitting element is mounted to a header of a light emitting lead frame, a light receiving element is mounted to a header of a light receiving lead frame and a power element is mounted to a header of a power lead frame, the light emitting element, the light receiving element and the power element are connected to respective lead portions with wires, and in a state with the light emitting element, and the light receiving element and the power element, disposed facing each other, they are entirely coated with a primary molding resin, and the primary molding resin and a heat sink formed in a heat dissipating lead frame are coated with a secondary molding resin. Also, a structure is adopted in which the lead terminal of the power element and the heat dissipating lead frame are stacked together, and joined at this stacked portion.

Abstract: A semiconductor device is provided including a semiconductor element having a plurality of electrodes, a plurality of bonding portions of a lead frame, a plate-like current path material which electrically connects at least one of the plurality of electrodes and one of the plurality of bonding portions, a housing which packages the semiconductor element having the plurality of electrodes, the plurality of bonding portions of the lead frame, and the current path material, wherein the plate-like current path material is arranged to be directly bonded to one of the plurality of electrodes and one of the plurality of bonding portions, and the middle portion of the current path material is formed apart from the surface of the semiconductor element. A method of manufacturing the same is also provided.