Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed, wherein the method lends itself to better automation of the manufacturing line as well as to improving the quality and reliability of the packages produced therefrom. This is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, in contrast with the conventional fully etched stencil-like lead frames, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant.

Abstract: A system and method for packaging a magnetic sensor is described. A sensor die is constructed such that connection pads are situated on two opposing sides of the die in two vertical arrays. Bonding wires connect the connection pads on the sensor die to wire bond pads on a substrate. Alternatively, the connection pads are connected to solderable chip pads on the substrate using flip chip bonding. Traces and vias are used to connect the wire bond pads or the solderable chip pads to sensor package pads. The sensor package pads are located on a single side of a sensor package for mounting on a next assembly. The next assembly has a land pattern that includes at least one leveling pad for positioning the sensor die perpendicular to the next assembly while being mounted and a single row of pads for making connections to the sensor package.

Abstract: A matrix package substrate molding process is provided. First, a matrix package substrate with a plurality of package units for disposing chips on the package units is provided. Next, an encapsulation mold is disposed on each of the package units. The mold has a plurality of mold cavities arranged as branches to correspondingly accommodate a chip. When the encapsulation is filled into the mold and flows into the cavities by branch, the chips on the branch are covered by the encapsulation. After curing the encapsulation, the mold is lifted off to complete the package operation. Accordingly, the processing time and cost are saved.

Abstract: A multi-chip stacked package structure, including a leadframe base thin package structure with two or more chips in the stacking structure, is provided that is capable of including two or more stacked chips that reduce the total stacking thickness. The package structure also reduces stacking thickness by achieving stacking of four or more chips into the area of a thin small outline package structure.

Abstract: A three-dimensional interconnect interposer adapted for use in system in package (SIP) includes a wafer, at least an embedded passive device and at least an interconnect pattern disposed on the front surface of the wafer, a plurality of cavities exposing the inner contact pads of the interconnect pattern formed on the back surface of the wafer, and a back connect pattern disposed on the back surface of the wafer electrically connected to the interconnect pattern and the embedded passive device through the inner contact pads.

Abstract: Disclosed are methods and devices for providing improved semiconductor packages and POP IC assemblies using the improved packages with reduced warping. According to disclosed embodiments of the inventions, a packaged semiconductor device for use in a POP assembly includes an encapsulated region generally defined by the substrate surface. The encapsulant is provided with contact apertures permitting external communication with contacts on the substrate and coupled to an encapsulated chip. Preferred embodiments of the invention are described in which the contact aperture sidewalls are angled within the range of approximately 10-30 degrees or more from vertical and in which the contact aperture is provided a gas release channel to permit gas to escape during reflow.

Abstract: A multi-chip package structure including a carrier, a first chip having an active surface and a rear surface, multiple bumps, a second chip, multiple first bonding wires, a package unit disposed above the first chip, a spacer disposed between the package unit and the first chip, multiple second bonding wires, and an encapsulant is provided. The bumps are disposed between the active surface and the carrier to electrically connect the first chip and the carrier. The second chip is disposed on the rear surface of the first chip. The first bonding wires electrically connect the second chip and the carrier. The second bonding wires electrically connect the package unit and the carrier. The encapsulant is disposed on the carrier to encapsulate the first chip, the second chip, at least a portion of the package unit, the bumps, the spacer, the first bonding wires and the second bonding wires.

Abstract: A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.

Abstract: A microelectronic module is provided with one or more first conductive pads on at least one of the exterior surfaces of the module for electrical interconnection of the functionality of the module to one or more second conductive pads on a second surface such as printed circuit board. A high density interposer assembly is disposed between the first conductive pads and second conductive pads. Outwardly projecting conductive elements on the interposer assembly are in registration with the first and second conductive pads whereby, when the interposer assembly is interposed between the first and second conductive pads, a mechanical connection is made between the elements, resulting in an electrical path between the first and second conductive pads.

Abstract: In a semiconductor device, a pad metal has at least a portion located immediately under a probe region, and the portion is divided into a plurality of narrow metal layers each arranged in parallel with a traveling direction of a probe. Thus, it is possible to enhance surface flatness of the pad metal and to prevent a characteristic of a semiconductor device from deteriorating without complication in processing and increase in chip size.

Abstract: A method of manufacturing an electronic parts packaging structure of the present invention, includes a step of mounting an electronic parts, which has a connection terminal and a passivating film to cover the connection terminal, on a mounted body to direct the connection terminal upward, a step of forming an insulating layer to cover the electronic parts, a step of forming a via hole in a portion of the passivating film and the insulating layer on the connection terminal to expose the connection terminal, and a step of forming a wiring pattern, which is connected electrically to the connection terminal via the via hole, on the insulating layer.

Abstract: A method and apparatus for decoupling conductive portions of a microelectronic device package. In one embodiment, the package can include a microelectronic substrate and a conductive member positioned at least proximate to the microelectronic substrate. The conductive member can have first and second neighboring conductive portions with at least a part of the first conductive portions spaced apart from a part of the neighboring second conductive portion to define an intermediate region between the first and second conductive portions. Each conductive portion has a bond region electrically coupled to the microelectronic substrate. A dielectric material is positioned adjacent to the first and second conductive portions in the intermediate region and has a dielectric constant of less than about 3.5.

Abstract: To solve the problems caused by accumulation of heat generated from an integrated circuit. The integrated circuit device of the invention includes a substrate over one surface of which an integrated circuit is formed. The other surface of the substrate (a surface over which the integrated circuit is not formed) includes a depressed portion and has a larger surface area than the one surface. The depressed portion formed on the other surface of the substrate is filled with a heat sink material, or a film containing a heat sink material is formed at least over the surface of the depressed portion. Such integrated circuit devices may be provided in a multilayer structure.

Abstract: Disclosed herein are an adhesive film having a multiple filler distribution and a method of manufacturing the same, and a chip stack package having the adhesive film and a method of manufacturing the same. The adhesive film may have an upper film layer with a high concentration of fillers with a small particle size, and a lower film layer with a low concentration of fillers of a large particle size. The adhesive film having a multiple filler distribution may be manufactured using a lamination method or a consecutive coating method. The adhesive film may include two film layers having identical chemical properties while having different physical properties.

Abstract: A semiconductor chip package may include a circuit board and a semiconductor chip that may be attached to the circuit board so as to be electrically connected to the circuit board. An intermediate pattern for reducing stress may be provided on a surface of the semiconductor chip that may face the circuit board.

Abstract: The device of the invention comprises a semiconductor element, a first connection element, a first patterned electrically conductive layer and a second patterned electrically conductive layer. The device is further provided with an encapsulation that encapsulates all except the first conductive layer, which is part of the substrate. The device can be suitably made in that the second conductive layer is provided, in pre-patterned form, with a permeable isolating layer as a foil.

Abstract: An interconnection structure for a pad region of the substrate is provided. A semiconductor circuit and a pad are disposed on the substrate of the pad region. The interconnection structure includes a first and a second dielectric layers, via plugs and contact plugs. The patterned conductive layer includes an auxiliary layer having a plurality of gaps and a plurality of first wire lines disposed between the auxiliary layers passes through the gaps and exits from the pad region. The first dielectric layer is disposed between the patterned conductive layer and the pad. The via plugs are disposed in the first dielectric layer for connecting the auxiliary layer and the pad. The second dielectric layer is disposed between the substrate and the patterned conductive layer. The contact plugs are disposed in the second dielectric layer for electrically connecting the semiconductor circuit and the first wire lines.

Abstract: Disclosed is an improved construction of an ultrasonic transducer, wherein a charge is not easily injected into an insulating film even when the bottom of a membrane comes in contact with a lower electrode, and a manufacturing method thereof without using the wafer laminating technique. The ultrasonic transducer includes a lower electrode; a cavity layer formed on the first electrode; an insulating film covering the cavity layer; and an upper electrode formed on the insulating film, wherein, the cavity layer includes projections formed into an insulating film protruded from the cavity layer. In addition, an opening is formed into the upper electrode, and this upper electrode having the opening formed therein is deposited at a position not being superposed with the projections of the insulating film when seen from the top.

Abstract: A semiconductor chip package may include one or more conductive patterns provided on a front surface of a wafer. An encapsulation layer may cover at least the front surface of the wafer. Chip plugs may be electrically connected to the conductive patterns, and may be embedded in a rear surface of the wafer. External connection terminals may be electrically connected to the chip plugs, and may be provided on the rear surface of the wafer.

Abstract: Provided is a technology capable of improving the reliability of a semiconductor device using WPP by preventing a short-circuit failure between uppermost-level interconnects. In the present invention, a buffer layer is formed between an uppermost-level interconnect and redistribution interconnect. The uppermost-level interconnect is made of a copper film, while the buffer layer is made of an aluminum film. The redistribution interconnect is made of a film stack of a copper film and a nickel film. In such a semiconductor device, stress concentration occurs at a triple point when temperature cycling between low temperature and high temperature is performed. The stress concentration on the triple point is relaxed by the presence of the buffer layer, whereby the conduction of the stress to an interface just below the triple point can be suppressed. Peeling due to the stress at the interface can thus be prevented.

Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.

Abstract: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with an connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. It is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

Abstract: A metal line, which can be used in a semiconductor device structure less than 65 nm in size by forming a barrier metal of an anti-diffusion layer for a copper line using CVD TiSiN, and a fabrication method thereof are provided. The metal line includes: a semiconductor substrate having a semiconductor device formed thereon; an insulating layer which has a contact hole at a portion corresponding to the semiconductor device and is formed on the semiconductor substrate; a TiSiN barrier metal layer which is formed in the contact hole; and a copper line which is formed on the TiSiN barrier metal layer.

Abstract: A semiconductor device includes a die with at least one electrode on a surface thereof, at least one solderable contact formed on the electrode, and a passivation layer formed over the electrode and including an opening that exposes the solderable contact. The passivation layer opening may be wider than the solderable contact such that a gap extends between the contact and the passivation layer. The device also includes a barrier layer disposed on the top surface of the electrode, and along the underside of the solderable contact and across the gap. The barrier layer may also extend under the passivation layer and may cover the entire top surface of the electrode. The barrier layer may also extend along the sidewalls of the electrode. The barrier layer may include a titanium layer or a titanium layer and nickel layer. The barrier layer protects the electrode and underlying die from acidic fluxes found in lead-free solders.

Abstract: A portable electronic device spring clip including a first retention section adapted to attach the spring clip to a framework; a second retention section adapted to be located at a top side of a metal cover frame of a display module of a portable electronic device; a first contact section adapted to electrically connect to a printed wiring board (PWB); and a second contact section adapted to electrically connect to the metal cover frame of the display module. The spring clip is adapted to electrically connect the metal cover frame of the display module to the PWB. The spring clip is adapted to mechanically retain the display module to the PWB when the framework is connected to the PWB.

Abstract: A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film.

Abstract: An integrated circuit chip includes a substrate, a device layer, an interconnection layer, a sealing base layer and a sealing ring stack layer. The substrate has a sealing region and a chip region. The sealing region is disposed around the chip region. The device layer is disposed within the chip region. The interconnection layer is disposed over and connected with the device layer. The sealing base layer is disposed within the sealing region. The sealing ring stack layer is disposed over and connected with the sealing base layer. A manufacturing process of the integrated circuit chip is also disclosed.

Abstract: TiN layer structures for semiconductor devices, methods of forming TiN layer structures, semiconductor devices having TiN layer structures and methods of fabricating semiconductor devices are disclosed. The TiN layer structure for a semiconductor device includes a TiN base layer and a conductive capping layer. The TiN base layer is formed on a substrate. The conductive capping layer is formed on the TiN base layer by laminating unit layers repeatedly.

Abstract: Generally, the process includes depositing a barrier layer and seed layer on a feature formed in a dielectric layer, performing a grafting process, initiating a copper layer and then filing the feature by use of a bulk copper fill process. Copper features formed according to aspects described herein have desirable adhesion properties to a barrier and seed layers formed on a semiconductor substrate and demonstrate enhanced electromigration and stress migration results in the fabricated devices formed on the substrate.

Abstract: Methods and articles are disclosed. The methods are directed to depositing nickel duplex layers on substrates to inhibit corrosion and improve solderability of the substrates. The substrates have a gold or gold alloy finish.

Abstract: A first mark formed simultaneously with the process step for forming a layer of metal interconnects is partly exposed at two parallel side surfaces of the separated semiconductor device or one side surface thereof to have a rectangular shape. This allows the identification of the orientation and product information of the semiconductor device in a small semiconductor device.

Abstract: A dual damascene structure comprising a substrate, a dielectric layer, a metal hard mask layer, a protection layer and a conductive layer is provided. The substrate has a conductive area. The dielectric layer is disposed on the substrate. The metal hard mask layer is disposed on the dielectric layer. The protection layer is disposed on the metal hard mask layer. A trench is disposed in the protection layer, the metal hard mask layer and a part of the dielectric layer. An opening is disposed in the dielectric layer under the trench. The opening exposes the conductive area. The conductive layer is disposed in the trench and the opening.

Abstract: A semiconductor package includes a substrate having a first surface portion in a cavity. The first surface portion includes an artificially formed grass structure. The package includes a getter film formed over the grass structure.

Abstract: A flip-chip packaging process is disclosed. The present invention is featured in forming a copper pillar on a wafer, forming a solder on a substrate; and enabling the solder to substantially cover the entire externally-exposed surface of the copper pillar, thereby connecting the copper pillar to the substrate. The copper pillar of the present invention can be such as a prism or a cylinder.

Abstract: A chip structure including a chip, a passivation layer, an elastic layer and a metal layer is provided, with a bump disposed on the metal layer for electrically connecting a bonding pad of the chip. The passivation layer and the elastic layer are covering an active surface of the chip, and have an opening respectively for exposing top surface of the bonding pad, wherein the elastic layer is utilized to make the bump being heat-pressed onto a contact of a substrate with an enhanced electrical performance, and the elastic layer is made of for example polyimide or other macromolecule polymer. Moreover, the chip structure further includes a plurality of elastic granular structures at the bottom of the bump to enhance the bonding reliability of the bump.

Abstract: An electronic module and a method of assembling the electronic module. A circuit board is connected to a chip substrate by an array of connectors, and a base member is on the side of the circuit board away from the chip substrate and connector array. An elastomeric structure is placed between the circuit board and the base member. The elastomeric structure has voids between a first defining plane adjacent the circuit board and a second defining plane adjacent the base member, with the voids adapted to permit local deformation of elastomeric material in the structure. The method includes applying a compressive force between the circuit board and base member to at least partially compressing the elastomeric structure to improve load equalization on the circuit board.

Abstract: The invention relates to a support (4) with solder ball elements (1) for loading substrates (2) with ball contacts. Furthermore, the invention relates to a system for loading substrates (2) with ball contacts and to a method for loading substrates (2) with ball contacts. For this purpose, the support (4) has a layer of adhesive (5) applied on one side, the layer of adhesive (5) losing its adhesive force to the greatest extent when irradiated. Furthermore, the support (4) has solder ball elements (1), which are arranged closely packed in rows (6) and columns (7) on the layer of adhesive (5) in a prescribed pitch (w) for a semiconductor chip or a semiconductor component.

Abstract: Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.

Abstract: The invention provides an alignment checking structure with a checkered pattern comprising a plurality of metal squares and a plurality of non-metal squares that are arranged in alternation, in a first direction and a second direction, and the first direction is perpendicular to the second direction

Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Abstract: An accelerated fuel passage of an accelerator pump operatively connected with a throttle shaft having a throttle valve. The accelerated fuel passage is connected to an upstream side of a needle orifice, which orifice is coupled to a main nozzle. Consequently, the fuel is discharged by the accelerator pump into an area before the needle orifice. By the addition of a one-way check valve system in a fuel pick up at a metering chamber for a fuel circuit, the fuel driven by the accelerator pump piston is discharged to a venturi tube of an intake passage through the main nozzle. A self pumping effect caused by an engine pulsation is dampened or eliminated by the needle orifice. Further, a check valve is provided within a fuel pick up at a metering chamber for a fuel circuit, whereby the fuel driven by the accelerator pump piston is discharged to a venturi tube through a main nozzle without returning to the fixed fuel chamber.

Abstract: The invention relates to a method for separating a cast lens from shell molds, whereby a separating tool exerts pressure on the lens but a height of the separating tool is guided along the interface between the lens and the shell mold to be separated from the lens. In a preferred embodiment the composite consisting of the lens and the shell molds is fixed on a holding device that can be rotated on an axis of rotation. The holding device is rotated by means of a first motor and the height of the separating tool is tracked by means of a second motor in relation to the height of the interface depending on the angle of rotation.

Abstract: A method of fabricating an optical film is provided. The method includes nipping a film composed of a molten polycarbonate resin extruded in a film-forming manner from a die attached to an extruder, between a temperature-preset molding roll having an engraving pattern on the surface thereof and a temperature-preset elastic roll, and thereby transferring the engraving pattern onto the film; and allowing the film having the engraving pattern transferred thereon to travel around the molding roll, and then separating the film from the molding roll. In the method, a preset value of a surface temperature of the molding roll is adjusted within a range of Tg+20° C. or above and Tg+45° C. or below, where Tg is a glass transition temperature of the film, and a preset value of a surface temperature of the elastic roll is adjusted to Tg or below.

Abstract: A method for forming a film pattern made of a high-performance material by arranging a functional fluid on a base substrate and drying the functional fluid, the functional fluid being the high-performance material dissolved or dispersed in a solvent is provided. The method includes: forming liquid reception portions in an effective area and a non-effective area of the base substrate on which the film pattern is to be formed, the non-effective area surrounding the effective area; arranging the functional fluid in the liquid reception portions formed in the effective area; and arranging the functional fluid or the solvent in the liquid reception portions formed in the non-effective area, wherein, in the non-effective area, larger amounts of the solvent are arranged in the liquid reception portions in areas that are more distant from a center of the effective area.

Abstract: A process for producing an arched pane arrangement for a motor vehicle, using a flexible die (24), a plastic film (22) being pressed onto the arched glass pane (18) in order to form a film combination (26) and the film combination being subjected to heat treatment at an pressure which is below atmospheric pressure in order to laminate the plastic film onto the pane. The die (24) is thin glass or a metal foil with a layer thickness of less than 1 mm each.

Abstract: A process for producing an arched pane arrangement for a motor vehicle, using a flexible die (24), a plastic film (22) being pressed onto the arched glass pane (18) in order to form a film combination (26) and the film combination being subjected to heat treatment at an pressure which is below atmospheric pressure in order to laminate the plastic film onto the pane. The die (24) is thin glass or a metal foil with a layer thickness of less than 1 mm each.

Abstract: A process for producing an arched pane arrangement for a motor vehicle, using a flexible die (24), a plastic film (22) being pressed onto the arched glass pane (18) in order to form a film combination (26) and the film combination being subjected to heat treatment at an pressure which is below atmospheric pressure in order to laminate the plastic film onto the pane. The die (24) is thin glass or a metal foil with a layer thickness of less than 1 mm each.

Abstract: Vertical moulds are provided for making concrete pipes poles or piles. The mould can be opened along its length and has an internal flexible rubber or polymer liner (5) in which the edges of the mould shell (63), that seal together when the mould is closed, incorporate a sealing strip (51) bonded to the mould liner (5) and supported on flanges (53) running parallel to the edges of the mould shell the attachment of the sealing strip (51) to the flanges (53) being arranged to allow the sealing strip (51) to follow the movement of the mould liner (5) during opening of the mould and removal of the moulded article. When moulding long hollow concrete articles of constant cross section an expandable core is used which can be contracted to allow easy removal of the articles of constant cross section from the mould. Also disclosed is a method of moulding long concrete articles in which an homogenous concrete mixture is subjected to a moulding pressure above (5) bar in the absence of vibration.

Abstract: An advanced structural foam molding technology for improving the dispersion of the blowing agent in the polymer matrix has been invented. This technological innovation is an improvement on the well-known existing low-pressure structural foam molding technology based on the preplasticating-type (so-called piggy-bag) injection-molding machines. By introducing means for continuing the polymer matrix melt flow stream, preferably an additional accumulator and a gear primp, the processing conditions become more consistent to disperse the injected gas more uniformly in the polymer matrix. By using this technology, the structural foams have a smaller cell size, a more uniform cell structure, a larger void fraction (i.e., more material saving), less surface swirl, and less weld line contrast.

Abstract: A form in place conductive gasket is disclosed. The gasket, foamed, gelled or unfoamed is made of one or more elastomer resins, such as silicone urethane and/or thermoplastic block copolymers and is either filled with a conductive filler and lined onto a desired substrate or lined onto the substrate unfilled and then coated with a conductive outerlayer, such as a silver filled elastomer or a conductive flocked layer. A process and system for making the gaskets are also disclosed.