Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed in the upper part of the semiconductor substrate so as to be spaced; a channel region formed in a part of the semiconductor substrate between the source region and the drain region; a first dielectric film formed on the channel region of the semiconductor substrate; a second dielectric film formed on the first dielectric film and having a higher permittivity than the first dielectric film; a third dielectric film formed on at least an end surface of the second dielectric film near the drain region out of end surfaces of the second dielectric film near the source and drain regions; and a gate electrode formed on the second dielectric film and the third dielectric film.

Abstract: A semiconductor device having at least one lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a lateral channel above the conductive substrate. The semiconductor device further includes a second contact above the lateral channel. The semiconductor device still further includes an interconnect having a sloped wall that connects the lateral channel to the conductive substrate. The interconnect is operable to provide a low resistance coupling between the first contact and the lateral channel. In a related but alternative embodiment, the first contact is a source contact and the second contact is a drain contact for the semiconductor device.

Abstract: A p-type base layer shaped like a well is formed for each of IGBT cells, and a p+-type collector layer and an n+-type cathode layer are formed on a surface opposite to a surface on which the p-type base layer is formed so as to be situated just below the p-type base layer. The p-type base layer of each of the IGBT cells includes a flat region including an emitter region and a bottom surface penetrated by a main trench, and first and second side diffusion regions between which the flat region is interposed. The first side diffusion region is situated just above the n+-type cathode layer and each of the bottom surfaces of the side diffusion regions forms a parabola-shaped smooth curve in longitudinal section. By replacing the p+-type collector layer with the n+-type cathode layer, it is possible to apply features of the above structure to a power MOSFET.

Abstract: A semiconductor device for preventing a parasitic bipolar transistor from operating while reducing the ON resistance of a double-diffused MOS transistor. Boron having a relatively high solid solubility limit in silicon and indium having a relatively low solid solubility limit in silicon are diffused as p-type impurities into a body region. The concentration ratio of indium with respect to boron is higher in the vicinity of a source diffusion layer in the body region than in other portions. Thus, indium that does not solidify remains in the lattice of silicon. This reduces the lifetime of carriers in the body region and prevents the parasitic bipolar transistor from operating. The lateral junction abruptness at a pn junction between the body region and the source diffusion layer is improved, and the ON resistance of the DMOS transistor is reduced.

Abstract: A synchronous rectifier comprising a MOSFET device, and a gate driver for driving the gate of the MOSFET device, the MOSFET device comprising first and second MOSFET transistors coupled with their drain-source paths in parallel to receive an alternating current waveform for rectification by the drain-source paths of the MOSFET transistors, the first transistor having a low Rdson and the second transistor having a high Rdson whereby the apparent Rdson of the MOSFET device is increased when the current through the MOSFET device is below a threshold thereby enabling zero crossing detection.

Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: A semiconductor device includes: a semiconductor substrate having a first semiconductor layer, an insulation layer and a second semiconductor layer, which are stacked in this order; a LDMOS transistor disposed on the first semiconductor layer; and a region having a dielectric constant, which is lower than that of the first or second semiconductor layer. The region contacts the insulation layer, and the region is disposed between a source and a drain of the LDMOS transistor. The device has high withstand voltage in a direction perpendicular to the substrate.

Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.

Abstract: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.

Abstract: A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.

Abstract: A cell design and methods for reducing the cell size of cells in high-current devices, such as MRAM, by increasing the effective width of a transistor in the cell to be greater than the actual width of the active area of the cell are described. This permits the cell size to be decreased without decreasing the current that is driven by the transistor. According to the invention, this is achieved by increasing the length of gate portions of one or more transistors within the active area of a cell to increase the effective transistor width. In one embodiment, two transistors, electrically connected in parallel, are used per cell. The two transistors double the effective transistor width within the cell relative to a single transistor design. Such cell designs can be used with a variety of devices, including various types of MRAM and PCRAM.

Abstract: A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using one of the three states of the OTP memory whereby a higher utilization of OTP memory cells is achieved. Selecting and programming two conductive circuits of the OTP into two different operational characteristics thus enables the storing and sensing one of the three different states of the OTP memory. These two conductive circuits may include two different transistors for programming into a linear resistor and a nonlinear resistor with different current conducting characteristics. The programming processes include application of a high voltage and different programming currents thus generating different operational characteristics of these two transistors.

Abstract: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.

Abstract: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the second dielectric layer. A first layer of interconnect conductors is disposed on the second dielectric layer and includes a first interconnect conductor contacting a first contact area of the first thin film resistor, a second interconnect conductor contacting a second contact area of the first thin film resistor, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor. A third dielectric layer is disposed on the second dielectric layer. A second layer of interconnect conductors is disposed on the third dielectric layer including a fourth interconnect conductor for contacting the second interconnect conductor.

Abstract: A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.

Abstract: A power transistor has a source region, a drain region, a semiconductor body arranged between the source region and the drain region, and a plurality of nanotubes. The plurality of nanotubes are connected in parallel and disposed in the semiconductor body such that the plurality of nanotubes are electrically insulated from the semiconductor body and electrically connect the source and drain regions of the transistor. The power transistor also includes at least one diode formed in the semiconductor body. A portion of the at least one diode formed in the semiconductor body is configured to act as a gate electrode for the transistor.

Abstract: A method utilizing a common gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby.

Abstract: According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising: forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate, and forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate; forming a first insulating film on side surfaces of the first gate electrode and the first gate insulating film, and forming a second insulating film on side surfaces of the second gate electrode and the second gate insulating film; forming a mask having a pattern corresponding to the P-type semiconductor region; etching away the second insulating film by using the mask; removing the mask; and forming a first gate electrode sidewall insulating film on the side surfaces of the first insulating film, and forming a second gate electrode sidewall insulating film on the side surfaces of

Abstract: A semiconductor device includes: a first element region and a second element region formed on a substrate to be adjacent to each other with an isolation region interposed therebetween; a first gate insulating film formed on the first element region; a second gate insulating film formed on the second element region; and a gate electrode continuously formed on the first gate insulating film, the isolation region and the second gate insulating film. The gate electrode includes a first silicided region formed to come into contact with the first gate insulating film, a second silicided region which is formed to come into contact with the second gate insulating film and is of a different composition from the first silicided region, and a conductive anti-diffusion region composed of a non-silicided region formed in a part of the gate electrode located on the isolation region and between the first element region and the second element region.

Abstract: Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (3P1, 3P2; 3N1, 3N2). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (3I).

Abstract: An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.

Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate and defining a device region. A MOSFET includes a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and a source/drain diffusion area sandwiching a channel region below the gate electrode. A stress film is continuously formed over the gate electrode and source/drain diffusion area and in the trench and applies a tensile stress or compressive stress to the semiconductor substrate. An insulating film buries the trench via the stress film.

Abstract: Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides are formed on the first well. On one side of the field insulator is formed a first conductive type second well and a source region formed therein. On the other side of the field insulator is formed an isolated drain region. A gate electrode is formed on the gate insulating layer on the source region and a first field plate is formed on a portion of the field insulator and connected with the gate electrode. A second field plate is formed on another portion of the field insulator and spaced apart from the first field plate.

Abstract: A substrate having a buried well is provided. The substrate may be formed by implanting ions in a surface well of a first substrate and subsequently forming a semiconductor layer, such as an epitaxial layer, over the surface well. In this manner, the surface well becomes a buried well having a semiconductor layer that is substantially undoped formed thereon. In an embodiment, a transistor is formed on the substrate. Because the epitaxial layer is substantially undoped, the transistor may be formed such that the junction capacitance between the source/drain regions and the underlying region is reduced. If desired, the epitaxial layer, or a portion thereof, may be doped to decrease the resistance between the channel region and the well contact.

Abstract: A silicon controlled rectifier (SCR) may include a first well and a second well formed within a substrate. A first junction region and a second junction region may be formed within the first well. A third junction region may include a first portion formed within the first well and a second portion formed within the substrate. A fourth junction region may include a first portion formed within the second well and a second portion formed within the substrate. A gate electrode may be formed on the substrate between the third junction region and the fourth junction region. A fifth junction region may be formed within a region of the substrate.

Abstract: A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure.

Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region formed in the semiconductor substrate and surrounded by the isolation region; a fully-silicided gate line formed on the isolation region and the active region; and an insulating sidewall continuously covering a side face of the gate line. At least a portion of the gate line has a projection projecting from the sidewall.

Abstract: A hydrogen gas sensitive semiconductor sensor including a catalytic metal layer, a semiconductor layer and an insulator layer arranged between the catalytic metal layer and the semiconductor layer. The catalytic metal layer includes an outer surface and an inner surface including at least one hydrogen atom adsorption surface portion. Each hydrogen atom adsorption surface portion is arranged adjacent to the insulator layer. The surface area of the outer surface is at least 100% larger than the total surface area of all of the at least one hydrogen atom adsorption surface portion. A probe includes the sensor, A hydrogen gas detection system includes the sensor. Use of the sensor for detection of presence of and/or measurement of concentration of hydrogen gas in a gas sample.

Abstract: A MRAM memory and process thereof is described. A GMR magnetic layer is patterned to form a memory bit layer and an intermediate conductive layer. The intermediate conductive layer is disposed between two conductive layers such that shallow metal plugs can be utilized to interconnect the intermediate conductive layer and the conductive layers. Thus, a conventional deep tungsten plug process, interconnecting two conductive layers, is eliminated.

Abstract: An image sensor with an image area having a plurality of photodetectors of a first conductivity type includes a substrate of the second conductivity type; a first layer of the first conductivity type spanning the image area; a second layer of the second conductivity type; wherein the first layer is between the substrate and the second layer, and the plurality of photodetectors is disposed in the second layer and abut the first layer.

Abstract: An image sensor capable of improving the performance of a transistor of a peripheral circuit region while maintaining high picture quality, and a method of manufacturing the same are disclosed. The image sensor may include a semiconductor substrate having an active pixel region and a peripheral circuit region, a first gate pattern formed on the semiconductor substrate in the active pixel region, and a second gate pattern formed on the semiconductor substrate in the peripheral circuit region and made of a second material layer. The second gate pattern may also include the first material layer.

Abstract: An optoelectronics processing module includes a transparent substrate and at least one optoelectronics component. One surface of the transparent substrate is formed with a plurality of first pads and a plurality of second pads. The optoelectronics component mounted on the transparent substrate has a plurality of connecting pads, which is irradiated with a laser beam and is then connected with the first pads.

Abstract: A method for manufacturing a physical quantity sensor having a movable portion, a support portion and an optical part is provided. The method includes steps of: etching a silicon substrate so that a movable-portion-to-be-formed portion, a support-portion-to-be-formed portion, and an optical-part-to-be-formed portion having a plurality of columns and trenches are formed; oxidizing the optical-part-to-be-formed portion so that each column changes to a silicon oxide column and the trench is filled with a silicon oxide layer; and removing a part of the movable-portion-to-be-formed portion connecting to the silicon substrate so that the movable portion is separated from the silicon substrate.

Abstract: A solid-state imaging device includes: a base made of an insulation material and having a frame form in planar shape with an aperture formed at an inner region; a plurality of wirings provided on one surface of the base and extending toward an outer periphery of the base from a region along the aperture; and an imaging element mounted on the surface of the base with wirings provided thereon so that a light-receptive region of the imaging element faces the aperture. An end portion on the aperture side of each of the plurality of wirings forms an internal terminal portion and an end portion on the outer peripheral side of each of the plurality of wirings forms an external terminal portion, the internal terminal portion of the wiring being connected electrically with an electrode of the imaging element.

Abstract: A wiring structure may include a pad, a conductive pattern and an insulating photoresist structure. The pad may be provided on a body and electrically connected to a circuit unit of the body. The conductive pattern may be provided on the body and may be electrically connected to the pad. The insulating photoresist structure may be provided on a surface of the conductive pattern. The insulating photoresist structure may have a contact hole through which the conductive pattern may be partially exposed. The insulating photoresist structure may be fabricated by providing a photosensitive photoresist film on the conductive layer, and patterning the photosensitive photoresist film by two photo processes.

Abstract: A CIS and a method of manufacturing the same are provided. The CIS includes a device isolation layer formed on a device isolation region of a substrate of a first conductive type, the substrate including an active region and the device isolation region, the active region including a photodiode region and a transistor region; a high-concentration diffusion region of the first conductive type formed around the device isolation layer; a gate electrode formed on the active region of the substrate with a gate insulation layer interposed therebetween; a low-concentration diffusion region of a second conductive type formed on the photodiode region and spaced a predetermined distance apart from the device isolation layer; and a high-concentration diffusion region of a second conductive type formed on the transistor region.

Abstract: Provided is a CMOS image sensor and method of manufacturing same. The CMOS image sensor includes a photodiode, a transfer transistor, a reset transistor, a drive transistor, and a select transistor. A device isolation layer is formed on a first conductive type substrate. Gate electrodes of the transfer transistor, the reset transistor, the drive transistor, and the select transistor are formed on an active region of the substrate with gate insulating layers interposed therebetween. A first diffusion region is formed of a second conductive type in a first region of the active region, where the first region does not include a floating diffusion region between the transfer transistor and the reset transistor and the photodiode region. A second diffusion region is formed of the second conductive type in the floating diffusion region at a concentration lower than that of the second conductive type first diffusion region.

Abstract: A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried regions 44a of the second conductivity type are provided on the bottom surface of the base diffusion regions 17a. A distance between adjacent base buried regions 44a at the bottom of the same base diffusion region 17a is Wm1, a distance between adjacent base buried regions 44a at the bottom of the different base diffusion regions 17a is Wm2, and a distance between the guard buried regions 44b is WPE. A ratio of an impurity quantity Q1 of the first conductivity type and an impurity quantity Q2 of the second conductivity type included inside the widthwise center of the innermost guard buried region 44b is 0.90<Q2/Q1 when Wm1<WPE<Wm2.

Abstract: A production method for a semiconductor device, including the steps of: forming a semiconductor layer of the first conductivity on the semiconductor substrate; forming a trench in the semiconductor layer, the trench penetrating through the semiconductor layer to reach the semiconductor substrate; filling a filling material in a predetermined bottom portion of the trench, so that a filling material portion is provided in the bottom portion of the trench up to a predetermined upper surface position which is shallower than an interface between the semiconductor substrate and the semiconductor layer; and, after the filling step, introducing an impurity of the second conductivity into a portion of the semiconductor layer exposed to an interior side wall of the trench.

Abstract: Mounting components such as LSIs, which emit noise to the outside and are subjected to the influence of external noise, on the top-most layer and the bottom-most layer respectively, a co-existing layer of the ground region and the power source region has been employed, where a ground region has been provided respectively to the range corresponding to the position the LSIs on the next layer below the top-most layer and the next layer above the bottom-most layer. Accordingly, the number of layers to be laminated to form the multilayer substrate has been reduced, because it is no longer required, unlike the related art, to provide a ground layer where the ground pattern is formed substantially over the entire surface of layer respectively to the next layer below the top-most layer having mounted a LSI thereon and of the next layer above the bottom-most layer having mounting a LSI thereon.

Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

Abstract: In a method for manufacturing an integrated semiconductor device with low capacitive coupling between a conductive member and a via, a semiconductor substrate with a surface is provided. The conductive member is formed on the surface of the substrate wherein the conductive member is provided for conducting a current in a direction parallel to the surface of the substrate. A sacrifice structure is produced. A via is formed for conducting a current in a direction vertical to the surface of the substrate. The sacrifice structure at least partially defines the shape and position of the via and separates the conductive member and the via. The sacrifice structure is removed thereby generating a void in place of the sacrifice structure.

Abstract: A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying the masking layer. The light sensitive layer is patterned and etched to form a pattern of openings therein. The masking layer and the conductor layer are etched according to the pattern of openings in the light sensitive layer. The conductor layer is etched at the outer surface area between the conductor layer and the dielectric layer to form undercuts. The dielectric layer is etched to form a notch profile at the outer surface area between the conductor layer and the dielectric layer and portions of the substrate are etched to form a plurality of trenches. An isolation layer is filled over the plurality of trenches and the masking layer.

Abstract: A semiconductor device exhibiting low parasitic resistance comprises a first substrate characterized by a first resistivity; a second substrate characterized by a second resistivity, a third substrate and a metal element. These substrates form a multi-layer semiconductor device where the second substrate is formed on the first substrate; the third substrate is formed on the second substrate; and the metal element is formed on the third substrate. The second substrate is electrically grounded and is highly doped with acceptor dopant as compared to the first substrate. In this way, the second resistivity is lower than the first resistivity.

Abstract: A fuse structure on a peripheral region of a substrate, the fuse structure comprising a plurality of fuses disposed on a plane and parallel to each other, wherein each fuse has a melting block and the melting blocks are arranged in a staggered form. Because of the fuse structure with melting blocks disposed in a staggered arrangement, the pitch of the fuses is relatively small and the size of the semiconductor device is decreased.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.

Abstract: A waveguide structure includes a SOI substrate. A core structure is formed on the SOI substrate comprising a plurality of multilayers having alternating or aperiodically distributed thin layers of either Si-rich oxide (SRO), Si-rich nitride (SRN) or Si-rich oxynitride (SRON). The multilayers are doped with a rare earth material so as to extend the emission range of the waveguide structure to the near infrared region. A low index cladding includes conductive oxides to act as electrodes.

Abstract: An inductor structure comprised of a magnetic section and a single turn solenoid The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.

Abstract: An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor.