Abstract: The bonding surfaces of an active layer wafer and a supporting wafer have fitting surfaces each comprising a part of a spherical surface of the same curvature, and they are to be bonded together with their bonding surfaces superposed with each other. As a result, an area left as not-bonded in the outer peripheral portion of the bonded wafer is reduced and thus a fixed quality area can be expanded. Therefore, the yield of the bonded SOI wafer becomes high, and the chipping, wafer peel-off and the like phenomenon in the subsequent steps of wafer processing can be reduced.

Abstract: Techniques for an integrated circuit device are provided. The integrated circuit device includes a substrate, an active circuit area, and a dielectric layer. A seal ring surrounds the active circuit area. At least one corner area of the integrated circuit includes a plurality of corner band stacks. Each of the plurality of corner band stacks is oriented at about a predetermined angle and extends from a first sawing trace to a second sawing trace. In a specific embodiment, if a structural fault in the at least one corner area occurs, the structural fault is predisposed to extend at about the predetermined angle.

Abstract: A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each dielectric layer. The metal patterns disposed in each dielectric layer extend to the next underlying dielectric layer.

Abstract: (1) A metal oxide dispersion for a dye-sensitized solar cell, which contains metal oxide fine particles, a binder composed of a polymer compound having an action to bind to the fine particles and a solvent; (2) a method for producing a photoactive electrode for a dye-sensitized solar cell by coating a dispersion containing the above-mentioned binder and metal oxide fine particles on a sheet-shaped electrode; (3) a photoactive electrode for a dye-sensitized solar cell, obtained by the method, which electrode has metal oxide containing the above-mentioned binder and metal oxide fine particles; and (4) a dye-sensitized solar cell with the above-mentioned photoactive electrode.

Abstract: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having Josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit having Josephson junctions formed by the use of an oxide high-temperature superconductor are connected is located in a low temperature environment kept at 4.2 K. The oxide high-temperature superconducting latch interface circuit is connected to a high-speed semiconductor amplifier and a signal outputted from the Nb superconducting circuit is transmitted to the high-speed semiconductor amplifier.

Abstract: It is an object of the present invention to provide a device which can pick up a chip from an adhesive film while preventing damage to the chip. In addition, a device which can pick up a chip over an adhesive film with a high yield is provided. A pickup device includes: a frame for holding a film to which a chip is attached, which is fixed to a support; a pressing jig which presses a surface of the film, to which a chip is not attached, while rotated or moved; a holding jig which holds the chip simultaneously with or after the pressing jig pressing the film; and a moving unit which moves the holding jig.

Abstract: A plurality of radio semiconductor chips each having a plurality of electrodes on a surface thereof is provided. By establishing connection between the respective electrodes of the semiconductor chips by wires in a chain form, continuous manufacture of inlets becomes possible. The effect of reducing the cost of a radio recognition semiconductor device can be thereby brought about.

Abstract: A first electrode is formed on a semiconductor substrate. A second electrode is formed separately at a predetermined interval from the first electrode, and has at least one opening. An actuator layer is connected to the second electrode, and drives the second electrode.

Abstract: A molded semiconductor package has a lead frame to which an LSI is bonded, inner lead frames located on opposing sides of the lead frame, and wires. Each wire is connected between the LSI and a corresponding one of the inner lead frames. A distance between an edge of the lead frame (or an edge of the molded semiconductor package) and an end of inner lead frame is larger than a distance between another edge of the lead frame (or another edge of the molded semiconductor package) and an edge of an inner lead frame to minimize the length of wires connected to the lead frame.

Abstract: To prevent any uneven solder wetting in a main surface of electrodes of a semiconductor connected with a main surface of a planar lead and any displacement of the lead vis-a-vis the electrodes due to the reflow of the solder in a semiconductor module having the semiconductor element mounted on a substrate and the planar lead electrically connected therewith, the present invention provides an improved semiconductor module characterized in that the width of at least a part of the region of the main surface of the lead facing the semiconductor element is expanded wider than or equal to the width of the electrodes formed on the semiconductor element, and preferably the other part of the main surface of the lead soldered to an electrode formed on the substrate is split in the extending direction thereof.

Abstract: The present invention relates to a package of a leadframe with heatsinks. The package of the invention comprises a leadframe, a die, a first heatsink and a second heatsink. The leadframe has a die pad and a plurality of leads, and the leads are disposed around the die pad. The die is disposed on the die pad. The first heatsink is disposed on a first side of the leadframe and has a plurality of first positioning portions. The second heatsink is disposed on a second side of the leadframe. The second heatsink has a plurality of second positioning portions. The second positioning portions are corresponding to the first positioning portions of the first heatsink, whereby the warped problem of the leadframe will be resolved.

Abstract: An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer. UBM pads of at least two different sizes are formed from the UBM layers. Solder paste is printed over at least some of the UBM pads. The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads. Bigger solder bumps are formed on at least some of the UBM pads.

Abstract: A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures, and a third metallization structure connecting said first and second metallization structures.

Abstract: An integrated circuit package includes a first non-conductive substrate having a first inner surface and a second non-conductive substrate having a second inner surface. A die having a first thickness is disposed between the first and second inner surfaces. A leadframe includes a member having a proximal end and a distal end. The proximal end has a second thickness less than the first thickness. The distal end is disposed between the first and second inner surfaces. The distal end is undulated such that the distal end has an effective thickness greater than the second thickness.

Abstract: A method of manufacturing a multi-substrate semiconductor package. The method includes providing a first substrate with a plurality of first dies present thereon and forming a plurality of electrical contacts on an upper surface of a lateral extension portion of at least one of the plurality of first dies on the first substrate. The method also includes providing a second substrate, the second substrate comprising a plurality of second dies, at least one of the plurality of second dies comprising an interconnect region. Further, the method includes forming a sandwich structure by bonding the second substrate to an upper surface of the first substrate to form an intermediate level within the sandwich structure and separating the dies. The method also includes coupling an electrically conductive structure through the interconnect region of the one second dies to the lateral extension portion of the one first die.

Abstract: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces.

Abstract: The invention relates to a carrier for a substrate, wherein at least parts of the carrier are comprised of a material with a coefficient of thermal expansion which is higher than the coefficient of thermal expansion of the substrate. In order to avoid, or at least decrease, the nonuniform coating of the substrates at the margins, in particular during sputtering processes, a web is centrally connected with the carrier. This web has a lower coefficient of thermal expansion than the region of the carrier on which it is fastened.

Abstract: A bumpless chip package comprising a supporting component, a chip, a metal-filled layer and an interconnection structure is provided. The supporting component has a supporting surface and a cavity. The chip is disposed within the cavity and has a plurality of chip pads formed on an active surface of the chip, wherein the active surface is upward. The metal-filled layer is filled in a space formed between the chip and the cavity. The interconnection structure is formed above the active surface of the chip and the supporting surface of the supporting component, and has an inner circuit and a plurality of contact pads. The contact pads are formed on a contact surface of the interconnection structure. At least one of the chip pads is electrically connected with at least one of the contact pads by the inner circuit.

Abstract: A semiconductor device with plastic housing composition includes an internal wiring that is electrically insulated from the plastic housing composition by an insulation layer. The plastic housing composition has a high thermal conductivity and a low coefficient of expansion, the coefficient of expansion being adapted to the semiconductor chip of the semiconductor device. This is achieved by forming the plastic housing composition with electrically semiconducting and/or electrically conducting filler particles. In particular, this plastic housing composition is advantageously used for semiconductor devices with flip-chip contacts and/or for semiconductor devices which are constructed according to the “universal packaging concept”.

Abstract: A semiconductor sensor device includes a sensor chip. The sensor chip includes a sensor region and contact areas on its upper side and is further arranged in a cavity housing. The cavity housing includes side walls, a housing bottom, a cavity, external contacts on the outside of the cavity and contact pads on an upper side of the housing bottom facing the cavity. The sensor chip is embedded into a rubber-elastic plastic composition within the cavity of the cavity housing such that the sensor region of the sensor chip faces the housing bottom and the contact areas of the sensor chip are electrically connected to the contact pads on the housing bottom via elastic flip-chip contacts.

Abstract: A ball grid array (BGA) package that may suppress flash contamination may include a flash contamination barrier wall. The barrier wall may be a portion of a copper pattern provided on a substrate. During a molding process, the flash contamination barrier may prevent a flash from contaminating a ball land. The barrier wall may restrict the flash to flow through a concave portion that may be defined by a surface of the substrate.

Abstract: An optical parts cap of the present invention includes a metal frame having an upper frame portion in which an opening portion is provided to a center portion and an upright frame portion provided to be connected to a lower peripheral portion of the upper frame portion, the metal frame in which a housing portion is provided in an inside of the metal frame by the upright frame portion, a reflection preventing layer formed on an outer surface and an inner surface of the metal frame respectively, and a glass provided to the housing portion of the metal frame, the reflection preventing layer is formed of either the metal oxide layer or the metal plating layer.

Abstract: A system is provided. The system includes a device that includes top and bottom thermally conductive substrates positioned opposite to one another, wherein a top surface of the bottom thermally conductive substrate is substantially atomically flat and a thermal blocking layer disposed between the top and bottom thermally conductive substrates. The device also includes top and bottom electrodes separated from one another between the top and bottom thermally conductive substrates to define a tunneling path, wherein the top electrode is disposed on the thermal blocking layer and the bottom electrode is disposed on the bottom thermally conductive substrate.

Abstract: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by a stiffening frame. Due to the nature of the manufacturing of the system board, there can be significant gaps formed in the mounting area of the MCM between the board and the stiffener. A method is described that not only fills the void, it also, in addition promotes thermo conduction of excess heat away from the MCM and at the same time promotes enhanced electrical properties of the LGA connections of the MCM to the system board.

Abstract: Provided are a plasma display panel and a method of manufacturing the same. The plasma display panel includes a plurality of substrates; a plurality of discharge electrode pairs formed on an inner surface of one of the substrates; a dielectric layer burying the discharge electrode pairs; barrier ribs disposed between the substrates to define a plurality of discharge cells; red, green, and blue phosphor layer coated on inner walls of the discharge cells, wherein one of the substrate s comprises a display area where an image is displayed and a non-display area corresponding to an edge of the display area and to a region where the discharge electrode pairs are connected to external terminals, and the thickness of the dielectric layer coated in the non-display area gradually increases to a boundary region between the display area and the non-display area, after which the dielectric layer is maintained at a uniform thickness in the display area.

Abstract: Disclosed herein are a semiconductor package substrate and a method for fabricating the same. In the semiconductor package substrate, the circuit layer of the wire bonding pad side differs in thickness from that of the ball pad side to which a half etching process is applied. In addition, a connection through hole is constructed to provide an electrical connection between the plating lead lines on the wire bonding pad side and the ball pad side, thereby preventing electrical disconnection when the plating lead line of the wire bonding pad side is cut.

Abstract: A chip package coupled to a circuit board includes a substrate and at least one chip. The substrate includes a plurality of first pads, a plurality of second pads and at least one first interconnecting structure. The first pads and the chip are located on a first surface of the substrate and the second pads are located on a second surface of the substrate. The first interconnecting structure is coupled with the chip, one of the first pads and one of the second pads for flexible design of various applications. A substrate of the chip package is also disclosed.

Abstract: Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.

Abstract: A semiconductor IC-embedded substrate suitable for embedding a semiconductor IC in which the electrode pitch is extremely narrow. The substrate comprises a semiconductor IC 120 in which stud bumps 121 are provided to the principal surface 120a, a first resin layer 111 for covering the principal surface 120a of the semiconductor IC 120, and a second resin layer 112 for covering the back surface 120b of the semiconductor IC 120. The stud bumps 121 of the semiconductor IC 120 protrude from the surface of the first resin layer 111. The method for causing the stud bumps 121 to protrude from the surface of the first resin layer 111 may involve using a wet blasting method to cause an overall reduction of the thickness of the first resin layer 111. The stud bumps 121 can thereby be properly uncovered even when the electrode pitch of the semiconductor IC 120 is narrow.

Abstract: A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 100 includes: a silicon substrate 101; a through electrode 129 extending through the silicon substrate 101; and a first insulating ring 130 provided in a circumference of a side surface of the through electrode 129 and extending through the semiconductor substrate 101. In addition, the semiconductor device 100 also includes a protruding portion 146, being provided at least in the vicinity of a back surface of a device-forming surface of the semiconductor substrate 101 so as to contact with the through electrode 129, and protruding in a direction along the surface of the semiconductor substrate 101 toward an interior of the through electrode 129.

Abstract: Disclosed herein are novel damage detection circuitries implemented on the periphery of a semiconductor device. The circuitries disclosed herein enable the easy identification of cracks and deformation, and other types of damage that commonly occur during test and assembly processes of semiconductor devices.

Abstract: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding an integrated circuit. The base element and support members reduce warpage due to thermal expansion mismatches between at least the integrated circuit and the substrate. In one embodiment, the elongated support members are detachable from the corners of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the corners of the base element. In yet another embodiment, the elongated support members are detachable from about the midsections of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the midsections of the base element.

Abstract: A die structural support apparatus and method are disclosed, in which a die component is provided. A support element can be configured for use with the die component, wherein said support element surrounds said die component, thereby strengthening said die component to provide a surrounding die support structure thereof. The die component preferably constitutes a SAW die, and may be formed from, for example, quartz. The support element can be molded, stamped, cast, machined and so forth and is preferably located with respect to the SAW die after the SAW die is formed.

Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Abstract: A heat dissipation device includes a chip unit and a heat dissipation unit thermally attached to the chip unit. The chip unit includes a carrier substrate and a chip in electrical contact with the carrier substrate. The heat dissipation unit includes a heat spreader thermally contacting with the chip and a heat dissipation member coupled to the heat spreader. The heat spreader and the heat dissipation member are integrated together before they are attached to the chip unit.

Abstract: A semiconductor device 1 includes a substrate 10, a semiconductor chip 20 (first semiconductor chip), semiconductor chips 30 (second semiconductor chips) and a heat sink 40. Semiconductor chips 20 and 30 are mounted on the substrate 10. The level of the top surface of the semiconductor chip 20 on the substrate 10 is lower than the level of the top surface of the semiconductor chip 30. A heat sink 40 is fixed to the semiconductor chip 20. Among the semiconductor chip 20 and the semiconductor chips 30, only above the semiconductor chip 20 is provided with the heat sink 40.

Abstract: A package for an IC includes a carrier with a cavity formed on one of the major surfaces. Bumps of a semiconductor die are mated to contact pads located on the bottom of the cavity. The die is attached to the major surface of the carrier. The major surface creates a support which securely holds the chip in place with adhesive for assembly.

Abstract: An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of the opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface of the semiconductor chip.

Abstract: An electrical or mechanical device which tends to heat up during operation, which bears on its surface a roughening coating comprised of thermally conductive material which aids in cooling the device.

Abstract: A Flash memory card is disclosed comprising a substrate, a Flash memory die on top of the substrate, a controller die on top of the Flash memory die, and an interposer coupled to with the controller die and on top of the Flash memory die wherein the interposer results in substantial reduced wire bonding to the substrate. The interposer can surround or be placed side by side with the controller die. A system and method in accordance with the present invention achieves the following objectives: (1) takes advantage of as large of a Flash memory die as possible, to increase the density of the Flash card by reducing the number of wire bond pads on the substrate and enabling insertion of the largest die possible that can fit inside a given card interior boundary; (2) more efficiently stacks Flash memory dies to increase density of the Flash card; and (3) has a substantially less number of bonding wires to the substrate as possible, to improve production yield.

Abstract: A semiconductor device of the present invention has a base plate, a digital circuit section provided on a side of an upper surface of the base plate and having a plurality of external connection electrodes, an insulating layer provided on the base plate around the digital circuit section and on the digital circuit section, a plurality of upper conductive layers provided on the insulating layer and connected to the external connection electrodes of the digital circuit section, a plurality of lower conductive layers provided on a side of a lower surface of the base plate, an upper and lower conducting portion which penetrates the base plate and the insulating layer and connects at least one of the upper conductive layers with at least one of the lower conductive layers, an analog circuit section connected to at least one of the upper conductive layers and one of the lower conductive layers, and a shield cover covering the analog circuit section.

Abstract: A panel for the production of electronic components is disclosed. The components have a substantially planar semiconductor chip with chip through-contacts which are provided with electrically conductive material. A rewiring region is subdivided into an insulating layer and also a first rewiring arranged therein, the rewiring projecting laterally beyond the side edge of the planar semiconductor chip. The rewiring has external contacts for electrical connections toward the outside. The panel provides a filling layer made of plastic, which encapsulates the semiconductor chip in a side region between the chip front side and the chip rear side and which is connected to the rewiring region.

Abstract: A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole (360), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals (130) is bonded to a second integrated circuit (310) containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate (330). The interposer contains a ground structure, or ground structures (390, 510), that shield circuitry from the clock distribution network. Conductive lines (150) in an integrated circuit are formed in trenches (610) in a semiconductor substrate.

Abstract: In one embodiment, a semiconductor module includes at least one semiconductor chip package, a board having functional pads and dummy pads, and at least one solder joint electrically connecting the semiconductor chip package and one of the functional pads of the board. Furthermore, at least one supporting solder bump is formed on one of the dummy pads and disposed under a portion of the semiconductor chip package. For example, the supporting solder bump may be disposed under a peripheral area of the semiconductor chip package.

Abstract: A Sn—Ag—Cu based lead-free solder ball which does not undergo yellowing of its surface when formed into a solder bump on an electrode of an electronic part such as a BGA package. The solder ball has excellent wettability and does not form voids at the time of soldering, even when it has a minute diameter such as 0.04-0.5 mm. It has a composition comprising 1.0-4.0 mass % of Ag, 0.05-2.0 mass % of Cu, 0.0005-0.005 mass % of P, and a remainder of Sn.

Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.

Abstract: Interconnect structures with polygonal cell structures. An exemplary interconnect structure comprises a substrate and a first dielectric layer, overlying the substrate and exposing a conductive feature formed therethrough and connected with the substrate, wherein the first dielectric layer includes a plurality of polygon cell structures with hollow interior.

Abstract: The invention includes a layer having an integrated circuit, a first terminal which is formed over the layer having the integrated circuit and is electrically connected to the layer having the integrated circuit, a conductive layer which functions as an antenna, which is formed over the first terminal and is electrically connected to the first terminal, and a second terminal which is formed over the layer having the integrated circuit and is not electrically connected to the layer having the integrated circuit, the conductive layer which functions as the antenna, and the first terminal.

Abstract: A semiconductor device containing a ruthenium diffusion barrier and a method of forming and integrating the ruthenium diffusion barrier with bulk Cu. The method includes forming the Ru diffusion barrier by depositing a first Ru layer onto a substrate in a first CVD process, modifying the first Ru layer by oxidation, or nitridation, or a combination thereof, depositing a second Ru layer on the modified first Ru layer, and plating a Cu layer onto the Ru diffusion barrier. According to one embodiment of the invention, the Ru diffusion barrier is treated and/or an ultra thin Cu layer deposited on the Ru diffusion barrier prior to Cu plating.

Abstract: A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A , a second metal layer 113 formed in the hole 112A , a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.