Abstract: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.

Abstract: Channel stop sections are formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.

Abstract: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide 3,4,9,10-perylene-based compound having, attached to each of the imide nitrogen atoms a substituted or unsubsitituted phenylalkyl group. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating an organic thin-film transistor device, preferably by sublimation or solution-phase deposition onto a substrate, wherein the substrate temperature is no more than 100° C.

Abstract: In a semiconductor-device fabrication method, a plurality of recessed portions are first formed in the principal surface of a substrate. Then, a through hole, passing through the substrate in the front-to-back direction of the substrate, is formed under a portion of the bottom of each recessed portion in the substrate. Subsequently, a plurality of semiconductor elements in the form of chips are spread in a liquid, and the semiconductor-element-spread liquid is poured over the principal surface of the substrate, while passing the liquid through the through holes, so that the semiconductor elements fit into the recessed portions in a self-aligned manner. In this way, the semiconductor elements are disposed into the recessed portions in the substrate in a self-aligned manner.

Abstract: A method of stacking semiconductor chips includes providing four semiconductor chips that each include a top surface with central bond pads. Each of the bond pads is electrically coupled to second bond pads located in a peripheral portion of the semiconductor chip through a conductive layer. The first and the second semiconductor chips are arranged alongside one another on a carrier substrate. The second bond pads from the first and second semiconductor chips are bonded to corresponding landing pads on the substrate. The third semiconductor chip is then stacked over the first semiconductor chip and the fourth semiconductor chip over the second semiconductor chip. The second bond pads of the third and fourth semiconductor chips can then be bonded to contact pads of the substrate. The substrate can then be separated into a first stack that includes the first and third semiconductor chips and a second stack that includes the second and fourth semiconductor chips.

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed.

Abstract: A vacuum sealed SAW pressure sensor is disclosed herein, which includes a sensing element configured as a SAW device (e.g., SAW resonator or SAW delay line) supported by a thin diaphragm. The substrate material can be implemented as a quartz wafer (i.e., a “base” wafer). The SAW device can be configured on one side of the wafer and the diaphragm etched on the opposite side. A quartz micromachined pressure sensor can thus be realized, which operates based on a variation of the surface wave velocity of a SAW device situated on the thin diaphragm. The SAW sensor is generally sealed in a vacuum and diaphragm sustains the sensor, thereby implementing a sensor on a wafer scale while allowing for a cost reduction per chip.

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Abstract: The present invention provides a solder ball that has solved the problem of micro-adhesion and, moreover, has solved both of the problems of micro-adhesion and wetting properties, and a method for preventing the micro-adhesion of solder balls. That is, the present invention provides a solder ball obtained by solidification and spheroidization in a gas phase and having metal soap molecules, preferably a metal soap molecules film of 3 nm or less in thickness, adsorbed on its surface. As the metal soap, there can be used, for example, calcium stearate, magnesium stearate or barium stearate. The present invention is preferably applied to solder balls with a diameter of 400 ?m or less.

Abstract: A method of manufacturing a semiconductor device includes (a) interposing an adhesive between a surface of a substrate on which an interconnect pattern is formed and a surface of a semiconductor chip on which electrodes are formed; and (b) applying pressure between the semiconductor chip and the substrate, and covering with the adhesive at least a part of lateral surfaces of the semiconductor chip that is perpendicular to the surface of the semiconductor chip on which the electrodes are formed.

Abstract: An electronic parts built-in substrate of the present invention includes a wiring substrate having connecting pads, a first electronic parts a bump of which is flip-chip connected to the connecting pad, a second electronic parts having a larger area than an area of the first electronic parts a bump of which is flip-chip connected to the connecting pad arranged on an outside of a periphery of the first electronic parts and which is packaged at a predetermined interval over the first electronic parts, and a filling insulating body filled in a clearance between the first electronic parts and the wiring substrate and clearances between the second electronic parts and the first electronic parts and the wiring substrate, wherein the first electronic parts is buried in the filling insulating body.

Abstract: According to one exemplary embodiment, an overmolded package comprises a semiconductor die situated on a substrate. The overmolded package further comprises an overmold situated over the semiconductor die and the substrate, where the overmold has a top surface. The overmolded package further comprises a conductive layer situated on the top surface of the overmold, where the conductive layer comprises a conductive polymer, and where the conductive layer forms an EMI and RFI shield. According to this exemplary embodiment, the overmolded package can further comprise a post situated over the substrate, where the post is connected to the conductive layer. The overmolded package can further comprise a hole situated in the overmold, where the hole is situated over the post, where the hole is filled with the conductive polymer, and where the conductive polymer is in contact with the post.

Abstract: A method of protecting metal traces and contacts on a fabricated semiconductor wafer from mechanical damage during dicing of the fabricated wafer, where the metal traces and contacts form electrical connections with an active device region of the semiconductor. The method includes the steps of providing a group of discrete metal deposits adjacent the metal traces and contacts, wherein said metal deposits are substantially not contiguously connected to each other or to any traces or contacts of the active device regions of semiconductor die, attaching the fabricated wafer to an adhesive tape used for securing the fabricated wafer during a die separation process, separating the die from the fabricated wafer while attached to the adhesive tape and removing the die from the adhesive tape.

Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, to thereby enhance reliability and productivity of a semiconductor chip mounting line, and also provides a method of producing the COF flexible printed wiring board. The COF flexible printed wiring board contains an insulating layer, a wiring pattern, on which a semiconductor chip being mounted, formed of a conductor layer provided on at least one side of the insulating layer and a releasing layer, wherein the releasing layer is formed from a releasing agent containing at least one species selected from a silane compound and silica sol and is provided on a surface of the insulating layer, which is opposite to the mounting side of the semiconductor chip.

Abstract: A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78<x<92. The channel core 24 has a top surface 26 of width wc and an upstanding surface 28, 30 of height hc, preferably oriented 90° to one another. The channel envelope 32 is in contact with the top 26 and upstanding surfaces 28, 30 so that the area of interface is increased as compared to contact only along the top surface 26, improving electrical conductivity and gate 18 control over the channel 16. The height hc can be tailored to enable a smaller scale FET 10 within a stabilized SRAM. Various methods of making the channel 16 are disclosed, including a mask and etch method, a handle wafer/carrier wafer method, and a shallow trench method.

Abstract: The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semiconductor film to the semiconductor film containing a rare gas element by a heat treatment. Furthermore, a first impurity region and a second impurity region formed in a semiconductor layer of a first n-channel TFT are provided outside a gate electrode. A third impurity region formed in a semiconductor layer of a second n-channel TFT is provided so as to be partially overlapped with a gate electrode. A third impurity region is provided outside a gate electrode. A fourth impurity region formed in a semiconductor layer of a p-channel TFT is provided so as to be partially overlapped with a gate electrode. A fifth impurity region is provided outside a gate electrode.

Abstract: A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2) is disclosed using SOI starting material (4, 6, 8) and a selective epitaxial growth process (110).

Abstract: Dummy gate patterns 111, 112 are formed on a silicon active layer 103 of an SOI substrate, and thereafter, these dummy gate patterns 111, 112 are removed to form gate grooves 130, 132. A threshold voltage of each transistor is adjusted by etching a silicon active layer 103 in any one of these gate, grooves 130, 132 to reduce a thickness of a portion constituting a channel region. This enables the enhancement of freedom degree and so on in circuit designing according to conditions.

Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material form a first island and second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layer prior to forming finFETs. An Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask, now a capping layer which is under tension, preventing lateral buckling of the nFET fin.

Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.

Abstract: In a semiconductor substrate, a field effect transistor, and methods for producing the same, in order to lower threading dislocation density and also to lower surface roughness, a step of repeating, a plurality of times, a process of epitaxially growing a SiGe gradient composition layer of which a Ge composition ratio is gradually increased from a Ge composition ratio of a base material and a process of epitaxially growing a SiGe constant-composition layer on the gradient composition layer at a final Ge composition ratio of the gradient composition layer, thereby depositing a SiGe layer of which a Ge composition ratio changes in a film deposition direction, in a step-like manner with a gradient, a heat treatment step of performing heat treatment at a temperature exceeding a temperature of the epitaxial growth either during or after formation of the SiGe layer, and a polishing step of polishing to remove irregularities on a surface of the SiGe layer which arise in the heat treatment after formation of the SiGe

Abstract: A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS) is provided. A gate in a CMOS area and a conductive layer pattern defining an opening, which opens an active region in a bipolar transistor area, are simultaneously formed by patterning a gate conductive layer. Thereafter, bipolar transistor manufacturing processes are performed while CMOS manufacturing processes are performed. Accordingly, the number of masks is decreased, and degradation of device characteristics is prevented.

Abstract: A graded composition, high dielectric constant gate insulator is deposited between a substrate and floating gate in a flash memory cell transistor. If the composition of the gate insulator is closer to the high-k material near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the high-k material near the floating gate, the tunnel barrier can be lower at the floating gate.

Abstract: Several a transistor, which are inhibited short channel effect moderately according to each transistor's channel length, are formed on a same SOI substrate. In the present invention, forming a first transistor on SOI substrate, and forming a second transistor which has a gate electrode whose length is longer than a gate length of the first transistor in a channel direction The impurities are doped from above a surface of the SOI substrate in an oblique direction against the surface, and from source side and drain side of the first transistor and the second transistor. By this means, a pocket layer is formed under an insulator layer of a SOI substrate.

Abstract: A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

Abstract: A process for the fabrication of a ferroelectric capacitor comprising depositing a layer of Ti 5 over an insulating layer 3 of Al2O3, and oxidising the Ti layer to form a TiO2 layer 7. Subsequently, a layer of PZT 9 is formed over the TiO2 layer 7. The PZT layer 9 is subjected to an annealing step in which, due to the presence of the TiO2 layer 7 it crystallises to form a layer 11 with a high degree of (111)-texture.

Abstract: In a method of manufacturing a capacitor of a semiconductor device and an apparatus therefor, dielectric layers are deposited using only a source gas without a reactant gas and a curing process is performed a single time. As a result, process simplification, yield improvement, and equipment simplification are achieved. In a stand-alone memory or an embedded memory, the step coverage is enhanced and oxidation of a storage node contact plug is prevented. Also, in an analog capacitor, an RF capacitor, or a high-voltage capacitor, which uses thicker dielectric layers than the stand-alone capacitor or the embedded capacitor, the manufacturing process is greatly simplified.

Abstract: Disclosed is a method of forming a capacitor of a semiconductor device which can secure a desired leakage current characteristic while securing a desired charging capacitance. The inventive method of forming a capacitor of a semiconductor device comprises steps of: forming a bottom electrode on a semiconductor substrate with a storage node contact so that the bottom electrode is connected with the storage node contact; plasma-nitrifying the bottom electrode to form a first nitrification film on the surface of the bottom electrode; forming a LaTbO dielectric film on the bottom electrode including the first nitrification film; plasma-nitrifying the LaTbO dielectric film to form a second nitrification film on the surface of the LaTbO dielectric film; and forming a top electrode on the LaTbO dielectric film including the second nitrification film.

Abstract: The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on a substrate. A patterned masking layer is formed over the metal. The patterned masking layer comprises openings therethrough to an outer surface of the metal. Individual of the openings are received over individual of the capacitor storage node locations. A pit is formed in the metal outer surface within individual of the openings. After forming the pits, the metal is anodically oxidized through the openings effective to form a single metal oxide-lined channel in individual of the openings over the individual capacitor storage nodes. Individual capacitor electrodes are formed within the channels in electrical connection with the individual capacitor storage node locations. At least some of the metal oxide is removed from the substrate, and the individual capacitor electrodes are incorporated into a plurality of capacitors.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having first and second main surfaces. The substrate has a heavily doped region of a first conductivity at the second main surface and has a lightly doped region of the first conductivity at the first main surface. The method includes providing trenches and mesas in the substrate, implanting, at an angle, a dopant of the first conductivity into a sidewall of a mesa and implanting, at an angle, a dopant of a second conductivity into the mesa at another sidewall. The method includes oxidizing the sidewalls and bottoms of each trench and tops of the mesas to create a top oxide layer, etching back the top oxide layer to expose a portion of the mesa, depositing an oxide layer to cover the etched back top layer and mesa and planarizing the top surface of the device.

Abstract: A method is provided for forming a non-volatile memory device. The method includes forming a stacked structure including a tunnel oxide layer, a floating gate, a thin oxide layer, and a control gate on a semiconductor substrate. Etching is used to define the sidewalls of the stacked structure. Dopants are implanted into exposed areas of the substrate to form source and drain regions within the substrate adjacent to the stacked structure. A liner dielectric layer is formed on the sidewalls of the stacked structure to patch the etching damage. Thereafter, a nitride barrier layer is formed on the liner dielectric layer, and an oxide spacer is formed on the nitride barrier layer. The nitride barrier layer can trap negative charge and thus act as a relatively high barrier at the tunneling oxide edge. Therefore, the threshold voltage difference between the initial erase of the memory device and the erase after many cycles is reduced.

Abstract: A method of manufacturing a microelectronic device including forming a memory cell having a floating gate located over a substrate, a dielectric layer over the floating gate, and a control gate located over a portion of the dielectric layer, wherein a portion of the dielectric layer is laterally disposed from the control gate. A protective layer is formed over the control gate and the dielectric layer. A mask having an opaque portion over the dielectric layer portion and an opening over the control gate is provided, and the protective layer is patterned employing the mask.

Abstract: A method for fabricating a power MOSFET, comprising an epitaxial layer, a gate dielectric layer and a gate layer formed on a substrate, the gate dielectric layer and the gate layer defined to form a gate structure, a stacked mask and the surface of the epitaxial layer partially exposed between the gate structure and the stacked mask, a well region formed in the epitaxial layer and partially under the gate structure and the stacked mask, a source region is formed in the well region between the gate structure and the stacked mask, a patterned dielectric layer exposing the top of the stacked mask formed over the substrate, the stacked mask removed to form a contact opening exposing the surface of the well region partially and a body region formed in the well region under the contact opening.

Abstract: A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at the bottom of the trench whilst the nitride liner 50 protects the sidewalls 28 from oxidation. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.

Abstract: The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance.

Abstract: A method for forming a trench in a semiconductor device is disclosed. An example method forms a pad oxide film and a silicon nitride film on a semiconductor substrate, selectively etches the silicon nitride film and the pad oxide film on a region to be formed with a trench, and implants oxygen ions into the semiconductor substrate in the region to be formed with the trench. The example method also forms an oxide in the semiconductor substrate by reacting the oxygen ions with the semiconductor substrate through a thermal diffusion of the oxygen ions, forms the trench by etching the semiconductor substrate and the oxide on the region to be formed with the trench using the silicon nitride film as a mask, forms a liner oxide film on an inner wall of the trench using a thermal diffusion process, and forms an insulation film on the liner oxide film such that the trench is filled.

Abstract: A semiconductor device capable of preventing a bridge generation during performing an etching process to form a plurality of gate structures on a substrate divided into an active region and a field region and an electrical short between a contact plug and the individual gate structure in the field region and a method for fabricating the same are provided. The semiconductor device includes: a substrate provided with an active region and a field region; a field oxide layer formed in the field region in such a way that the field oxide layer is recessed to be lower than a surface of the substrate disposed in the active region; and a plurality of gate structures formed on the field oxide layer and the substrate in the active region.

Abstract: There is provided a field effect transistor which is suitable for a power amplifier application or the like, and have a double recess structure with superior repeatability. A film thickness of an AlGaAs layer can determine a depth of a second step of a recess uniquely by using the AlGaAs layer and an InGaP layer with a higher etching selection ratio, a double recess structure can be formed with desirable repeatability, and a high withstand voltage device suitable for a power amplifier application or the like is achieved by making both side surfaces of a gate electrode into the AlGaAs layer.

Abstract: Atomic layer epitaxy (ALE) is applied to the fabrication of new forms of rare-earth oxides, rare-earth nitrides and rare-earth phosphides. Further, ternary compounds composed of binary (rare-earth oxides, rare-earth nitrides and rare-earth phosphides) mixed with silicon and or germanium to form compound semiconductors of the formula RE-(O, N, P)—(Si,Ge) are also disclosed, where RE=at least one selection from group of rare-earth metals, O=oxygen, N=nitrogen, P=phosphorus, Si=silicon and Ge=germanium. The presented ALE growth technique and material system can be applied to silicon electronics, opto-electronic, magneto-electronics and magneto-optics devices.

Abstract: An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses 20 and 22 in the mesa 14. The size of recesses 20 and 22 can be used to tune the value of the electrical resistance between contacts 16 and 18.

Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

Abstract: The present invention is related to methods of processing a semiconductor device. A plasma vapor deposition process is used to fill a trench with an oxide layer, wherein sharp corners are formed by the oxide layer. A pre-planarization sputtering process is performed to reduce the oxide layer corner sharpness. A planarization process is performed using polishing.

Abstract: A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semiconductor substrate having the contact hole, changing characteristics of a portion of the barrier layer on the insulating layer and the portion of the barrier layer in the contact hold such that the characteristics between the barrier layer on the insulating layer and the barrier layer in the contact hole differ, depositing a tungsten layer for forming the tungsten contact plug, on the barrier layer, and removing the tungsten layer from the upper portion of the insulating layer to planarize the semiconductor device.

Abstract: A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor body (1308). Then, surfaces of the trench region are nitrided (1310) via a nitridation process. An oxidation process is performed that combines with the nitrided surfaces (1312) to form a nitrogen containing liner. Subsequently, the trench region is filled with dielectric material (1316) and then planarized (1318) to remove excess dielectric fill material.

Abstract: The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.

Abstract: In order to achieve an isolation trench formation process according to the present invention in which the structure of a silicon nitride film liner can be easily controlled and to allow both of reduction of the device feature length and reduction in stress occurring in an isolation trench, the silicon nitride film liner is first deposited on the inner wall of the trench formed on a silicon substrate. The upper surface of a first embedded insulator film for filling the inside of the trench is recessed downward so as to expose an upper end portion of the silicon nitride film liner. Next, the exposed portion of the silicon nitride film liner is converted into non-silicon-nitride type insulator film, such as a silicon oxide film. A second embedded insulator film is then deposited on the upper portion of the first embedded insulator film, and the deposited surface is then planarized.

Abstract: A dielectric film containing atomic layer deposited HfSiON and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. The HfSiON layer thickness is controlled by repeating for a number of cycles a sequence including pulsing a hafnium containing precursor into a reaction chamber, pulsing an oxygen containing precursor into the reaction chamber, pulsing a silicon containing precursor into the reaction chamber, and pulsing a nitrogen containing precursor until a desired thickness is formed. Dielectric films containing atomic layer deposited HfSiON are thermodynamically stable such that the HfSiON will have minimal reactions with a silicon substrate or other structures during processing.

Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.

Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.

Abstract: A method for cutting a semiconductor device is provided. The device includes a first semiconductor layer, an insulation layer, and a second semiconductor layer. The method includes the steps of: forming a semiconductor part in the first semiconductor layer; irradiating a laser beam on a surface of the first semiconductor layer; and cutting the device into a semiconductor chip by using the laser beam. The laser beam is reflected at an interface so that a first reflected beam is generated, and the laser beam is reflected at another interface so that a second reflected beam is generated. The insulation film has a thickness, which is determined to weaken the first and second reflected beams each other.