Abstract: There is provided a technique for effectively removing a metallic element for promoting crystallization in a semiconductor film with a crystalline structure after the semiconductor film is obtained using the metallic element, to reduce a variation between elements. In a step of forming a gettering site, a plasma CVD method is used and a film formation is conducted using raw gas including monosilane, noble gas, and nitrogen to obtain a semiconductor film which includes the noble gas element at a high concentration, specifically, a concentration of 1×1020/cm3 to 1×1021/cm3 and has an amorphous structure, typically, an amorphous silicon film.

Abstract: Provided is a method for manufacturing a semiconductor device capable of preventing a solution from penetrating a lower layer by forming a poly silicon layer stacked of the films having the different grain boundary structures at border, wherein the solution is used in the subsequent strip and cleaning process.

Abstract: Zinc-oxide nanostructures are formed by forming a pattern on a surface of a substrate. A catalyst metal, such as nickel, is formed on the surface of the substrate. Growth of at least one zinc oxide nanostructure is induced on the catalyst metal substantially over the pattern on the surface of the substrate based on a vapor-liquid-solid technique. In one exemplary embodiment, inducing the growth of at least one zinc-oxide nanostructure induces growth of each zinc-oxide nanostructure substantially over a patterned polysilicon layer. In another exemplary embodiment, when growth of at least one zinc-oxide nanostructure is induced, each zinc-oxide nanostructure grows substantially over an etched silicon substrate layer.

Abstract: An impurity is ion-implanted with a silicon nitride film formed on a silicon substrate as a mask film to form a source/drain layer of a MOS transistor. Heat treatment for activating the impurity is done as it is without removing the silicon nitride film to thereby produce heat treatment-based stress between the silicon nitride film and the silicon substrate.

Abstract: A semiconductor system having a pn transition and a method for manufacturing a semiconductor system are disclosed. The semiconductor system is designed in the form of a chip having an edge region, the semiconductor system includes a first layer of a first conductivity type and a second layer of a second conductivity type, which is of opposite polarity to the first conductivity type. The first layer has an edge region and a center region, the pn transition being provided between the first layer and the second layer. The second layer is more weakly doped in its edge region than in its center region, and the boundary surface of the pn transition at the edge region is non-parallel to the main chip plane.

Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small atoms into an nMOS semiconductor substrate (130) to a depth (132) no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer (400) over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (700).

Abstract: A method of forming a predetermined pattern by disposing a functional liquid on a substrate, the method includes the steps of forming banks on the substrate, and disposing the functional liquid on a region divided by the banks, wherein a width of the region is partially formed so as to be large.

Abstract: A flash memory device includes a floating gate formed with a byproduct, such as a polymer, generated in an etching process. The flash memory device is configured to minimize the unstableness often caused by a floating gate that includes direct contact between polymer and polysilicon. Formation of the floating gate includes forming a tunneling oxide layer, a conductive layer and an insulating layer on a semiconductor substrate. Portions of the insulating layer are removed using a photoresist pattern defining a floating gate area as a mask. Thermal oxide layers are formed on a surface of the conductive layer from which the insulating layer was removed. Polymer materials are included on sides of the respective photoresist pattern and insulating layer. A floating gate is formed by selectively removing portions of the thermal oxide layer and the conductive layer using the photoresist and the polymer materials as a mask.

Abstract: Disclosed herein are a junction where electrical interconnects on a semiconductor substrate intersect and a method of manufacturing a junction where electrical interconnects on a semiconductor substrate intersect is disclosed. In one embodiment, the junction includes a portion of at least one current providing electrical interconnect having a length parallel to a longitudinal axis thereof and configured to provide a flow of electrical current. In addition, the junction includes a portion of at least one current receiving electrical interconnect having a length parallel to a longitudinal axis thereof and configured to intersect with the at least one current providing interconnect at the junction in order to receive the flow of electrical current from the at least one current providing interconnect.

Abstract: A series of improved processes and methods to manufacture solder bumps on the wafer which shrink the space among solder bumps and reduce the cost of manufacturing. A design method and a relevant manufacturing process are introduced to form an organic material or metal material layer, which is called a Bump-Reflow-Control Layer. The pad patterns can be defined by this method. A mechanical part is designed with a hermetic cover to improve the photoresist process. The series of photolithography process including the designing method of related photolithography mask is introduced to achieve the high quality and thick photoresist.

Abstract: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a coating on the interconnect elements of the microfeature workpiece, producing a layer over the surface of the microfeature workpiece after forming the coating, and removing the coating from at least a portion of the individual interconnect elements. The coating has a surface tension less than a surface tension of the interconnect elements to reduce the extent to which the material in the layer wicks up the interconnect elements and produces a fillet at the base of the individual interconnect elements.

Abstract: According to an aspect of the invention, there is provided a method for fabricating a semiconductor device. The method may include forming at least one interconnection layer having a low dielectric constant insulating film and an interconnection buried in the low dielectric constant insulating film, forming a trench or a hole extending in the interconnection layer, performing heat treatment for the interconnection layer having the trench or the hole, and burying a material in the trench or the hole.

Abstract: Circuit edits may be performed through the back side of an integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the back side. An insulating layer is not deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, a conductor is deposited over the circuit edit connection targets from the back side of the integrated circuit to couple together the circuit edit connection targets.

Abstract: A barrier layer structure includes a first dielectric layer forming on a conductive layer and having a via being formed in the first dielectric layer, wherein the via in the first dielectric layer is connected to the conductive layer. A first metal layer is steppedly covered on the first dielectric layer. A layer of metallized materials is steppedly covered on the first metal layer, but the layer of metallized materials does not cover the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. A second metal layer is steppedly covered on the layer of metallized materials, and the second metal layer is covered the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. The barrier layer structure will have lower resistivity in the bottom via of the first dielectric layer and it is capable of preventing copper atoms from diffusing into the dielectric layer.

Abstract: Methods for fabricating an interlayer dielectric layer of a semiconductor device are disclosed. An illustrated method comprises forming a metallic interconnect on a substrate; depositing an SRO layer on the metallic interconnect while the substrate is located in a chamber; and forming an FSG layer on the SRO layer without removing the substrate from the chamber.

Abstract: A semiconductor device includes a semiconductor substrate having electronic elements produced therein, and an insulating underlayer formed thereon, and a multi-layered wiring arrangement constructed on the insulating underlayer semiconductor substrate. The multi-layered wiring arrangement includes a first insulating interlayer structure formed on the insulating underlayer, a second insulating interlayer structure, and a third insulating interlayer structure formed on the first insulating interlayer structure. Each of the first, second and third insulating interlayer structures includes a low-k insulating layer, and has a reinforcing element formed therein. The second insulating interlayer structure has a joint plug formed therein. The reinforcing elements of the first and third insulating interlayer structures are connected to each other through the joint plug.

Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.

Abstract: In a method for manufacturing a semiconductor device, an insulating film having pores is formed on a substrate, and an opening is formed in the insulating film. Thereafter, a material gas supplying Si or C is supplied to the insulating film. Thereby, deficient elements, such as Si or C, are supplied to the insulating film. Thereafter, the opening, including a barrier metal, is filled with a conductive member to form a wiring structure.

Abstract: A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.

Abstract: An interconnect structure in back end of line (BEOL) applications comprising a tunable etch resistant anti-reflective (TERA) coating is described. The TERA coating can, for example, be incorporated within a single damascene structure, or a dual damascene structure. The TERA coating can serve as part of a lithographic mask for forming the interconnect structure, or it may serve as a hard mask, a chemical mechanical polishing (CMP) stop layer, or a sacrificial layer during CMP.

Abstract: A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a second layer of dielectric material adjacent the layer of silicon nitride.

Abstract: Methods and structures are provided for conformal lining of dual damascene structures in semiconductor devices that contain porous or low k dielectrics. Features, such as trenches and contact vias are formed in the dielectrics. The features are subjected to low-power plasma predeposition treatment to irregularities on the porous surfaces and/or reactively form an permeation barrier before a diffusion barrier material is deposited on the feature. The diffusion barrier may, for example, be deposited by CVD using metalorganic vapor reagents. The feature is then filled with copper metal and further processed to complete a dual damascene interconnect. The plasma predeposition treatment advantageously reduces the amount of permeation of the metalorganic reagent into the interlayer dielectric.

Abstract: A method for forming a contact hole, a method for manufacturing a circuit board and a method for manufacturing an electro-optical device that increase the reliability of electrical coupling via a conductive part and prevent wire-breaking due to projections when forming a contact hole in an interlayer film by using a needle, and burying a conductive material in the contact hole is provided.

Abstract: A method for forming vias which pass through a semiconductor wafer substrate assembly such as a semiconductor die or wafer allows two different types of connections to be formed during a single formation process. One connection passes through the wafer without being electrically coupled to the wafer, while the other connection electrically connects to a conductive pad. To connect to a pad, a larger opening is etched into an overlying dielectric layer, while to pass through a pad without connection, a narrower opening is etched into the overlying dielectric layer. An inventive structure resulting from the method is also described.

Abstract: Disclosed is a method for fabricating a semiconductor device with protected conductive structures. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask insulation layer formed on the conductive layer; forming a first insulation layer on the conductive structures; forming a plurality of plugs contacted to the substrate disposed between the conductive structures by passing through the first insulation layer and having a predetermined height corresponding to a height between the conductive layer and a top of the hard mask insulation layer; forming an attack barrier layer covering top and sidewalls of the hard mask insulation layer; forming a second insulation layer on the attack barrier layer; and selectively etching the second insulation layer to form a contact hole exposing at least one of the plugs.

Abstract: One embodiment of the present invention is a method for making copper or a copper alloy interconnects, which method includes: (a) forming a patterned insulating layer over a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening; (b) depositing a barrier layer over the patterned insulating layer including over the field and inside surfaces of the at least one opening, the barrier layer consists of a refractory metal or an alloy of a refractory metal; (c) physical vapor depositing a substantially non-conformal seed layer consisting of copper or a copper alloy over the barrier layer, wherein said substantially non-conformal seed layer is thicker than about 500 ? over the field; (d) chemical vapor depositing a substantially conformal seed layer consisting of copper or a copper alloy over the substantially non-conformal seed layer; and (e) filling the at least one opening by electroplating a metallic layer consisting of copper or a copper alloy ov

Abstract: Disclosed is a method for detecting an end-point of a CMP process of a semiconductor device. More specifically, when all polishing processes are performed using a nitride film as a polishing barrier film, a buffer layer including nitrogen is formed on the nitride film and a polishing process is performed. Then, the concentration of NO from ammonia gas generated from the buffer layer is detected so that the nitride film may be polished to a desired target without damage of the nitride film. As a result, an end-point can be set.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: A method for patterning a magnetic memory cell junction is provided herein, which includes etching exposed portions of a stack of layers to a level spaced above a tunneling barrier layer of the stack of layers. In addition, the method may include implanting dopants into exposed portions of the stack of layers. For example, the method may include oxidizing and/or nitriding the exposed portions of the stack of layers. In some embodiments, the steps of etching and implanting dopants may form an upper portion of the magnetic cell junction. Alternatively, the method may include alternating the steps of etching and implanting dopants throughout the thickness of the exposed portions of the stack of layers. In either case, the stack of layers may include a magnetic layer which includes a material adapted to prevent the introduction of dopants underlying the tunneling barrier layer during the step of implanting.

Abstract: Methods and compositions are provided for planarizing substrate surfaces with low dishing. Aspects of the invention provide methods of using compositions comprising an abrasive selected from the group consisting of alumina and ceria and a surfactant for chemical mechanical planarization of substrates to remove polysilicon.

Abstract: A method by which a silicon wafer is prevented from increasing boron concentration near the surface and difference in the boron concentration does not arise between the surface of the annealed wafer and the silicon bulk to eliminate boron contamination in the silicon wafer caused by an annealing treatment is provided. The method includes, when annealing a silicon wafer having a surface on which a native oxide film has formed and boron of environmental origin or from chemical treatment prior to annealing has deposited, steps of carrying out temperature heat-up in a mixed gas atmosphere having a mixing ratio of hydrogen gas to inert gas of 5% to 100% so as to remove the boron-containing native oxide film, followed by annealing in an inert gas atmosphere.

Abstract: Precision in an etching process is to be improved. A detecting unit 404 detects a variation of plasma emission intensity at a plurality of wavelengths (an emission band having an intensity peak in the proximity of 358 nm and an emission band having an intensity peak in the proximity of 387 nm) during a dry etching process being performed on either of a nitrogen-containing film formed on a semiconductor substrate or a non-nitrogen film provided in direct contact with the nitrogen-containing film in an etching apparatus 402. An arithmetic processing unit 406 performs calculation based on detected variation. A control unit 410 determines an endpoint of the dry etching process in consideration of the calculation result.

Abstract: A method for removing polymer as an etching residue is described. A substrate with polymer as an etching residue thereon is provided, and a hydrogen-containing plasma is used to treat the substrate. A wet clean step is then performed to remove the polymer from the substrate. The treatment using hydrogen-containing plasma can change the chemical property of the polymer, so that the polymer can be removed more easily in the subsequent wet clean step.

Abstract: The invention relates to a process for patterning dielectric layers. A photoresist layer is applied to the dielectric layer and patterned. Then, the pattern which has been predetermined by the resist mask is transferred to the dielectric layer. The incineration of the resist mask is carried out a temperature of 50° C. to 200° C., with the oxygen plasma being generated from a gas which has an oxygen content of 40 to 60% by volume. During a subsequent step of cleaning the patterned dielectric layer using dilute hydrofluoric acid, the trenches which have been introduced into the dielectric layer are widened to a significantly lesser extent than after incineration under the conditions which have previously been customary.

Abstract: A method of depositing a gate dielectric layer for a thin film transistor is provided. The gate dielectric layer is deposited using a plasma enhanced deposition with a gas mixture comprising a silicon and chlorine containing compound.

Abstract: A preferred embodiment of the invention provides a method of spin coating a liquid, such as a resist, onto a surface of a substrate. An embodiment of the invention comprises dispensing a liquid onto the surface; spinning the substrate at a first rotational velocity at least until the liquid forms a substantially uniform film on the surface of the substrate; and spinning the substrate at a second rotational velocity in an opposite direction at least until the liquid reforms a substantially uniform film on the surface of the substrate. Other embodiments include a first rotational acceleration for accelerating the substrate to the first rotational velocity, and a second rotational acceleration for accelerating the substrate to the second rotational velocity. Preferably, the second rotational acceleration is much larger than the first rotational acceleration. Still other embodiments include repeating the first velocity, second velocity sequence one or more times.

Abstract: A process for passivating polysilicon and a process for fabricating a polysilicon thin film transistor. A polysilicon layer is formed. Next, high-pressure annealing is performed using a fluorine-containing gas, a chlorine-containing gas, an oxygen-containing gas, a nitrogen-containing gas, or mixtures thereof to passivate the polysilicon layer.

Abstract: With evacuation of an interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to a substrate surface.

Abstract: The present invention provides non-woven laminate that is not subjected to final consolidation by a binder and the production thereof. The laminate includes at least one non-woven mat containing glass staple fibers pre-consolidated with a resin, and at least one non-woven layer of synthetic fibers. The synthetic non-woven layers and the pre-consolidated non-woven mat of glass fibers are bounded together by needling such that a portion of the fibers of the upper synthetic non-woven layer passes through the non-woven mat of glass fibers possibly through the underlying synthetic non-woven layer. The synthetic fibers are heat shrunken and the laminate is binder free.

Abstract: The present invention relates to glass, glass-ceramic materials, lamp reflectors and processes for making them. The glass material has a composition, by weight of the total composition, comprising 56–67% SiO2; 9–22% Al2O3; 3.4–3.8% Li2O; 1.8–2.6% ZnO; 1.5–2.5% MgO; 3.3–5% TiO2; 0–2.5% ZrO2; 1.5–3% B2O3; 0–6% P2O5; 0–0.6% F; less than 500 ppm Fe; and components resulting from effective amount of at least one refining agent. The glass-ceramic material of the present invention contains ?-spodumene solid solution as the predominant crystalline phase, and can be obtained by proper thermal treatment of the glass-ceramic material.

Abstract: A homogeneous bulky porous ceramic material is provided, the average pore diameter D50 of which is less than 4 ?m and the closed porosity of which is less than 2 ?m, and having a bubble point that matches the pore diameter measured on the material. A hollow fiber based on the material and a module employing such fibers together with a paste constituting a precursor for the material and including a pore-forming agent are also provided.

Abstract: A unified process which couples a unique in situ catalyst regeneration process with a continuous reactive distillation under pressure for the alkylation of light aromatic hydrocarbons such as benzene with C2–C30 olefins using a solid acid alkylation catalyst supported in the reflux zone of a distillation column. Periodic regeneration of the catalyst is carried out with a countercurrent injection of a C4–C16 paraffin below the benzene rectification zone at the top of the column, but above the catalyst zone while the aromatic hydrocarbon reaction feedstock is injected continuously at a point above a rectification zone at the base of the column where the aromatic compound is separated from the paraffin and by-products washed from the catalyst. The use of the C4–C16 paraffin with the aromatic at a mole fraction in the range of 40 to 90% enables a regeneration temperature of about 175–250° C. to be achieved and maintained by adjusting the column pressure and aromatic reflux rate.

Abstract: A method for oxidizing carbon adsorbable organic compounds in a controlled manner within a bed of activated carbon. The bed of activated carbon is exposed to a source of molecular oxygen, such as air, and is controlled within a temperature range whereby the molecular oxygen is slowly oxidizing the activated carbon. Under this controlled set of conditions, the activated carbon will oxidize organic compounds present within the bed of activated carbon. This technique has widespread versatility for the controlled destruction of organic vapors and liquids by activated carbon and applications for the regeneration of spent activated carbons containing previously adsorbed organic compounds.

Abstract: A catalyst in which X-ray diffraction intensity ratio of the crystal lattice plane spacing d-value of 0.196±0.002 nm to the crystal lattice plane spacing d-value of 0.386±0.008 nm is in a range from 7:100 to 35:100 and a process for making the catalyst to contact with ethylbenzene containing xylenes in the presence of hydrogen.

Abstract: The present invention relates to a catalyst component suitable for olefin (co)polymerization, which comprises an aluminoxane supported on magnesium halide and contains more than 5% by weight of aluminum. The catalyst component according to the present invention is obtained by contacting an aluminoxane compound and a magnesium compound in the presence of a multifunctional organic compound. The catalyst comprising said component and metallocene shows good activity and consumes less amount of aluminoxane in the process of olefin polymerization. The polymer prepared by using said catalyst has an improved particle morphology and a narrow particle distribution.

Abstract: A process for preparing a mixed catalyst compound used in the polymerization of polyolefins to produce bimodal polyethylenes is disclosed. In an embodiment, a process of preparing the mixed catalyst system includes: mixing a first catalyst and an activator in a first liquid medium to form a first mixture, combining a support with the first mixture to form a first support slurry, drying the first support slurry in an extent sufficient to provide a dried supported first catalyst, mixing the dried supported first catalyst in a second liquid medium to form a second support slurry, and combining one or more additional catalysts with the second support slurry to provide the mixed catalyst compound.

Abstract: Catalyst compositions comprising a first metallocene compound, a second metallocene compound, a third metallocene compound, a chemically-treated solid oxide, and an organoaluminum compound are provided. Methods for preparing and using the catalyst and polyolefins are also provided. The compositions and methods disclosed herein provide ethylene polymers having decreased haze while minimizing impact on other properties, such as dart impact.

Abstract: A catalytic composition, including a cationic metal-pair complex, is disclosed, along with a method for its preparation. A method for the polymerization of ethylenically unsaturated monomers using the catalytic composition, and the addition polymers produced thereby are also disclosed.

Abstract: A catalyst for the oligomerization of olefins, especially ethylene contains: at least one nickel complex e.g. Li2 Ni X2 that results from bringing into contact a nickel salt e.g. a nickel carboxylate with a bidentate chelating ligand containing a nitrogen-containing heterocyclic compound with an alcohol e.g. Ha-C(OH)RR?; and at least one hydrocarbylaluminum compound from tris(hydrocarbyl)aluminum compounds, chlorinated or brominated hydrocarbylaluminum compounds or at least one aluminoxane.

Abstract: In an embodiment, a method of hydrogenating a highly unsaturated hydrocarbon to an unsaturated hydrocarbon includes contacting the highly unsaturated hydrocarbon with a catalyst in the presence of hydrogen. The catalyst comprises palladium and an inorganic support having a surface area of from about 4.5 to about 20 m2/g, or alternatively 5 to 14.5 m2/g. The inorganic support may comprise ?-alumina treated with a fluoride source. The palladium may be primarily disposed near the surface of the support. In addition, the catalyst may comprise silver distributed throughout the support. In another embodiment, a method of making the foregoing selective hydrogenation catalyst includes contacting a fluorine-containing compound with an inorganic support, heating the support, and adding palladium to the inorganic support. After adding palladium to the support, the support can then be heated again, followed by adding silver to and then heating the support once again.