Abstract: A signal presence detection device has a first reference voltage generation device in the form of a first voltage divider, a second reference voltage generation device in the form of a second voltage divider and a third reference voltage generation device in the form of a third voltage divider. The detection device also has a signal conditioning device such as a hysteretic amplifier with an output that is coupled to the first and second voltage dividers. A comparison device is coupled to all three voltage dividers to compare a voltage of the first voltage divider to a voltage of the third voltage divider and to compare a voltage of the second voltage divider to the voltage of the third voltage divider. The comparison device is coupled at two outputs thereof to two respective inputs of an XOR device. The XOR device receives respective signals from the first and second outputs of the comparison device and produces a signal presence output that serves to indicate whether an incoming signal is present or absent.

Abstract: There is disclosed a circuit and a process for detecting peak-to-peak voltage. The circuit comprises a first comparator having an output coupled to a first capacitor, a non-inverting input for receiving a high frequency AC waveform, and an inverting input, a second comparator having an output coupled to a second capacitor, and a first second input, an operational amplifier having a non-inverting input coupled to the inverting input of the first comparator, and an inverting input coupled to the first input. The process comprises charging- a first capacitor when a high frequency AC waveform voltage is greater than a buffered voltage of the first capacitor, charging a second capacitor when an inverted buffered voltage of the second capacitor is greater than the high frequency AC waveform voltage, and outputting a voltage based on the buffered voltage of the first capacitor and the inverted buffered voltage of the second capacitor.

Abstract: A method and an apparatus for switching on a voltage supply of a voltage domain of a semiconductor circuit is disclosed. A voltage supply is connected to a supply voltage of the semiconductor circuit by means of a switchable element. The switchable element is activated in such a way that, for switching on the voltage supply of the voltage domain, a current through the switchable element rises progressively with at least one intermediate value, in particular stepwise manner.

Abstract: A standby circuit generates a control signal for configuring a main power supply circuit to operate in one of a full operation mode and a standby operation mode. The standby circuit includes a standby power supply block and a control block. The standby power supply block produces a power supply signal for powering the control block. The control block receives a mode control signal that indicates the operation mode and automatically generates a coupling signal based on the mode indicated by the mode control signal. The control signal is based on the coupling signal.

Abstract: In television type systems having separate data, audio and video portions, it is desirable to maintain or correct the relative timing of the signals by delaying the lesser delayed one(s) to match the delay of the more delayed one(s). A method and apparatus are described where events leading to significant changes in delay of a first, more delayed signal are recognized before that delay change appears in that first delayed signal, for one example by recognizing delay changes made before or at the input to, or within the system. Information about the significant delay change is communicated to a second signal's compensating delay before hand to enable faster and more accurate tracking of the second signal's delay to the first signal's delay.

Abstract: An output driver circuit comprising a plurality of multiple gate field effect transistors (MGFETs) that provides an output signal is provided. Each output driver circuit may have a first MGFET gate for receiving a drive signal, a second MGFET gate for biasing purposes, and a current electrode for providing an output signal. Some embodiments provide a drive signal and a bias signal to the same MGFET device. Alternate embodiments provide the same drive signal (or alternately the same bias signal) to both gates of the same MGFET device. Some embodiments may provide an output driver circuit having variable output impedance. Predriver circuitry and/or bias control circuitry may optionally be used.

Abstract: An apparatus for providing a signal to a transmission medium. A first switching stage is connected in series between a source voltage and a transmission medium, and a second switching stage connected in series between the transmission medium and a reference line. The first and second switching stages each comprise at least one p channel transistor in parallel with at least one n channel transistor. The first and second switching stages are preferably configured to substantially symmetrically drive the transmission medium at a frequency of at least 4 gigahertz (GHz). The stages are further preferably characterized as variable resistance stages with lower resistance at the rails as compared to the midpoint of the input signal. Additional sets of stages can be provided to facilitate multiple outputs.

Abstract: An apparatus for generating a power-up signal of a semiconductor memory apparatus includes a first power-up signal generator that generates a first power-up signal to be activated on the basis of a comparison between a power supply voltage level supplied to the semiconductor memory apparatus and a first set voltage level, and a second power-up signal generator that generates a second power-up signal to be activated with a predetermined delay time on the basis of a comparison between the power supply voltage level and a second set voltage level.

Abstract: A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.

Abstract: A delay locked loop (DLL) circuit in which situations of lock to multiple periods of a reference signal is determined by a lock detector using dummy delay elements and a duty cycle correction circuit (DCC). The lock detector, the dummy delay elements and the delay control circuit are used in a path parallel to the delay elements which generate the desired delayed signals having different delays in relation to the reference signal. Due to the use of the parallel path, the throughput performance of the DLL circuit is not impeded. In an embodiment, separate charge pumps are used by a phase comparator and the lock detector used in the parallel path.

Abstract: A Delayed Locked Loop Circuit of DLL comprises a buffer that receives a power-down signal and an inverted signal of a first clock signal; first and second delay lines an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively; a replica delay unit, a phase comparator for comparing a phase difference between the output signal of the second buffer and the output signal of the replica delay unit; and a delay line controller for controlling delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator. The DLL circuit is configured such that the first and second buffers are disabled when the power-down mode entry notifying signal corresponding to a power-down mode is provided.

Abstract: The invention relates to an electronic component that can be operated by means of an alternating voltage. Said component includes at least one input, at least one output and a pair of electronic sub-components with an identical function. The input(s) of the electronic component is/are coupled to a respective input of the electronic sub-components with an identical function and the output(s) of the electronic component is/are coupled to a respective output of said electronic sub-components. In addition, the electronic component is configured in such a way that at least one output only one output signal of the first sub-component of the pair of functionally identical electronic components can be picked up during a first half-wave of an alternating voltage, whereas only one output signal of the second sub-component of the pair of functionally identical electronic can be picked up during the second half-wave of the alternating voltage.

Abstract: A system for and method of reducing power consumed by an electronic system is disclosed. The system includes an energy controller for controlling power to one or more functional modules or regions on the electronic system. Each of the functional modules has an activity detector for determining whether any activity is occurring on the respective functional module. When an activity detector detects no activity on a functional module, the energy controller automatically reduces power or clock gating to that functional module after completing a computation. When activity is detected on the functional module, the energy controller automatically restores power to the functional module. Preferably, multiple functional modules, each having an activity detector, and the energy controller are contained on a single semiconductor die.

Abstract: A circuit for transmitting logic signals across a high voltage barrier has a logic signal buffer with true and complement state differential outputs. A binary flip-flop with set and reset inputs is further provided. A first coupling capacitor is coupled to the true buffer output and to the set input of the binary flip-flop. A second coupling capacitor is coupled to the complement buffer output and to the reset input of the binary flip-flop circuit.

Abstract: A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is operable to be received at said data input, is clocked through said at least one latch and passes to said data output along said forward data path; at least one of said at least one latch comprises a retention latch operable to retain a signal value during said sleep mode, said retention latch not being located on said forward data path; and a bidirectional tristateable device, said bidirectional tristateable device being arranged between said forward data path and said retention latch and being operable to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein in response to receipt of a second sleep signal, said se

Abstract: The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the other electrode of the capacitor, an accurate operation can be obtained without being influenced by variations in the TFT characteristics even when the amplitude of an input signal is small relatively to the width of a power supply voltage.

Abstract: The present invention relates to a clock control circuit, it can reduce power consumption in data input and output operations, and a semiconductor memory device including the clock control circuit, and data input and output operation method of the semiconductor memory device. The clock control circuit according to the present invention can generate an input or output control clock signal only when data are substantially input or output in the data input and output operations. It is thus possible to save unnecessary power consumption.

Abstract: An internal resistor device of an integrated circuit chip, including a MOS transistor and a logic unit, is provided. The MOS transistor has a drain coupled to an input pin of the integrated circuit chip and a source coupled to a predetermined voltage. The logic unit receives a control signal from the input pin and a driving signal, and then executes a logic operation of the driving and the control signals. The result of the logic operation is provided to the gate of the MOS transistor. When the input pin is floating, the internal resistor device provides a predetermined fixed voltage to internal circuits chip. When the input voltage level is inverse to the predetermined fixed voltage, static current is almost not consumed.

Abstract: According to the present invention, a semiconductor device is provided wherein a stepdown-type DC-DC converter includes a first off detection circuit, a second off detection circuit, a capacitor, a capacitor, a diode, inverters, an inductor, a first level shift circuit, a second level shift circuit, a third level shift circuit, a 2-input NAND circuit, a 2-input NAND circuit, a high-side N-channel power MOS transistor and a low-side N-channel power MOS transistor. The first off detection circuit and the second off detection circuit reduce fall times of the gates of the N-channel power MOS transistors, thereby reducing dead time.

Abstract: In many high voltage circuits, it often needs to shift the logic voltage level to keep the circuit normal operation. In the class-D amplifier circuitry, it needs to shift the voltage level of pulse width modulation (PWM) signal to control the connecting of different power switches. In other applications, such as a driver to drive amplifier of an audio device, it also needs a level shift circuit to maintain the circuitry in normal voltage operation. Therefore, this invention is to provide a novel level shift circuit with high performance, low cost and low power dissipation characteristics.

Abstract: A level shifter circuit includes first and second reference potential supply lines; first and second output potential supply circuits each connected between the first and second reference potential supply lines; first and second input lines; first and second output lines; and a stress test circuit which functions to, during normal operation, when the first input signal and the second input signal are input to the first input line and the second input line, output the first output signal and the second output signal having respectively different potentials for the first output line and the second output line, and during the stress test, when the first input signal and the second input signal are input to the first input line and the second input line, output signals having identical potentials from the first output line and the second output line.

Abstract: In a high-frequency switch circuit having a booster circuit and a voltage switch circuit for ON/OFF control of the booster circuit, the voltage switch circuit has a means for gradually dropping the gate input voltage and the drain/source input voltage of a series of FETs over a voltage drop time of 10 ?sec or more at the time of switching from a boosted voltage to a non-boosted voltage.

Abstract: An antifuse programming, protection, and sensing device incorporates a control circuit to program and protect an antifuse. The antifuse, which is initially constructed as a low conductivity path, is programmable to a high conductivity path by application of an elevated voltage across terminals of the antifuse. Application of 0 volts to the VDD node of a conduction control portion of the antifuse programming, protection, and sensing device allows an elevated voltage for programming to be applied to the antifuse. Upon application of a nominal working voltage to the VDD node of the conduction control circuitry, the antifuse and an adjoining sense amplifier circuit are protected from overvoltage and tampering. The sense amplifier supplies a sense current to the antifuse, measures a voltage at an input to the antifuse, and determines a programmed state if a measured voltage level is low.

Abstract: A semiconductor integrated circuit includes: a elevated voltage detector that outputs a elevated voltage pump enable signal; a elevated voltage pump that is driven by the elevated voltage pump enable signal to pump the elevated voltage; a substrate bias voltage detector that outputs a substrate bias voltage control signal when at least one of the elevated voltage pump enable signal and a substrate bias voltage pump enable signal for driving a substrate bias voltage pump changes to an active state; and the substrate bias voltage pump that is driven by the substrate bias voltage control signal to pump the substrate bias voltage.

Abstract: A semiconductor apparatus (100) comprises a low potential reference circuit region (1) and a high potential reference circuit region (2), and the high potential reference circuit region (2) is surrounded by a high withstand voltage separating region (3). By a trench (4) formed in the outer periphery of the high withstand voltage separating region (3), the low potential reference circuit region (1) and high potential reference circuit region (2) are separated from each other. Further, the trench (4) is filled up with an insulating material, and insulates the low potential reference circuit region (1) and high potential reference circuit region (2). The high withstand voltage separating region (3) is partitioned by the trench (4), high withstand voltage NMOS (5) or high withstand voltage PMOS (6) is provided in the partitioned position.

Abstract: Semiconductor integrated circuit apparatus and electronic apparatus having a leakage current detection circuit where arbitrarily set leakage current detection ratio does not depend on power supply voltage, temperature, or manufacturing variations, and where leakage current detection is straightforward. Semiconductor integrated circuit apparatus extracts a stable potential from the center of two NchMIS transistors, amplifies drain current of an NchMOS transistor taking this potential as a gate potential to a current value of an arbitrary ratio using current mirror circuit, makes this current value flow through NchMOS transistor with the gate and drain connected, and applies drain potential of this NchMOS transistor to the gate of leakage current detection NchMOS transistor.

Abstract: A semiconductor device includes: a pump circuit that boosts an output node connected to a memory cell array; an oscillator that outputs a clock to the pump circuit; and a detection circuit that outputs an actuating signal to the oscillator. In this semiconductor device, the actuating signal actuates the oscillator when the voltage of the output node of the pump circuit is lower than a first reference voltage, and the actuating signal stops the oscillator when the voltage of the output node is higher than a second reference voltage. In accordance with the present invention, when the voltage of the output node of the pump circuit is higher than the target voltage, the oscillator is stopped, and so is the pump circuit. Thus, unnecessary charge flow to the ground can be prevented, and the power consumption of the booster circuit can be reduced.

Abstract: A semiconductor circuit includes a voltage pump, which has a series circuit of capacitors. The voltage pump furthermore has first switching elements, which are coupled between, in each case, two capacitors of the series circuit, and are coupled to capacitor electrodes of the capacitors by coupling lines. Connection lines are coupled to a respective connecting line and, in each case, have a second switching element, which enables an interruption of the respective connection line. It is possible for the second switching elements to be jointly switched to a conducting state when all the first switching elements are switched to a non-conducting state, as a result of which each capacitor is electrically charged individually by in each case two connection lines.

Abstract: An integrated semiconductor circuit has a potential detector for detecting a potential boosted by a high voltage generator. One terminal of a first capacitor is connected to a potential detection terminal via a first switching device, the other terminal thereof being connected to a reference potential terminal. A terminal of a second capacitor is connected, via a second switching device, to a first node at which the first switching device and the first capacitor are connected, the other terminal thereof being connected to the reference potential terminal. A third switch is connected between a second node at which the second switching device and the second capacitor are connected and the reference potential terminal. A clock generator generates clock signals to simultaneously and periodically turn on the first and the third switching devices whereas turn on the second switch periodically in an opposite timing for the first and the third switching devices.

Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Abstract: A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.

Abstract: Provided is a power amplifier of a low-power consumption system that has linearity at a peak output power while increasing efficiency in a most frequently used range, and thereby enables a battery to last longer. The power amplifier includes an input impedance matcher for impedance-matching a signal input from the outside; a high-power amplifier and a low-power amplifier for amplifying the signal having passed through the input impedance matcher; an amplification controller controlling the high-power amplifier and low-power amplifier according to the power level of the input signal; an output impedance matcher for impedance-matching the signal amplified by the high-power amplifier and low-power amplifier; and a dynamic voltage supplier for supplying the low-power amplifier with a variable driving voltage. With the constitution set forth above, linearity at peak output power is maintained, and efficiency increases in the most frequently used range, thereby enabling the battery of a handheld to last longer.

Abstract: A slew rate enhancement circuit for adjusting a gamma curve including a main output stage, a monitoring stage, an assistant output stage and a gamma curve generating device is provided. The main output stage also generates a first push signal and a first pull signal according to the input voltage, and thereafter the second push signal and second pull signal are level shifted by the monitoring stage. A second push signal and second pull signal will turn on or turn off the assistant output stage to decided whether to output an assistant current to the load or not. The gamma curve generating device receives the assistant current to outputs at least one gamma reference voltage for adjusting a gamma curve. Specially, the improved compact circuit does not increase static operating current for the original operational amplifier and occupy a small chip area.

Abstract: Class D amplifiers are used for their high efficiency, but they have some undesirable characteristics, one of these being the residual switching frequency ripple. Embodiments of the present invention comprise methods and apparatuses for reducing the switching frequency ripple using a technique known herein as ripple steering. A secondary output is added to the amplifier for the purpose of steering the switching ripple away from the main output thus substantially relieving the main output from a major artifact of prior art Class D amplifiers.

Abstract: A differential amplifier is disclosed. The differential amplifier includes a first load element coupled between a first voltage and a first node. A second load element is coupled between the first voltage and a second node. A current source is coupled between a second voltage and a third node. A first input element is coupled between the first node and the third node and receives an input signal so as to adjust a voltage level of the first node. A second input element is coupled between the second node and the third node and receives a reference voltage signal so as to adjust a voltage level of the second node. A third input element is coupled between the second node and the third node and receives the input signal so as to adjust the voltage level of the second node.

Abstract: In a non-destructive test instrument, there is provided a time variable gain (TVG) amplifier wherein the gain of the amplifier is dynamically changed to optimize the amplitude of a flaw echo signal. The TVG digital memory for a given TVG curve specifies and controls not only the start gain value, and the end game value, but the gain rate of change slope as well to generate TVG curve line segments.

Abstract: The present invention relates to an electronic circuit for amplification of bipolar symmetric current signals. The electronic circuit has a pair of complimentary current mirrors. Depending on the polarity of the bipolar current signal one or the current mirrors is active while the other current mirror is in an off state. This way adding a biasing current to the input signal is avoided which substantially reduces noise.

Abstract: Disclosed is a differential amplifier of a multi-level output type comprising a load circuit including a diode-connected first transistor with a source thereof connected to a power supply and a second transistor with a source thereof connected to the power supply and connected to a gate of the first transistor through a capacitor, a differential pair including a third transistor and a fourth transistor with sources thereof connected in common and drains thereof connected to drains of the first and second transistors, respectively, a current source for supplying a current to the differential pair, a first switch connected between a gate of the second transistor and a drain of the fourth transistor, an amplifier with an input thereof connected to a drain of the second transistor and an output thereof connected to an output terminal, a second switch connected between a gate of the fourth transistor and a first input terminal, a third switch connected between the gate of the fourth transistor and a third input te

Abstract: A transmitting arrangement includes a matching circuit, a reference circuit and a comparator. The output of the matching circuit can be coupled to an antenna and comprises an adjustable impedance. The reference circuit is connected to an input of the matching circuit and comprises a reference impedance. Inputs of the comparator are coupled to the matching circuit and the reference circuit and its output is coupled to the adjustable impedance via a control input of the matching circuit.

Abstract: A phase locked loop circuit (PLL) has a reference terminal for receiving a reference signal and an output terminal for providing an output signal.

Abstract: Ultrasound medical devices, systems and methods are described.

Abstract: A synthesizer that has a phase detector 8 and a charge pump circuit 9 for injecting an electric charge, or pulling it out that corresponded to a frequency difference of an input, a low-pass filter 11 for converting this electric charge into a voltage, a voltage control oscillator (VCO) 13 for changing an output frequency for this input voltage, a divider 14 for dividing the frequency of the input, and a voltage holding circuit 10 for holding the input voltage for a plurality of output frequencies of the VCO. A holding voltage of the voltage holding circuit 10 is switched with a switch 12, and the frequency of an output clock signal 3 is switched.

Abstract: The invention is directed to a resonant circuit having a frequency-determining element which has at least one switchable frequency-changing element connected in parallel therewith. The frequency-changing element has two series-connected transistors whose control connections are connected to a node that receives a fixed potential. First connections of the two series-connected transistors are connected to one another and also to a control input for a control signal for switching the frequency-changing element of the resonant circuit. The invention keeps the control voltage for the two transistors at a higher potential than the threshold voltage for the transistors. This reduces a parasitic capacitance in the two transistors during operation.

Abstract: Methods of enabling or disabling ultrasound vibration devices of ultrasound medical devices are described.

Abstract: The present invention provides a tuning fork shaped oscillator, an angular velocity sensor element, and an angular velocity sensor with improved breaking strength with respect to CI and drive power, CI stability, and frequency stability. The present invention relates to a tuning fork shaped crystal oscillator of a configuration wherein two tuning fork shaped crystal elements that have been formed by wet etching during the process of forming the external shape of a tuning fork, in such a manner that the longitudinal direction of the tuning fork is aligned on the Y-axis of the crystalline axes (XYZ) and also the lateral direction thereof is aligned on the X-axis, are bonded together with the ±X-axis directions thereof oriented in opposite directions; and the right side surface of each of the two tuning fork shaped crystal elements is the +X face of the crystal when the two tuning fork shaped crystal elements are viewed in an upright attitude.

Abstract: A method to control a frequency oscillator, as a crystal oscillator, and to form an oscillating circuit in order to produce a frequency oscillator improved to its qualities, in which the frequency of reference oscillator (1) is changed by means of frequency multiplier (2) into output frequency. As frequency oscillator a low frequency oscillator (1) is used, the control of which output frequency (5) is carried out adjusting the low frequency oscillator (1) by means of control arrangement (4).

Abstract: An amplifier arrangement for ultra-wideband, UWB, applications and. a method to amplify a UWB signal are presented. A transistor, whose control input forms an input of the arrangement, is connected to a resonant circuit having a controllable resonator frequency. At the resonator circuit, an output of the arrangement is formed. The resonant circuit includes a frequency determining inductance whose value is controllable. By doing this, it is possible to preselect different frequency bands, while achieving the same gain characteristics in each band.

Abstract: In order to make it possible to direct sufficient microwave energy at a target with an electronic device which is to be interfered with or to be destroyed, the beams (7) from at least two antenna arrays (10) are focused on an effective area (8) in the vicinity of that target, preferably from a vehicle (3) which is equipped with these arrays (10). For effective super-imposition of the emitted microwave energy (7) in the emission direction of in each case one of the arrays (10), the use of an arc for discharging the capacitance (43) of the resonator via its spark gap (13) is observed, and is recorded quasi-continuously optoelectronically. The electrode separation of the spark gap (13) or the fluid pressure of the dielectric in the vicinity of the spark gap (13) is then varied by control elements such that all of the spark gaps (13) in an array (10) ignite virtually at the same time, so that their discharge current pulses which lead to the emission of the microwave energy (7) start virtually in phase.

Abstract: A voltage-controlled oscillator, associated temperature detecting unit, and integrated circuit is disclosed. The voltage-controlled oscillator comprises a frequency drift compensation unit, which compensates for a frequency drift of the oscillator and supplies a compensation signal to a component having a voltage-controlled capacitance.

Abstract: A voltage-controlled oscillator operates stably over a narrow variation range of a control voltage, including a variable capacitance circuit 12 controllable by voltage, an inductor circuit 11 having inductors, a negative resistance circuit 13, and a capacitance control circuit 14 that outputs a correction voltage. An oscillator circuit is constituted by the variable capacitance circuit 12, the inductor circuit 11, and the negative resistance circuit 13 connected in parallel. The capacitance control circuit 14 controls to correct the capacitance of the variable capacitance circuit 12 with the correction voltage outputted in response to a temperature fluctuation and/or power supply voltage fluctuation in the oscillator circuit.