Abstract: It is an object to provide a liquid composition for forming a thin film, with which a ferroelectric thin film having excellent characteristics can be prepared even by baking at a low temperature, and a process for producing a ferroelectric thin film using it. The above object is achieved by use of a liquid composition for forming a ferroelectric thin film, characterized in that in a liquid medium, ferroelectric oxide particles being plate or needle crystals, which are represented by the formula ABO3 (wherein A is at least one member selected from the group consisting of Ba2+, Sr2+, Ca2+, Pb2+, La3+, K+ and Na+, and B is at least one member selected from the group consisting of Ti4+, Zr4+, Nb5+, Ta5+ and Fe3+) and have a Perovskite structure and which have an average primary particle size of at most 100 nm and an aspect ratio of at least 2, are dispersed, and a soluble metal compound which forms a ferroelectric oxide by heating, is dissolved.

Abstract: A low-k dielectric layer having a composition of silicon, oxygen and carbon is removed from a wafer. The low-k dielectric layer is removed by exposing a surface of the low-k dielectric layer to an oxygen-containing gas to oxidized the surface. The oxidized surface is immersed in an etching solution having HF and H2SO4 to etch the low-k dielectric layer. The etched surface is exposed to at least one of (i) an etching solution having H2SO4 and H2O2, and (ii) an RF or microwave energized oxygen-containing gas, to remove the low-k dielectric layer from the wafer.

Abstract: An edge protection process for semiconductor device fabrication includes forming a protective layer on the circumferential edge region of a semiconductor substrate. The semiconductor substrate is placed in a plasma atmosphere and trench structures, such as deep trenches and shallow trench isolation structures are etched in the substrate. The protective layer substantially prevents the etching of the circumferential edge region, such that the formation of black silicon is substantially minimized during the etching process.

Abstract: A metal oxide sensor is provided on a semiconductor substrate to provide on-chip sensing of gases. The sensor may include a metal layer that may have pores formed by lithography to be of a certain width. The top metal layer may be oxidized resulting in a narrowing of the pores. Another metal layer may be formed over the oxidized layer and electrical contacts may be formed on the metal layer. The contacts may be coupled to a monitoring system that receives electrical signals indicative of gases sensed by the metal oxide sensor.

Abstract: Method and apparatus for efficiently analyzing visual defects of an integrated circuit wafer in the manufacturing process thereof by utilizing an asymmetric visual defect review methodology that can effectively extract high yield-killing defects out of numerous reported defects within the limited capacity and manpower available for review. Roughly described, the method comprises inspecting the semiconductor wafer, thereby obtaining the defect location and defect size, sampling the defects asymmetrically by determining asymmetrical defect review ratios, and thereby reviewing the defects asymmetrically. Also described is a method of asymmetrically sampling visual defects that can effectively extract out high yield-killing defects from a mass of defects by determining asymmetric defect review ratios, and a system for use in sampling visual defects asymmetrically.

Abstract: In a side plate (52) of a retainer (50), a jig insertion groove (70) is cut at an upper end portion of its front edge. A releasing jig (J) is insertable into a gap between the bottom surface of the jig insertion groove (70) and a vertical front edge of a recessed surface (27) of a female housing (20). If the releasing jig (J) is rotated so as to be pried, the retainer (50) is pushed back diagonally downward along a guide groove (60) and reaches a temporary retaining position.

Abstract: The present invention provides a method for placing a dopant in a substrate and a method for manufacturing an integrated circuit. The method for placing a dopant in a substrate, among other steps, includes providing a substrate (340) and implanting a dopant within the substrate (340) using an implant (370), the implant (370) moving at varying speeds across the substrate (340) to provide different concentrations of the dopant within the substrate (340).

Abstract: Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering method is applied to the substrate with the material layers for critical dimension (CD) or profile measurement.

Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.

Abstract: An optical membrane device and method for making such a device are described. This membrane is notable in that it comprises an optically curved surface. In some embodiments, this curved optical surface is optically concave and coated, for example, with a highly reflecting (HR) coating to create a curved mirror. In other embodiments, the optical surface is optically convex and coated with, preferably, an antireflective (AR) coating to function as a refractive or diffractive lens.

Abstract: Disclosed is an acid etching resistance material comprising a compound having a repeating unit represented by the following general formula (1): (in the general formula (1), R1 is a hydrogen atom or methyl group; R3 is a cyclic group selected from an alicyclic group and an aromatic group; R4 is a polar group; R2 is a group represented by the following general formula (2); and j is 0 or 1): (in the general formula (2), R5 is a hydrogen atom or methyl group).

Abstract: A method for fabricating a chip-scale package includes securing a device substrate that carries at least two adjacent semiconductor devices to a sacrificial substrate. The sacrificial substrate may include conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. The device substrate is then severed along each street and the newly formed peripheral edge of each semiconductor device coated with dielectric material. If the sacrificial substrate includes conductive elements, they may be exposed between adjacent semiconductor devices and subsequently serve as lower sections of contacts. Peripheral sections of contacts are formed on the peripheral edge. Upper sections of the contacts may also be formed over the active surfaces of the semiconductor devices. Once the contacts are formed, the sacrificial substrate is substantially removed from the back sides of the semiconductor devices.

Abstract: A white-light emitting device comprising a first PRS-LED and a second PRS-LED. The first PRS-LED has a primary light source to emit blue light and a secondary light source to emit red light responsive to the blue light; and the second PRS-LED has a primary light source to emit green light and a secondary light source for emitting red light responsive to the green light. Each of the primary light sources is made from an InGaN layer disposed between a p-type GaN layer and an n-type GaN layer. The secondary light sources are made from AlGaInP. The primary light source and the secondary light source can be disposed on opposite sides of a sapphire substrate. Alternatively, the second light source is disposed on the n-type GaN layer of the primary light source. The second light sources may comprise micro-rods of AlGaInP of same or different compositions.

Abstract: A semiconductor component having a light-emitting semiconductor layer or a light-emitting semiconductor element, two contact locations and a vertically or horizontally patterned carrier substrate, and a method for producing a semiconductor component are disclosed for the purpose of reducing or compensating for the thermal stresses in the component. The thermal stresses arise as a result of temperature changes during processing and during operation and on account of the different expansion coefficients of the semiconductor and carrier substrate. The carrier substrate is patterned in such a way that the thermal stresses are reduced or compensated for sufficiently to ensure that the component does not fail.

Abstract: A method of manufacturing a ridge type semiconductor light emitting device includes: a process of epitaxially growing a multi-layered semiconductor layer having at least a first conductive type cladding layer, an active layer, a second conductive type first cladding layer, an etching stop layer, and a second conductive type second cladding layer on a substrate; a process of forming a ridge groove for forming a ridge; and a process of forming a current-flow barrier layer in the ridge groove. The process of forming ridge grooves has first and second anisotropic etching processes of performing anisotropic etching, an etching-mask forming process, and an isotropic etching process of performing anisotropic etching.

Abstract: A micromachined device made of semiconductor material is formed by: a semiconductor body; an intermediate layer set on top of the semiconductor body; and a substrate, set on top of the intermediate layer. A cavity extends in the intermediate layer and is delimited laterally by bottom fixed regions, at the top by the substrate, and at the bottom by the semiconductor body. The bottom fixed regions form fixed electrodes, which extend in the intermediate layer towards the inside of the cavity. An oscillating element is formed in the substrate above the cavity and is separated from top fixed regions through trenches, which extend throughout the thickness of the substrate. The oscillating element is formed by an oscillating platform set above the cavity, and by mobile electrodes, which extend towards the top fixed regions in a staggered way with respect to the fixed electrodes. The fixed electrodes and mobile electrodes are thus comb-fingered in plan view but formed on different levels.

Abstract: The invention is directed to improving of a yield and reliability of a BGA type semiconductor device having ball-shaped conductive terminals. A semiconductor wafer having warped portions is supported by a plurality of pins, being spaced from a heated stage. The semiconductor wafer is heated as a whole by uniformly irradiating thermal radiation thereto by using IR heaters disposed on an upper part of the semiconductor wafer and side heaters facing to lateral surfaces of the semiconductor wafer. This enables uniform reflowing of the conductive terminals provided on the semiconductor wafer, and makes each of the conductive terminals form a uniform shape.

Abstract: A method for manufacturing a printed circuit board includes: forming inner circuit patterns in an insulating material in multi-layers, forming a plurality of through holes at certain portions of the insulating material, and forming an outer circuit pattern which is electrically connected to the inner circuit pattern, at an inner circumferential surface of the through hole and the surface of the insulating material, and a terminal portion; forming a first photo solder resist layer at an entire surface of the insulating material and an entire surface of the outer circuit pattern, and exposing the terminal portion by removing a specific portion of the first photo solder resist layer; abrading the surface of the first photo solder resist layer; printing a second photo solder resist layer at the surface of the first photo solder resist layer, and exposing the terminal portion to the outside by removing a specific portion of the second photo solder resist layer; and forming a pad portion by plating the surface of t

Abstract: A method of packaging includes placing a restrainer on a package during processing. The method includes clipping the restrainer in place and then exposing the package to high temperatures. After processing the restrainer is removed. An alternative process attaches a component die to a substrate having a cavity in a first surface. The process may then include dispensing and curing an underfill material in the cavity, and attaching a lid to the first surface of the substrate.

Abstract: A semiconductor chip with conductive wiring that is routed to the edge of the substrate from the chip's backside. A plurality of such semiconductor chips are stacked and electrically connected using a wiring element that is a circuit board or conductive adhesive strips. The wiring element connects the conductive wiring of each semiconductor chip along the sides of the chips to the package substrate. A method of manufacturing the semiconductor chip includes batch manufacturing a plurality of die on a wafer with an active surface on which a plurality bonding pads are formed, and a backside which is the rear side of the active surface; forming a circuit groove on the backside; applying conductive wiring on the circuit groove using a conductive material; and separating the wafer into a plurality of semiconductor chips.

Abstract: A method of forming a semiconductor package including placing a semiconductor chip in cavities of a semiconductor chip carrier substrate.

Abstract: A first reconstituted wafer is formed, followed by a first redistribution layer. In parallel, a second reconstituted wafer is formed. The second reconstituted wafer is diced along a gap such that individualized embedded chips are formed having tilted sidewalls defining an angle of more than 90 degrees with respect to the active surface of the reconstituted wafer. The embedded chips are placed with the backside on an active surface of the first reconstituted wafer on the first redistribution layer. Afterwards, a second redistribution layer is formed on the active surface of the embedded chips and tilted sidewalls wherein the second redistribution layer connects contact pads of the second chips with the first redistribution layer.

Abstract: A method and apparatus to stencil interposers on a wafer of dies is described. In one embodiment, an interposer stenciling apparatus includes an interposer forming stencil configured to deposit interposer material onto a backside of a wafer of dies in a predetermined formation. In another embodiment, another interposer forming stencil is configured to form additional interposer layers on existing interposers to support dies thereon having different size configurations.

Abstract: A layer of electrically insulating material is applied to a substrate and a component located thereon, in such a way that said layer follows the surface contours.

Abstract: The electrical contacts, such as ball grid array (BGA) solder balls, of an integrated circuit (IC) are coupled to printed circuit board (PCB) bonding pads that include vias. According to an embodiment of an electronic assembly, the vias are formed off-center, so as to inhibit bridging between adjacent solder balls during a solder reflow operation by minimizing the effect of solder ball ballooning resulting from outgassing of a thermally expansive substance, such as a volatile organic compound (VOC) from the via channels. The bonding pads are separated into two groups, each having vias offset in a different direction, so that asymmetric surface tension forces in the molten solder during a solder reflow operation do not cause the IC to slide to one side. A substrate, an electronic assembly, an electronic system, and fabrication methods are also described.

Abstract: A method of manufacturing a package substrate includes forming a first copper plated layer on a base substrate having through holes and inner surfaces of the through hole, coating a first resist over the first copper plated layer, partially removing the first resist, forming a second copper plated layer on the first copper plated layer, stripping the first resist, coating a second resist over the resultant structure, and removing the second resist from regions where wire bonding pads and solder ball pads are to be formed, removing exposed portions of the first copper plated layer, forming the wire bonding pads and the solder ball pads, removing the second resist, removing exposed portions of the first copper plated layer, and coating a solder resist over all surfaces of the resultant structure, and removing portions of the solder resist respectively covering the wire bonding pads and the solder ball pads.

Abstract: Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.

Abstract: An electronic device, in which a flat plate semiconductor and dumets connected to surface electrodes on the front and back surfaces of the semiconductor and to lead wires are encapsulated in a glass tube.

Abstract: A thin film transistor with multiple gates using an MILC process which is capable of materializing multiple gates without increasing dimensions and a method thereof. The thin film transistor has a semiconductor layer which is formed on a insulating substrate in a zigzag shape; and a gate electrode which is equipped with one or more slots intersecting with the semiconductor layer, the semiconductor layer includes two or more body parts intersecting with the gate electrode; and one or more connection parts connecting each neighboring body part, wherein a part overlapping the semiconductor layer in the gate electrode acts as a multiple gate, and MILC surfaces are formed at a part which does not intersect with the gate electrode in the semiconductor layer.

Abstract: A semiconductor device comprises a support layer made of semiconductor, a diffusion layer formed by implanting impurities in a surface layer of the support layer, a buried insulating layer provided on the diffusion layer, an island-like active layer provided on the buried insulating layer, a channel region formed in the active layer, source and drain regions formed in the active layer, sandwiching the channel region, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film and on side surfaces of the island-like active layer, and insulated and isolated from the channel, source, and drain regions, and an electrode connected to the active layer.

Abstract: Methods are provided for producing SiGe-on-insulator structures and for forming strain-relaxed SiGe layers on silicon while minimizing defects. Amorphous SiGe layers are deposited by CVD from trisilane and GeH4. The amorphous SiGe layers are recrystallized over silicon by melt or solid phase epitaxy (SPE) processes. The melt processes preferably also cause diffusion of germanium to dilute the overall germanium content and essentially consume the silicon overlying the insulator. The SPE process can be conducted with or without diffusion of germanium into the underlying silicon, and so is applicable to SOI as well as conventional semiconductor substrates.

Abstract: A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.

Abstract: Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

Abstract: A process for forming a strained semiconductor layer. The process includes implanting ions into a semiconductor layer prior to performing a condensation process on the layer. The ions assist in diffusion of atoms (e.g. germanium) in the semiconductor layer and to increase the relaxation of the semiconductor layer. After the condensation process, the layer can be used as a template layer for forming a strained semiconductor layer.

Abstract: In crystallizing an amorphous silicon film by illuminating it with linear pulse laser beams having a normal-distribution type beam profile or a similar beam profile, the linear pulse laser beams are applied in an overlapped manner. There can be obtained effects similar to those as obtained by a method in which the laser illumination power is gradually increased and then decreased in a step-like manner in plural scans.

Abstract: A semiconductor device is provided comprising several device components formed in the same substrate, such as a P-substrate having an offset Nch transistor including N-type source and drain each formed in a P-well spatially separated from one another, and the drain surrounded by a low concentration N-type diffusion layer; an offset Pch transistor including P-type source and drain each formed in an N-well spatially separated from one another, and the drain surrounded by a low concentration P-type diffusion layer; a triple well including a deep N-well, and a P-type IP well formed therein; a normal N-well for forming a Pch MOS transistor; and a normal P-well for forming an Nch MOS transistor; in which simultaneously formed are the low concentration N-type diffusion layer, N-well and normal N-well; the P-well and normal P-well; and the low concentration P-type diffusion layer and IP well.

Abstract: A semiconductor device is proposed which includes: a semiconductor substrate of a first conductivity type; a channel region formed at a surface of the semiconductor substrate; source and drain regions of a second conductivity type formed at both sides of the channel region in the semiconductor substrate; an insulating layer covering the channel region; and a gate electrode formed on the insulating layer, the insulating layer containing impurity atoms in such a manner that a concentration thereof is non-uniformly distributed along a surface parallel to the semiconductor substrate.

Abstract: A method for making a semiconductor device is described. That method comprises forming a polysilicon layer on a dielectric layer, which is formed on a substrate. The polysilicon layer is etched to generate a patterned polysilicon layer with an upper surface that is wider than its lower surface. The method may be applied, when using a replacement gate process to make transistors that have metal gate electrodes.

Abstract: A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The carbon-doped silicon formed in the recesses resides close to the transistor channel and serves to provide a tensile stress to the channel, thereby facilitating improved carrier mobility in NMOS type transistor devices.

Abstract: A method of fabricating local interconnect lines (LILs) of a CMOS structures, the method comprising etching an inter layer dielectric (ILD) material of the CMOS structure at a first temperature to form one or more holes and one or more slits; and etching an etch-stop material of the CMOS structure at a second temperature lower than the first temperature to extend the holes and slits to devices of the CMOS structure.

Abstract: Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

Abstract: Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.

Abstract: A technique for producing a thin gate oxide having a relatively high dielectric constant. Embodiments relate to the structure and development of a gate oxide having a thickness of less than 1 nm, having a dielectric constant greater than twenty, and being substantially free of undesired electrical characteristics caused by exposure of the gate oxide to high complementary metal-oxide-semiconductor processing temperatures.

Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.

Abstract: The invention includes a method of forming spaced conductive regions. A construction is formed which includes a first electrically conductive material over a semiconductor substrate. The construction also includes openings extending through the first electrically conductive material and into the semiconductor substrate. A second electrically conductive material is formed within the openings and over the first electrically conductive material and is in electrical contact with the first electrically conductive material. The second electrically conductive material is subjected to anodic dissolution while the first electrically conductive material is electrically connected to a power source.

Abstract: Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some semiconductor devices on a wafer to have a single polysilicon wafer and other devices to have a dual polysilicon layer. In one embodiment, the semiconductor devices are utilized to form a memory device wherein the storage capacitors and transistors located in the cell region are formed with a dual polysilicon layer and devices in the periphery region are formed with a single polysilicon layer.

Abstract: To fabricate a vertical transistor, a trench is provided, the side wall of which is formed by a semiconductor substrate in single crystal form and the base of which is formed by a polycrystalline semiconductor substrate. A transition region is arranged between the side wall and the base. A semiconductor layer is deposited so that an epitaxial semiconductor layer grows on the side wall and a semiconductor layer grows on the base, with a space remaining between these layers. The semiconductor layers are covered with a thin dielectric, which partially limits a flow of current, and the space is filled. During a subsequent heat treatment, dopants diffuse out of the conductive material into the epitaxial semiconductor layer, where they form a doping region. The thin dielectric limits the diffusion of the dopants into the semiconductor substrate and prevents the propagation of crystal lattice defects into the epitaxial semiconductor layer.

Abstract: A method of fabricating a split gate flash memory device by which stringer generation is prevented. The method includes forming a dielectric layer on an active area of a semiconductor substrate, forming a first gate covered with a cap layer on the dielectric layer, and forming an insulating layer on a sidewall of the first gate. The method also includes forming a dummy spacer over the sidewall of the first gate, the first gate including the cap layer and the insulating layer, and removing the dielectric layer failing to be covered with the dummy spacer and the dummy spacer to form an exposed portion of the substrate. The method further includes forming a gate insulating layer on the exposed portion of the substrate, and forming a second gate overlapping one side of the first gate, wherein a split gate is configured with the first and second gates.

Abstract: A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.

Abstract: A method of forming a memory cell array comprising a plurality of memory cells, each of the memory cells including a trench capacitor and a transistor is disclosed.