Abstract: An EEPROM device manufacturing method is disclosed. The method includes the steps of oxidation, polysilicon deposition, and etching to form first polysilicon layers of a select transistor and a floating gate electrode. The method also includes a second polysilicon deposition step followed by an etching step to form a logic gate electrode and a control gate electrode at the same time. This method prevents damage to the silicon substrate and reduces the number of process steps compared to conventional manufacturing methods.

Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.

Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.

Abstract: A method for forming, by thermal oxidation, a silicon oxide layer on an integrated circuit including three-dimensional silicon patterns, includes implanting a first element according to a first angle with respect to a horizontal direction. The first element is electrically neutral and has a first effect on the growth rate of a thermal oxide on silicon. A second element is implanted according to a second angle with respect to the horizontal direction. The second element is electrically neutral and has a second effect complementary to the first effect on the growth rate of a thermal oxide on silicon. The second angle is distinct from the first angle, and one of the first and second angles is a right angled. The silicon is thermally oxidized.

Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.

Abstract: A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the patterned mask layer has a first line width. The first layer can then be etched to form a first plurality of sloped sidewalls. After removing a portion of the patterned mask so that the patterned mask layer has a second line width less than the first line width, the first layer can be etched again to form a second plurality of sloped sidewalls. The patterned mask layer can then be removed. The first layer can be etched again to form a third plurality of sloped sidewalls. The first plurality of sloped sidewalls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls can form an array of parallel triangular channels.

Abstract: The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.

Abstract: Provided are a doping mask and methods of manufacturing a charge transfer image device and a microelectronic device using the same. The method includes forming a photoresist film on an entire surface of a substrate or sub-substrate having a peripheral circuit region and a pixel region, removing the photoresist film on an upper surface of the substrate intended for the peripheral circuit region and patterning the photoresist film on an upper surface of the substrate intended for the pixel region to form a photoresist pattern having an array of openings with a predetermined pitch, implanting ions at the same concentration level into the entire surface of the substrate using the photoresist pattern as a doping mask, and diffusing the implanted ions by annealing. The pitch is determined so that ions implanted through each opening diffuse toward those implanted through an adjacent one to form wells.

Abstract: A method and structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in the opening. A structure is over the doped high conductivity region selected from a group consisting of a wordline, a gate, a dielectric layer, and a combination thereof.

Abstract: An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain extension region are formed in a semiconductor material using an angled implant. The source extension region extends under the gate structure, whereas the drain extension region is laterally spaced apart from the gate structure. A source region is formed in the semiconductor substrate and a drain region is formed in the semiconductor substrate, where the source and drain regions are laterally spaced apart from the gate structure. A source-side halo region is formed in the semiconductor substrate adjacent the source extension region.

Abstract: Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region of the semiconductor substrate, a gate formed on the gate insulating film, a channel region formed in the semiconductor substrate and overlapping the gate, and LDD regions formed in the semiconductor substrate and at both sides of the gate, centering the gate. In addition, the example transistor includes source and drain regions formed under the LDD regions, offset regions formed in the semiconductor substrate and between the channel region and LDD regions, and gate spacers formed at both sidewalls of the gate.

Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

Abstract: A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (32a, 32b, 32c) to break the channel region of the transistor into parallel sections. The gate electrode (35) extends over the multiple channel regions, and the underlying well (26) and thus the drift region (DFT) of the transistor extends along the full channel width. Channel stop doped regions (33) underlie the field oxide isolation structures (29c), and provide conductive paths for carriers during breakdown. Parasitic bipolar conduction, and damage due to that conduction, is therefore avoided.

Abstract: A method for producing a compound semiconductor wafer used for production of HBT by vapor growth of a sub-collector layer, a collector layer, a base layer and an emitter layer in this turn on a compound semiconductor substrate using MOCVD method wherein the base layer is grown as a p-type compound semiconductor thin film layer containing at least one of Ga, Al and In as a Group III element and As as a Group V element under such growth conditions that the growth rate gives a growth determined by a Group V gas flow rate-feed.

Abstract: A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (9A) on the first dielectric layer, and forming a second dielectric layer (18D) over the first dummy fill layer. A thin film resistor (2) is formed on the second dielectric layer (18D). A first inter-level dielectric layer (21A) is formed on the thin film resistor and the second dielectric layer. A first metal layer (22A) is formed on the first inter-level dielectric layer and electrically contacts a portion of the thin film resistor. Preferably, the first dummy fill layer is formed as a repetitive pattern of sections such that the repetitive pattern is symmetrically aligned with respect to multiple edges of the thin-film resistor (2).

Abstract: Methods of preparing a porous low-k dielectric material on a substrate are provided. The methods involve the use of ultraviolet radiation to react with and remove porogen from a porogen containing precursor film, leaving a porous low-k dielectric matrix. Methods using oxidative conditions and non-oxidative conditions are described. The methods described may be used to remove porogen from porogen-containing precursor films. The porogen may be a hydrocarbon such as a terpene (e.g., alpha-terpinene) or a norbornene (e.g., ENB). The resulting porous low-k dielectric matrix can then be annealed to remove water and remaining silanols capped to protect it from degradation by ambient conditions, which methods will also be described.

Abstract: A semiconductor device structure has trenches of two widths or more. The smallest widths are to maximize density. The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories. These more demanding, wider isolation trenches are lined with a high quality grown oxide as part of the process for achieving the desired result of high quality isolation. For the case of the narrowest trenches, the additional liner causes the aspect ratio, the ratio of the depth of the trench to the width of the trench, to increase. Subsequent deposition of insulating material to fill the trenches with the highest aspect ratios can result in voids that can ultimately result in degraded yields. These voids are avoided by etching at least a portion of the liners of those trenches with the highest aspect ratios to reduce the aspect ratio to acceptable levels.

Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.

Abstract: A method of creating an electrically conducting bonding between a face of a first semiconductor element and a face of a second semiconductor element using heat treatment. The method applies the faces one against the other with the placing between them of at least one layer of a material configured to provide, after heat treatment, an electrically conducting bonding between the two faces. The deposited layers are chosen so that the heat treatment does not induce any reaction product between said material and the semi-conductor elements. Then, a heat treatment is carried out.

Abstract: A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.

Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.

Abstract: When the laser light having the harmonic is used for crystallizing the semiconductor film, there is a problem that the energy conversion efficiency from the fundamental wave to the harmonic is low. And since the laser light converted into the harmonic has lower energy than the fundamental wave, it is difficult to enhance the throughput by enlarging the area of the beam spot. The present invention provides a laser irradiation apparatus emitting the fundamental wave simultaneously with the wavelength not longer than that of the fundamental wave, typically the harmonic converted from the fundamental wave, wherein the laser light emitted from one resonator having the fundamental wave and the wavelength not longer than that of the fundamental wave are irradiated without being separated.

Abstract: A plurality of successive layers are firmly adhered to one another and to a wafer surface and an electrical component or sub-assembly even when the wafer surface is not even and the layers are bent. The wafer surface is initially cleaned by an ion bombardment of an inert gas (e.g. argon) on the wafer surface in an RF discharge at a relatively high gas pressure. The wafer surface is then provided with a microscopic roughness by applying a low power so that the inert gas (e.g. argon) ions do not have sufficient energy to etch the surface. A layer of chromium is then sputter deposited on the wafer surface as by a DC magnetron with an intrinsic tensile stress and low gas entrapment by passing a minimal amount of the inert gas through the magnetron and by applying no RF bias to the wafer. The chromium layer is atomically bonded to the microscopically rough wafer surface.

Abstract: By providing an asymmetric design of a halo region and extension regions of a field effect transistor, the transistor performance may significantly be enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even completely be avoided, wherein a moderately reduced concentration gradient may further enhance the transistor performance.

Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, halogen atoms (120) and transition metal atoms (130) to form a halogen-containing metal layer (140) on a semiconductor substrate (150). The halogen-containing metal layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (400) comprising the metal silicide electrode.

Abstract: A transistor having a gate electrode with a T-shaped cross section is fabricated from a single layer of conductive material using an etching process. A two process etch is performed to form side walls having a notched profile. The notches allow source and drain regions to be implanted in a substrate and thermally processed without creating excessive overlap capacitance with the gate electrode. The reduction of overlap capacitance increases the operating performance of the transistor, including drive current.

Abstract: There are provided a gate dielectric film formed on a semiconductor substrate; a gate electrode including: a first electrode layer formed on the gate dielectric film, a dielectric film having a thickness of 5 ? or more and 100 ? or less, and formed on the first electrode layer, and a second electrode layer formed on the dielectric film; and a source and drain regions formed in the semiconductor substrate at both sides of the gate electrode.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a thin film are described.

Abstract: An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.

Abstract: A method for routing a plurality of signal traces out of a plurality of corresponding bumper pads for implementation of a die on a multi-layer circuit board includes utilizing the plurality of bumper pads positioned in a periphery area of the die; utilizing a plurality of power/ground bumper pads positioned in a center area of the die; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of first-layer traces being routed in a first layer of the multi-layer circuit board; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of second-layer traces being routed in a second layer of the multi-layer circuit board; routing the plurality of first-layer traces straight away from the die; and routing the plurality of second-layer traces with a turn not to be vertically underneath the first-layer traces.

Abstract: A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2?t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)?GD2 for the second copper layer.

Abstract: A first film made of silicon carbide is formed over a substrate. The surface of the first film is exposed to an oxidizing atmosphere to oxidize the surface layer of the first film. The surface of the first film is made in contact with chemical which makes the surface hydrophilic. On the hydrophilic surface of the first film, a second film is formed which is an insulating film made of a low dielectric constant insulating material having a relative dielectric constant of 2.7 or smaller or an insulating film made by a coating method. A sufficient adhesion property is obtained when a film made of low dielectric constant insulating material is formed on an insulating film made of silicon carbide having a small amount of oxygen contents.

Abstract: Disclosed is a method for forming a gate in a semiconductor device. The method includes the steps of: sequentially forming a gate insulation layer and an inter-layer insulation layer on a substrate; patterning the inter-layer insulation layer into a predetermined configuration, thereby forming a patterned inter-layer insulation layer; forming a nitride layer on the patterned inter-layer insulation layer; simultaneously etching the nitride layer and the substrate, thereby obtaining a spacer on sidewalls of the patterned inter-layer insulation layer and a trench having a predetermined depth in the substrate; forming a conductive layer on the trench; and planarizing the conductive layer, thereby forming the gate.

Abstract: An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching process could include CF4 chemistry. The inner edges of the sloped ARC areas reduce the original photo-defined space since the underlying layers are now defined by the sloped edges.

Abstract: A hole is formed in an insulating film containing silicon and carbon. The insulating film has a density or a carbon concentration varying gradually in the direction of the thickness thereof.

Abstract: Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.

Abstract: Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting assemblies. A semiconductor component substrate, such as a semiconductor die or other substrate, has dielectric material disposed on a surface thereof, surrounding but not covering interconnect elements, such as bond pads, on that surface. A second semiconductor component substrate, such as a carrier substrate with interconnect elements such as terminal pads, is adhered to the first semiconductor component substrate, forming a semiconductor package assembly having interconnect voids between the corresponding interconnect elements. A flowable conductive material is then injected into each interconnect void using an injection needle that passes through one of the substrates into the interconnect void, forming a conductive interconnect between the bond pads and terminal pads of the substrates.

Abstract: A method of depositing a metal film on a substrate includes a supercritical preclean step, a supercritical desorb step, and a metal deposition step. Preferably, the preclean step comprises maintaining supercritical carbon dioxide and a chelating agent in contact with the substrate in order to remove an oxide layer from a metal surface of the substrate. More preferably, the preclean step comprises maintaining the supercritical carbon dioxide, the chelating agent, and an acid in contact with the substrate. Alternatively, the preclean step comprises maintaining the supercritical carbon dioxide and an amine in contact with the oxide layer. The desorb step comprises maintaining supercritical carbon dioxide in contact with the substrate in order to remove adsorbed material from the substrate.

Abstract: The invention includes methods of forming metal oxide and/or semimetal oxide. The invention can include formation of at least one metal-and-halogen-containing material and/or at least one semimetal-and-halogen-containing material over a semiconductor substrate surface. The material can be subjected to aminolysis followed by oxidation to convert the material to metal oxide and/or semimetal oxide. The aminolysis and oxidation can be separate ALD steps relative to one another, or can be conducted in a reaction chamber in a common processing step.

Abstract: A method of forming a boride layer for integrated circuit fabrication is disclosed. In one embodiment, the boride layer is formed by chemisorbing monolayers of a boron-containing compound and one refractory metal compound onto a substrate. In an alternate embodiment, the boride layer has a composite structure. The composite boride layer structure comprises two or more refractory metals. The composite boride layer is formed by sequentially chemisorbing monolayers of a boron compound and two or more refractory metal compounds on a substrate.

Abstract: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure.

Abstract: A plasma treatment method which is capable of extending the MTF (mean-time-to-failure) of metal interconnects fabricated on a semiconductor wafer substrate, is disclosed. The invention includes providing a trench typically in a dielectric layer on a substrate; depositing a metal in the trench; and exposing the metal to a nitrogen-based plasma. The plasma-treatment step accelerates grain growth and re-orients the grains in the metal to a closely-packed crystal orientation texture which approaches or approximates the <111> crystal orientation texture of copper.

Abstract: The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A plurality of layers is deposited on said surface wherein a lower layer exhibits a higher polishing rate than an upper layer and wherein the thickness of the plurality of layers exceeds the step height. Afterwards the plurality of layers is chemically mechanically polished such that the lower layer is at least partly removed in the first region. By this method achieves a better planarization. Additionally, smaller top contact openings after a wet clean step are achievable and a deformation of contact openings due to annealing steps is reduced.

Abstract: A chemical supplying apparatus includes first and second mixing tanks for mixing and supplying chemical slurries used in a semiconductor fabrication process. The slurries are alternately provided from the first and second mixing tanks such that the slurry is continuously available to a precessing apparatus for maximum efficiency. While one of the tanks is supplying the slurry, the other tank is cleaned and then used to prepare a new batch of the slurry.

Abstract: Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.

Abstract: The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: forming a gate line on a semiconductor substrate; forming a buffer layer and a spacer nitride film on the entire surface of the substrate including the gate line; selectively etching the buffer layer and the spacer nitride film in such a manner that they remain on both sides of the gate line; performing an ion implantation process using the remaining buffer layer and spacer nitride film as a barrier film to form junction regions in the semiconductor substrate at both sides of the gate line; forming an interlayer insulating film on the entire upper portion of the resulting substrate; selectively removing the interlayer insulating film to form contact holes exposing the upper surface of the junction regions; and forming contact plugs in the contact holes.

Abstract: A method of forming conductive connections for semiconductor devices is provided. An organic low-k dielectric layer is formed over a wafer. A conductive aluminum containing layer is formed over the organic low-k dielectric layer. The wafer is placed in an etch chamber. An etch gas comprising HBr is provided into the etch chamber. A plasma is formed from the etch gas comprising HBr. The plasma from the etch gas comprising HBr is used to selectively etch the conductive aluminum containing layer with respect to the low-k dielectric layer.

Abstract: In a metal film production apparatus, a copper plate member is etched with a Cl2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl2 gas; and the temperatures of the copper plate member and a substrate and a difference between their temperatures are controlled as predetermined, to deposit the Cu component of the precursor on the substrate, thereby forming a film of Cu. In this apparatus, Cl* is formed in an excitation chamber of a passage communicating with the interior of the chamber to flow a Cl2 gas, and the Cl* is supplied into the chamber to withdraw a Cl2 gas from the precursor adsorbed onto the substrate, thereby promoting a Cu film formation reaction. The apparatus has a high film formation speed, can use an inexpensive starting material, and can minimize impurities remaining in the film.

Abstract: A plasma processing method utilizing a plasma processing apparatus having a plasma generating unit, a process chamber including an outer cylinder for withstanding a reduced pressure, and an inner cylinder made of non-magnetic material and being replaceable arranged inside the outer cylinder, a process gas supply unit for supplying gas to the process chamber, a specimen table for holding a specimen and a vacuum pumping unit. A temperature of the inner cylinder is monitored, and a desired inner cylinder temperature which is inputted in advance in response to a processing condition of the specimen is compared with the monitored temperature of the inner cylinder. A temperature of the outer cylinder is controlled in response to a result of the comparison so as to control the inner cylinder temperature to a predetermined value.

Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.