Abstract: A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states.

Abstract: A sampling circuit for compensating the phase difference of a sampling pulse due to a temperature variation to accurately sample input signals is provided. The sampling circuit samples received input signals. The sampling circuit includes a pulse generator for generating a pulse signal according to a timing at which an input signal should be sampled, a step recovery diode for outputting a sampling pulse responsive to the pulse signal, a detector for detecting the value for the input signal according to the sampling pulse, a temperature detecting circuit for detecting the temperature around the step recovery diode and a temperature compensating unit for controlling a timing at which the step recovery diode outputs the sampling pulse based on the temperature detected by the temperature detecting circuit.

Abstract: By flexibly coping with both image sensors of a CCD sensor and a CMOS sensor without providing any external circuit, a signal processing is performed. In a sensor selecting switch provided in an image-sensor signal-processing circuit, first and fourth switches are turned on when the CMOS sensor is connected, and second and third switches are turned on when the CCD sensor is connected. The sensor selecting switch is controlled by a control signal generated in a control circuit, based on sensor selection data which is stored in a register and which is data for selecting the CCD or CMOS sensor. By so doing, even if polarity of an output signal of the image sensor is reversed, a normal signal is inputted to both inputs of the CDS amplifier, whereby it is possible to flexibly cope with both of the CCD and CMOS sensors.

Abstract: A CMOS driver with minimum shoot-through current is disclosed. The potential for shoot-through current may be eliminated or reduced with a break-before-make circuit driving an output stage. The break-before-make circuit may include a first logic element followed by a first inverter and a second logic element followed by a second inverter. The inverters may be cross-coupled to one another and/or the internal transistors may be configured with different strengths. The logic elements may be configured to eliminate or reduce potential shoot-through current paths, and the signal inputs may be controlled within a certain voltage range.

Abstract: In a semiconductor device for controlling switching power supply of this invention, having a switching element and switching operation control circuit, after receiving a current detection signal when switching is turned off, a fixed delay time is applied to the current detection signal by a delay circuit so that switching turn-on control by a transformer reset pulse signal obtained based on a signal from the tertiary windings of the transformer is not accepted within a blanking time corresponding to the delay time. Thus, the switching by the switching element is halted.

Abstract: Measure-controlled delay (MCD) circuits are provided for synchronizing an output clock to an input clock. In response to triggering of a measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic prevents output of the output clock when any of a predetermined one or more of the samples correspond to a particular logic value (i.e., logic “1” or “0”). For example, sample reset logic may prevent an MCD circuit from providing the output clock when a sample taken from the earliest sampling point of the measure delay array corresponds to logic “1.” The MCD circuit may then provide the output clock in response to a subsequent triggering for which a sample taken from the earliest sampling point is logic “0.” Phase error of the output clock is thereby reduced. Clock synchronization circuits with improved response to process, voltage and temperature (PVT) variations are also provided.

Abstract: A reset initialization structure and method is described. A power on reset pulse is utilized to force the state of system reset during intervals of Vcc which otherwise would result in indeterminate reset states. Operation is adaptable to include all DC power systems. The reset initialization structure provides operational protection during power up and power down conditions.

Abstract: The clock generator of this invention saves a buffer memory for the data transfer interface, which has conventionally been required, when using a spectrum spread clock in circuits and devices inside a system. The clock generator can easily be applied as the operational clock in a system, and enhances the performance of the system. In the clock generator, the variable delay circuit controls the phase of the reference clock generated by an oscillator. The delay setting circuit is able to vary the setting of the control voltage to the variable delay circuit at each clock cycle, and modulates the phase of the reference clock. The phase modulation means of the delay setting circuit fluctuates the cycle of the output modulation clock to thereby spread the spectrum.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.

Abstract: A frequency synthesizer and a method for synthesizing a microwave output signal frequency. The synthesizer uses a reference signal having a variable frequency and accumulation in feedback of a phase locked loop for synthesizing a microwave output frequency. The feedback accumulation rate is derived from a first seed word and the variable reference frequency is derived from a second seed word. A spur suppressor having arithmetic frequency conversions reduces the levels of in-band spurious signals of the variable reference frequency signal in order to reduce the spurious signal levels in the output signal.

Abstract: A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g.

Abstract: System and method for even order and odd order nonlinear distortion of a compensating signal that removes substantially all of the nonlinear distortion in one order or in two orders. Two or more diodes are arranged in at least one of an anti-series configuration and an anti-parallel configuration in which a circuit voltage is equal to a selected odd order and/or to a selected even order in current, plus higher order terms that are often negligible. The diodes may be replaced by other selected nonlinear devices.

Abstract: A high-speed front-multiplexed multi-channel LVDS-compatible repeater circuit that limits input leakage current levels in the event one or more input voltages of the circuit exceeds the supply voltage. The LVDS repeater includes a multiplexor having a plurality of differential inputs and at least one differential output. The multiplexor includes a plurality of transmission gates to allow any one of the differential inputs to be routed to any differential output. Each transmission gate includes a first PMOS transistor and an NMOS transistor. The multiplexor further includes first Schottky diodes coupled between Vcc and the back-gate nodes of the first PMOS transistors, and second PMOS transistors coupled as shunts between the gate nodes of the first PMOS transistors and the source nodes of the NMOS transistors.

Abstract: A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

Abstract: A charge pump circuit which uses a constant current from a constant current source for charging or discharging a capacitor and which obtains an output voltage by shifting a power supply voltage using a charged voltage of the charged capacitor. With this structure, a large current can be limited and generation of noise can be prevented.

Abstract: A reverse current is prevented in a charge pump circuit. A complementary pair of clocks CLK and *CLK varies while a first through a fourth charge transfer MOS transistors M11, M12, M13 and M14 are turned off. Then the second charge transfer MOS transistor M12 is turned on to discharge a first pumping capacitor CA and the third charge transfer MOS transistor M13 is turned on to charge a second pumping capacitor CB. Next, the complementary pair of clocks CLK and *CLK varies after the first through the fourth charge transfer MOS transistors M11, M12, M13 and M14 are turned off again. Then the fourth charge transfer MOS transistor M14 is turned on to discharge the second pumping capacitor CB and the first charge transfer MOS transistor M11 is turned on to charge the first pumping capacitor CA.

Abstract: In a basic circuit of a booster circuit, two charging units perform a charging operation and two boosting units perform a boosting operation (discharging operation). One of the charging units is connected to a voltage input and the other is connected to a voltage output. The charging unit that is connected to the voltage input includes three parallel connected MOS transistors Q11, Q12, and Q13, the other charging unit includes a MOS transistor Q4. One of the boosting units is connected to the voltage input and the other is connected to the voltage output. The boosting unit that is connected to the voltage input includes three parallel connected MOS transistors Q31, Q32, and Q33, the other boosting unit includes a MOS transistor Q2. Q11 and Q31 are turned ON immediately after start up, then Q12 and Q32 are turned ON and finally Q13 and Q33 are turned ON.

Abstract: A bias circuit for providing at least first and second bias signals for biasing a cascode current source and/or a cascode current sink includes a resistive element and first, second and third transistors, each transistor having first and second source/drain terminals and a gate terminal. The first source/drain terminal of the first transistor is coupled to the gate terminal, the first bias signal being generated at the first source/drain terminal in response to receiving a first reference current at the first source/drain terminal. A first end of the first resistive element is coupled to the second source/drain terminal of the first transistor. The gate terminal of the second transistor is coupled to the gate terminal of the first transistor, the second bias signal being generated at the first source/drain terminal of the second transistor in response to receiving a second reference current at the first source/drain terminal of the second transistor.

Abstract: The present invention provides a semiconductor integrated circuit device equipped with a negative feedback amplifier circuit or a step-down circuit which realizes stabilization of an output voltage effectively in response to a variation in power supply voltage. A constant current source is used to cause a bias current for setting current consumption to flow in a differential amplifying MOSFET. A capacitor is provided between an external power supply voltage and a predetermined circuit node to thereby detect a reduction in the external power supply voltage. An operating current of the differential amplifying MOSFET is increased through the use of a current flowing in the capacitor due to such an external power variation, thereby executing the operation of stabilizing an output voltage corresponding to the reduction in the external power supply voltage.

Abstract: Frequency stabilization of chopper-stabilized amplifiers using multipath hybrid double-nested Miller compensation. The compensation may provide a desired 6 dB/oct roll off for both instrumentation amplifiers and operational amplifiers. Various embodiments are disclosed.

Abstract: Disclosed is a circuit for compensating for an offset voltage of a monitoring photodiode. After the offset voltage is measured in a photodiode test, current source and offset resistors are added according to the measured resistances, thereby compensating for the offset voltage.

Abstract: In an audio amplifier having a D-class power amplifier, a noise upon muting is suppressed. A sampling rate converter circuit for sampling rate converting a digital audio signal into a digital audio signal, and a ?? modulation circuit for re-quantizing the digital audio signal into a bit-reduced digital audio signal are provided. Further, a PWM modulation circuit for converting the digital audio signal into a PWM signal, and a D-class power amplifier to which the PWM signal are supplied. Still further, a dither signal forming circuit for superimposing a dither signal SDI on the digital audio signal, and a forming circuit for forming a muting signal SDET are provided. Upon muting, an input side of the sampling rate converter circuit is stopped by the muting signal SDET.

Abstract: The present invention provides an asynchronous BTL (Bridge Tied Load) design for a Class-D audio amplifier. The Class-D audio amplifier comprises two independent signal routes, each of the two independent signal routes includes a PWM (Pulse Width Modulator), a predriver and a power MOS circuit; each of the two independent signal routes receives an input signal via the PWM thereof, and outputs signal through the power MOS circuit thereof, and then cooperatively drive a loudspeaker; no synchronous signal is inputted to each of the two PWMs, and the two power MOS circuits feed back independent signals respectively to the two PWMs. The present invention omits the synchronous design of the prior art, and let the two push-pull signals required by the BTL design being processed independently, while cooperatively drive the loudspeaker.

Abstract: The invention relates to a VGA stage having a novel circuit configuration for amplifying/attenuating a differential input signal which is transmitted via a transmission line (H). The VGA stage comprises an operational amplifier (OPV1, OPV2), which is connected as shunt feedback, for amplifying the input signal; a string of resistors (R01, R01?) for attenuating the signal; and a control device (2) for switching the string of resistors (R01, R01?).

Abstract: An amplifier providing a drive signal indicative of a data input signal to a capacitive and/or resistive type load, the amplifier having a first transistor circuit adapted for converting the data input signal to a corresponding current signal in which the transistors of the first transistor circuit operate at a first voltage and having a second transistor circuit amplifying the current signal in which the transistors of the second transistor circuit operate at a second voltage. The first transistor circuit and the second transistor circuit are integrated for providing a class AB operable current output to the load.

Abstract: A differential amplifier circuit with feedback to increase common mode loop gain at low frequencies.

Abstract: An analog signal gain controller and equalizer with an increased signal bandwidth for reducing intersymbol interference (ISI) within a digital data signal.

Abstract: Phase-locked loop (PLL) methods and apparatus are described for generating multiple output clocks synchronized to different frequencies of multiple input signals, wherein the multiple-output PLL employs a single voltage controlled oscillator (VCO). In an embodiment, the base module generates signals with a controlled frequency, multiple equidistant phase, and reduced duty cycles. Frequency dividers using barrel-shifters driven by an early-late detector combined with a left/right “one hot” shift-register or driven by an early-late detector combined with up-down counter/decoder are also disclosed.

Abstract: The frequency changes in a bang-bang PLL that are generated using a digital phase detector's up/down signal are initially set to produce a faster pull-in rate and then reduced to produce a slower pull-in rate. The faster pull-in involves relatively large frequency changes and the slower pull-in rate involves smaller frequency changes. The changes in frequency of a bang-bang PLL can be implemented using a step size controller that includes timing control logic and step size logic. The function of the timing control logic is to control the timing of step size changes. The function of the step size logic is to set the step size of the frequency changes that are made by the VCO in response to the pd_up/down signal that is delivered directly to the VCO from the digital phase detector.

Abstract: An oscillator includes a resonant circuit of at least one inductance device and at least one tunable capacitance. The tunable capacitance is implemented through diffusion capacitances of at least one current-carrying transistor. The tunable capacitance has a first differential amplifier having a first transistor and a second transistor and a second differential amplifier having a third transistor and a fourth transistor Electrical properties of the first transistor and second transistor are complementary to electrical properties of the third transistor and fourth transistor, and control connections of the first transistor and the third transistor are connected to one another. Control connections of the second transistor and the fourth transistor are connected to one another. Second current connections of the first transistor and the third transistor are connected to one another, and second current connections of the second transistor and the fourth transistor are connected to one another.

Abstract: A semiconductor package includes a package substrate and an integrated circuit. The package substrate has a first surface. The integrated circuit couples electrically to the first surface of the package substrate. The integrated circuit and the package substrate together form the semiconductor package. The semiconductor package also includes a first inductance circuit and a second inductance circuit, both formed within the semiconductor package. The first and second inductance circuits couple to each other in parallel. The first and second inductance circuits have substantially symmetrical geometric characteristics.

Abstract: A self-calibrating integrated circuit includes a processor having at least one analog function used with the processor; one or more sensors adapted to sense one or more environmental parameters of the at least one analog function; and a solid state memory being configured to store the one or more environmental parameters of the at least one analog function.

Abstract: Proposed is a device actuated by a transponder for the generation of a switch signal. The device is based on an oscillating circuit (10) with a capacitance (C1), an identification coil (L1) and an oscillator amplifier (12). Connected to the oscillating circuit (10) is a frequency observer (20) which evaluates the frequency (f1) tuned in the oscillating circuit (10) and which when finding a change emits a switch signal (S). A change of the frequency in the oscillating circuit (10) is effected by the approach of a transponder (60). The device permits a nearly loadless transponder identification.

Abstract: An oscillator circuit includes a current source for generating a current depending on the ambient temperature, a plurality of oscillators for oscillating at respective periods depending on the current from the current source and based on different relations between the ambient temperature and the periods, and a frequency demultiplication unit for receiving an output signal from one of the oscillators selected by a period selecting circuit 103. The frequency dividing ratio of the frequency demultiplication circuit is set so that a higher ambient temperature provides a smaller frequency dividing ratio.

Abstract: A circuit arrangement having a plurality of variable capacitance elements such as varactors is described, the varactors having associated electronic control means which controls the capacitance of the variable capacitance elements over a control range. The control range is such that for any particular variable capacitance element a complete variation from a lowest to a highest capacitance is obtained from only a portion of the control range.

Abstract: A system is provided to improve frequency stability and system linearity in voltage controlled oscillators.

Abstract: In a surface acoustic wave device, electrode films constituting at least one IDT are disposed on a piezoelectric substrate, and an SiO2 film is arranged on the piezoelectric substrate so as to cover the electrode films. The film-thickness of the electrode films is in the range of about 1% to about 3% of the wavelength of an excited surface acoustic wave.

Abstract: A switch comprises voltage applying means for providing direct current potentials to first to third beams arranged with a spacing slightly distant one from another, and electrodes for inputting/outputting signals to/from the beams. By controlling the direct current potential provided to the beam, an electrostatic force is caused to thereby change the beam positions and change a capacitance between the beams. By causing an electrostatic force between the first and second beams and moving the both beams, the first and second beams can be electrically coupled together at high speed. Also, an electrostatic force is caused on the third beam arranged facing to the first and second beams, to previously place it close to the first and second beams. When the electrostatic force is released from between the first and second beams, the second beam moves toward the third beam thereby releasing the first and second beams of an electric coupling.

Abstract: A variable force solenoid is described, wherein the solenoid has a relatively long stroke and a relatively low profile. The solenoid includes an armature with at least one tapered surface and a pole piece with at least one tapered surface. The armature and the pole piece may each be provided with multiple tapers on more than one surface thereof.

Abstract: A magnetic securement device that includes a high energy magnet and a securing member. The magnet attaches to sheetrock walls through magnetic attraction to sheetrock screws or nails. The device would support display objects by either squeezing them between the device and the wall or by hanging them on hooks or frames affixed to the magnet. The magnet of the device is a lightweight rare earth magnet that provides great strength in a small package. The magnets are able to attach themselves to the head of a screw or nail and cling there with enough force to support light display objects attached thereto.

Abstract: A surface-mounting choke coil has a resin coating material with magnetic powder which is filled a space between the upper flange and the lower flange of a drum-type ferrite core, while covering the circumferential of the winding. The resin coating material with magnetic powder has a glass transition temperature Tg of about ?20° C. or lower, more preferably about ?50° C. or lower in a course of transferring from a glass state to a rubber state during changing of shear modulus with respect to temperature as a physical property when hardening, and the thickness of the upper flange of the drum-type ferrite core is about 0.35 mm or less, and a value of a ratio L2/L1 of an outer diameter L2 of the upper flange to a diameter L1 of the winding core of the drum-type ferrite core is about 1.9 or more.

Abstract: An ignition coil for an internal combustion engine minimizes the propagation of cracks in the encapsulate material surrounding the components of the ignition coil and provides a supplemental dielectric barrier. In one embodiment, the ignition coil comprises a housing, an outer core, an inner coil, and a coil assembly. The housing includes a bottom wall connected to an outer wall extending around the periphery of the housing. The outer core is positioned inside the outer wall, while the inner core is positioned inside the outer core. The coil assembly includes a primary winding and a secondary winding concentrically positioned relative to each other. The coil assembly is mounted to the inner core and positioned inside the outer core. The housing further includes an inner wall extending along the inner periphery of the outer core and positioned between the outer core and the coil assembly to prevent propagation of cracks.

Abstract: The present invention provides a filter circuit realizing reduction in the number of magnetic cores on a circuit board and a space occupied by the magnetic cores, and a power supply unit using the filter circuit. A filter circuit includes a first filter part and a second filter part which are connected in series. The first filter part includes a center leg coil and a capacitor, and the second filter part includes an outer leg coil and a capacitor. The center leg coil is wound around a center leg of a magnetic core including the center leg, a first outer leg part configuring a loop magnetic path in common with the center leg, and a second outer leg part configuring another loop magnetic path in common with the center leg. The first and second outer leg parts share the center leg. The outer leg coil is wound around the outer leg parts in a manner such that magnetic fluxes generated in the outer leg parts by current flowing in the outer leg coil cancel each other in the center leg.

Abstract: Some embodiments provide a first portion of an inductor disposed in a first layer of a multilayer substrate, a second portion of the inductor disposed in a second layer of the multilayer substrate, the second portion coupled to the first portion, and a shielding plane disposed between the first portion and the second portion.

Abstract: Provided are methods and devices in which an inductor is embedded in a package adapted to carry an integrated circuit and a magnetically permeable material is also embedded in the package so that the inductor and the magnetically permeable material are magnetically coupled to each other. In one embodiment, the magnetic permeable material is shaped as a pin which is press-fit into the core of a helix-shaped inductor embedded in the package substrate.

Abstract: A fuse structure is described. The fuse structure includes a first region adapted to be coupled to a voltage source, a second region adapted to be coupled to a ground, and a current flow region disposed between the first and second regions. The current flow region has a configuration that causes a void to be opened at a point of localized heating due to current crowding within the current flow region and that causes the void to propagate across the current flow region.

Abstract: A position sensor comprises a resistive element positionable on a first surface. A pair of leads are on the resistive element, the pair of leads adapted to supply a first voltage, such as by being grounded. An intermediate lead is positioned on the resistive element between the pair of leads, the intermediate lead being adapted to provide a second voltage. A contact element is positionable on a second surface, the contact element adapted to contact at least a portion of the resistive element to detect a voltage at a contact position, the detected voltage being related to the position or movement of the second surface relative to the first surface. In another version, a position sensor comprises a resistive element comprising first and second resistive strips. A plurality of leads are positioned on each resistive strip to provide a voltage to each resistive strip.

Abstract: A method for providing a security code comprises providing an access location identification and security device information. A user provides access location information and access duration information to a code generator system. The access location information and access duration information is encrypted to provide an access code. The user provides a user token data to the code generator system, such that the access code is encrypted using the user token data to provide a security code. The security code is dispatched to the user.

Abstract: A remote keyless entry (RKE) transponder has a noise alarm timer having a time interval used for determining whether a received signal meets a predefined condition within a time interval. If the received signal meets the predefined condition within the time interval, the noise alarm timer is disabled and the RKE transponder circuits are enabled so that normal operation in processing the desired signal commences. If the received signal does not meet the predefined condition within the time interval the noise alarm timer issues an alert signal, whereby appropriate action may be taken such as adjusting the channel input sensitivity, disabling a channel, or placing the RKE transponder into a sleep mode in order to reduce the power consumption caused by undesired input signals. A smart wake-up filter determines whether or not the input signal meets the predefined condition within the time interval.

Abstract: An obstacle detecting apparatus includes an image input unit for receiving images inputted respectively from a plurality of image pick-up devices and accumulating the input images, a feature calculating unit for calculating predetermined, specific feature quantities in the respective accumulated images, a feature comparing unit for comparing the feature quantities, and a result judging unit for judging the presence or absence of an obstacle on the basis of the comparison result. The obstacle detecting apparatus can thus detect an obstacle present on the road by distinguishing the obstacle from a mere object causing no obstruction to driving of the vehicle.