Abstract: The field-effect semiconductor device includes a channel layer; a contact layer; a semiconductor structure having an electron-affinity different from those of the channel layer and the contact layer and formed between the channel layer and the contact layer; an ohmic electrode formed on the contact layer; and a Schottky electrode formed on the semiconductor structure. The junction face between the channel layer and the semiconductor structure and the junction face between the contact layer and the semiconductor structure are iso-type heterojunctions.

Abstract: A power amplifier includes a substrate, a heat sink for dissipating heat, and a heterojunction bipolar transistor (HBT) disposed on the substrate. The HBT includes a collector, a base, and at least an emitter. The power amplifier further includes an emitter electrode directly connecting the heat sink and the emitter of the HBT. The emitter electrode is a flip-chip bump, and the heat sink is a metal layer that sandwiches the HBT with the substrate. Alternatively, the emitter electrode is a backside via that penetrates the substrate, and the heat sink is a metal layer, disposed on the substrate opposite the HBT.

Abstract: A semiconductor device includes a substrate having an active layer, an element region provided in the active layer, a P-type semiconductor region provided in the element region, and first and second N-type semiconductor regions provided in the element region, located on the sides of the P-type semiconductor region, respectively and spaced in a first direction. The device has an N-type MOS transistor and first and second P-type MOS transistors. The N-type MOS transistor has a first gate electrode provided on the P-type semiconductor region. The first P-type MOS transistor has a second gate electrode provided on the first N-type semiconductor region. The second P-type MOS transistor has a third gate electrode provided on the second N-type semiconductor region.

Abstract: A semiconductor storage device includes a semiconductor substrate; an sulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first conduction type both formed in the first semiconductor layer, and having a body of a second conduction type formed in the first semiconductor layer between the source region and the drain region, the memory cells being capable of storing data by accumulating or releasing electric charge in or from their respective body regions; memory cell lines each including a plurality of the memory cells aligned in the channel lengthwise direction; and a memory cell array including a plurality of the memory cell lines aligned in a channel widthwise direction of the memory cells.

Abstract: A semiconductor device which includes fuses for relieving defective areas in the semiconductor device is described. There is provided a semiconductor device including a semiconductor substrate having a circuit element, an insulating layer provided on the semiconductor substrate, a fuse element formed in the insulating layer, the fuse element including at least two fuse units connected in series, each of the fuse units having a resistor and a fuse connected in parallel, the fuse disposed above the resistor.

Abstract: A semiconductor device includes a semiconductor path, the semiconductor path including an organic semiconductor material, a first contact to inject charge carriers into the semiconductor path, a second contact to extract charge carriers from the semiconductor path, and a layer including phosphine arranged between the first contact and the semiconductor path and/or between the second contact and the semiconductor path. The phosphine in the layer acts as a charge transfer molecule which makes it easier to transfer charge carriers between contact and organic semiconductor material. As a result, the contact resistance between contact and organic semiconductor material can be reduced considerably.

Abstract: A semiconductor integrated circuit structure and method for fabricating. The semiconductor integrated circuit structure includes a light sensitive device integral with a semiconductor substrate, a cover dielectric layer disposed over the light sensitive device, and a lens-formation dielectric layer disposed over the cover dielectric layer. Light is transmittable though the cover dielectric layer; and through the lens-formation dielectric layer. The lens-formation dielectric layer forms an embedded convex microlens. The microlens directs light onto the light sensitive device.

Abstract: A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes. At least one nanoparticle is provided on the projecting feature between the first and second electrodes.

Abstract: The self-aligned Schottky-barrier clamped planar DMOS transistor structure comprises a self-aligned source region being surrounded by a planar gate region. The self-aligned source region comprises a moderately-doped p-base diffusion ring being formed in a lightly-doped N? epitaxial semiconductor layer, a heavily-doped n+ source diffusion ring being formed within the moderately-doped p-base diffusion ring, and a Schottky-barrier contact with the moderately-doped p-base diffusion ring acted as a diffusion guard ring being formed in a middle semiconductor surface portion of the self-aligned source region. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being silicided with or without metal silicide layers. The self-aligned source region further comprises a lightly-doped p? diffusion region being formed beneath a middle portion of the moderately-doped p-base diffusion ring.

Abstract: A memory device comprising a layer of piezoelectric material and a layer of ferroelectric material clamped together such that a voltage applied to one layer results in a voltage being generated across the other layer. The method of data storage and retrieval comprising the steps of: providing a layer of ferroelectric material, providing a layer of piezoelectric material, clamping the two layers together, storing data by internally polarising the ferroelectric material in one of two stable directions in accordance with the data to be stored, and retrieving stored data by applying a non-polarising voltage to one layer and detecting a resultant voltage from the other layer. Preferably, the piezoelectric material is implemented as a ferroelectric material.

Abstract: A semiconductor device is prepared using an insulating film consisting of a tantalum-tungsten oxide crystal film, a tantalum-molybdenum oxide crystal film, or a laminated film where a silicon oxide, silicon oxynitride or silicon nitride film is laminated on the crystal film. The tantalum-tungsten oxide film is deposited on a substrate under an atmosphere of a mixture of the first material gas comprising tantalum, the second material gas comprising tungsten and an oxidizing agent. For improving a dielectric constant of the tantalum-tungsten or tantalum-molybdenum oxide crystal film, on a Ru substrate with (001) orientation is deposited a oxide crystal film, which is then heated in N2O plasma and subject to rapid thermal nitriding.

Abstract: A semiconductor device and a manufacturing method thereof in which the peripheral length of an aperture and the mechanical strength of cylinders in a cell can be increased without changing the occupation rate of patterns in the cell. By forming a slit in the middle of each mask pattern so as not to expose parts of wafer, the aperture of the wafer becomes nearly cocoon-shaped with a constriction in the middle. Thereby, the peripheral length of the aperture can be increased without changing the occupation rate of the mask patterns in a cell. Further, the shape of the bottom of the aperture also becomes nearly cocoon-shaped with a constriction in the middle, and therefore it is possible to increase the mechanical strength of cylinders.

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Abstract: In a semiconductor device including a memory unit and a logic unit, a generation of a step in a terminal end surface of an electroconductive plug in a region above a capacitor element is inhibited. Such semiconductor device includes an insulating layer provided on the semiconductor substrate extending from the memory unit to the logic unit; a plurality of second interconnect connecting plugs embedded in the interlayer insulating film and the interlayer insulating film in the logic unit; capacitor elements embedded in the interlayer insulating film in memory unit; and dummy plugs, embedded in the interlayer insulating film and the interlayer insulating film in a region above a region that is provided with the capacitor element in the memory unit, and insulated from the capacitor element. A plurality of second interconnect connecting plugs and the dummy plug are terminated in the top surface of the interlayer insulating film.

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.

Abstract: A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers. A compatible non-volatile memory transistor can be formed from this basic structure by adding a high-K dielectric constant film with an embedded metal nano-dot layer between the tunnel insulator and the gate stack.

Abstract: Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer.

Abstract: An EEPROM memory transistor having a floating gate. The floating gate is formed using a BiCMOS process and has a first sinker dopant region proximate to a tunnel diode window, and a second sinker dopant region proximate to a coupling capacitor region. An optional third sinker region may be formed proximate to a source junction of the EEPROM memory transistor. Also, a shallow trench isolation (STI) region may be formed between the first and second sinker dopant regions.

Abstract: A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.

Abstract: There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.

Abstract: An enhancement mode field effect transistor whose operation threshold value varies greatly according to the substrate voltage. This field effect transistor is implemented by substituting the gate electrode of a depression mode field effect transistor for a gate electrode of the conductivity type opposite to that of a channel formation region, or a midgap gate electrode. In a preferred embodiment of the present invention, this field effect transistor is provided between a CMOS structure logic gate and a ground line. As a result, the leak current when the field effect transistor is not operating can be diminished without reducing the operational speed of the logic gate.

Abstract: A semiconductor device includes a semiconductor substrate; a first insulation layer formed on the semiconductor substrate; a semiconductor layer insulated from the semiconductor substrate by the insulation layer; a source region of a first conduction type and a drain region of the first conduction type formed in the semiconductor layer; a body region of a second conduction type formed in the semiconductor layer between the source region and the drain region, said body region being capable of storing data by accumulating or releasing electric charge; a second insulation layer formed on the body region; a word line formed on the second insulation layer and insulated from the body region by the second insulation layer; and a bit line electrically connected to the drain region, wherein the area of the body region in contact with the first insulation layer is larger than the area thereof in contact with the second insulation layer.

Abstract: A silicon-on-insulator (SOI) substrate including laminated layers of a substrate, an oxide layer, and a silicon layer in order. The oxide layer has an electrifying hole fluidly connected with the substrate and the electrifying hole is filled with a part of the silicon layer. A method for fabricating the floating structure is also disclosed which includes the steps of forming an oxide layer having a predetermined thickness on a substrate, forming one or more electrifying holes in an area of the oxide layer corresponding to an inner part of the floating structure, forming a silicon layer on the oxide layer including an electrification structure electrically connecting the silicon layer to the substrate, forming a pattern for the floating structure on the silicon layer, removing the oxide layer corresponding to an inner area of the pattern, forming a thermal oxide layer on a surface of the silicon layer, and removing the thermal oxide layer to form the floating structure.

Abstract: A nonvolatile semiconductor memory device whose gate structure of a transistor other than a memory cell transistor has a same stacked gate structure as the memory cell transistor, the gate structure comprising a semiconductor substrate, a first insulation film provided on the semiconductor substrate, a first conductive film provided on the first insulation film, a second insulation film, provided on the first conductive film, having an opening, a spacer provided on the second insulation film to define the opening, and a second conductive film provided on the spacer and electrically connected to the first conductive film via the opening.

Abstract: An insulating film includes a first barrier layer, a well layer provided on the first barrier layer, a second barrier layer provided on the well layer. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer consists of a material having a second bandgap smaller than the first bandgap and having a second relative permittivity larger than first relative permittivity. The second barrier layer consists of a material having a third bandgap larger than the second bandgap and having a third relative perminivity smaller than second relative permittivity. Each of the first and second barrier layers has a thickness not smaller than 2.5 angstroms, and 2.5>(d1/?1+d2/?2) is satisfied where d1 and d2 (angstrom) are the thicknesses of the first and second barrier layers, respectively, ?1 is the first relative permittivity, and ?2 is the third permittivity.

Abstract: A method of forming a raised source/drain proximate a spacer of a gate of a transistor on a substrate, and a semiconductor device of an integrated circuit employing the same. In one embodiment, the method includes orienting the gate substantially along a <100> direction of the substrate. The method also includes providing a semiconductor material adjacent the spacer of the gate to form a raised source/drain layer of the raised source/drain oriented substantially along a <100> direction of the substrate.

Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset of 2 eV or greater. Gate oxides formed from elements such as yttrium and gadolinium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract: A method for fabricating a MEMS device comprises providing a substrate having a back side, a front side opposite to the back side and a periphery portion. A desired microstructure is formed on the back side of the substrate. The substrate is then supported for rotation. A precursor solution is deposited on the front side of the substrate during rotation so that a thin film layer may be formed thereon. During formation of the thin film layer, the substrate is supported and rotated that the microstructure formed on the back side is protected.

Abstract: A high performance MTJ in an MRAM array is disclosed in which the bottom conductor has an amorphous Ta capping layer. A key feature is a surfactant layer comprised of oxygen that is formed on the Ta surface. The resulting smooth and flat Ta capping layer promotes a smooth and flat surface in the MTJ layers which are subsequently formed on the surfactant layer. For a 0.3×0.6 micron MTJ bit size, a 35 to 40 Angstrom thick NiFe(18%) free layer, an AlOx barrier layer generated from a ROX oxidation of an 9 to 10 Angstrom thick Al layer, and a Ru/Ta/Ru capping layer are employed to give a dR/R of >40% and an RA of about 4000 ohm-?m2. The MTJ configuraton is extendable to a 0.2×0.4 micron MTJ bit size.

Abstract: A magnetic random access memory with lower switching field is provided. The memory includes a first antiferromagnetic layer, a pinned layer formed on the first antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, a ferromagnetic free layer formed on the tunnel barrier layer, and a multi-layered metal layer. The multi-layered metal layer is formed by at least one metal layer, where the direction of the anisotropy axis of the antiferromagnetic layer and the ferromagnetic layer and that of the ferromagnetic free layer are arranged orthogonally. The provided memory has the advantage of lowering the switching field of the ferromagnetic layer, and further lowering the writing current.

Abstract: In a semiconductor device having a MEMS according to this invention, a plurality of units having movable portions for constituting a MEMS are monolithically mounted on a semiconductor substrate on which an integrated circuit including a driving circuit, sensor circuit, memory, and processor is formed. Each unit has a processor, memory, driving circuit, and sensor circuit.

Abstract: An integrated photosensitive device with a metal-insulator-semiconductor (MIS) photodiode constructed with one or more substantially continuous layers of semiconductor material and with a substantially continuous layer of dielectric material.

Abstract: A photo-detecting device that enables a solid-state image sensor to meet the requirement of higher quality imaging including: a first silicon substrate 120 having p- and n-type regions; a first SOI substrate 130 in which a second silicon substrate 132 having p- and n-type regions is formed on a first SOI insulation layer 131; and a second SOI substrate 140 in which a third silicon substrate 142 having p- and n-type regions is formed on a second SOI insulation layer 141. Each pn-junction of the first silicon substrate 120, the second silicon substrate 132, and the third silicon substrate 142 forms a photodiode for converting incident light into electric charges. The depth of each pn-junction, which is measured from the surface of the second SOI substrate 140 irradiated with the light, is determined according to absorption length of light to be converted into electric charges.

Abstract: The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride film and having a window; depositing a second silicon nitride film covering an inner surface of the isolation trench; forming a first silicon oxide film burying the isolation trench; etching and removing the first silicon oxide film in an upper region of the isolation trench; etching and removing the exposed second silicon nitride film; chemical-mechanical-polishing the second silicon oxide film; and etching and removing the exposed first silicon nitride film.

Abstract: The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or other integrated circuit device. The capacitive memory elements may have a generally oblong shape and may be capacitive elements. The capacitive memory elements may be disposed in a slanted orientation. The capacitive memory elements may be disposed in a non-orthogonal orientation. The capacitive memory elements may be disposed so that an axis through one of the plurality of capacitive memory elements is not generally parallel with an edge of the substrate. The axis may not be generally perpendicular with an orthogonal edge of the substrate. The plurality of capacitive memory elements may be arranged in a first row and a second row so that an axis through one of the plurality of capacitive memory elements located in the first row does not form an axis of any capacitive memory element in the second row.

Abstract: A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current path through the first region is determined by a portion of a doping boundary between the first region and the second region.

Abstract: In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

Abstract: The manufacturing method for an electronic circuit device comprises attaching an electronic circuit assembly including a circuit substrate with electronic circuit elements attached to a base, joining lead terminals integrally with the base via frames before molding the lead terminals composed of a different material from that of the base with mold resin, electrically connecting the lead terminals to the electronic circuit assembly, molding the electronic circuit assembly, lead terminals, and flange with mold resin in a batch partially excluding the flange and lead terminals installed on the base, and separating and removing the frames from the lead terminals and base after the molding with the mold resin.

Abstract: A semiconductor device has an, improved mounting reliability and has external terminals formed by exposing portions of leads from a back surface of a resin sealing member. End portions on one side of the leads are fixed to a back surface of a semiconductor chip, and portions of the leads positioned outside the semiconductor chip are connected with electrodes formed on the semiconductor chip through wires.

Abstract: A semiconductor package including a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.

Abstract: A power module package is provided. The power module package includes a power circuit element, a control circuit element, a lead frame, a heat sink, and an epoxy molding compound (EMC). The control circuit element is connected to the power circuit and controls chips in the power circuit. The lead frame has external connecting means formed at the edges thereof, and a down set part, namely, formed between the external connecting means. The lead frame has a first surface to which the power circuit and the control circuit are attached, and a second surface used as a heat dissipating path, in particular, the power circuit is attached to the down set part. The heat sink which is closely attached to the down set part of the second surface of the lead frame by an adhesive. The EMC surrounds the power circuit, the control circuit, the lead frame and the heat sink, and exposes the external connecting means of the lead frame and a side of the heat sink.

Abstract: A substrate is provided for packaging a microelectronic device having a pattern of contacts on the surface thereof. The substrate is formed from a support member having a substantially planar surface, and first, second, and third electrically conductive paths. The electrically conductive paths each extends from a corresponding device-attachable region on the substantially planar surface. The third device-attachable regions are each substantially equidistant to the first and second device-attachable regions. In addition, the device contact pattern may correspond spatially to a pattern formed by the first and third device-attachable regions or by the second and third device-attachable regions may form a second pattern. Also provided is a method for attaching a microelectronic device to a substrate. The invention is particularly suited for use in forming packages having a flip-chip configuration.

Abstract: A multichip package has a leadframe including peripheral leads arranged about a centrally situated die paddle. A first (“upper”) die is attached to a first (“top”) side of the leadframe die paddle, which can be generally flat. The second (“bottom”) side of the leadframe is partially-cut away (such as by partial etching), so that an outer part of the die paddle is thinner, and so that an inner part of the leads is thinner. These partially cutaway portions in the second (“bottom”) side of the leadframe provide a cavity, in which a second (“lower”) die is attached active side upward. The lower die may have bond pads situated near the center of the active surface, and electrical interconnection of the lower die may be made by wire bonds running through the gap between the die paddle and the leads; or, the lower die may be attached, and electrically interconnected, by flip chip interconnect to the die attach side of the cavity in the leadframe.

Abstract: This invention relates to an integrated circuit device, in particular for manufacturing smart card electronic units for smart cards. It comprises: an active layer (32) including a semiconductor material within which integrated circuits are formed and having a face (34) provided with a plurality of electrical connection terminals (36) and a second face, wherein said face has a thickness smaller than 100 ?m, and a complementary layer (40) having a first face (42) attached to the active face of the active layer, a second face (44) and a side surface (48), wherein said complementary layer includes a plurality of recesses (46), each recess extending through the whole thickness of the complementary layer, and extending from a contact terminal (36) to said side surface (48).

Abstract: A semiconductor arrangement is disclosed, having transistors based on organic semiconductors and non-volatile read/write memory cells. The invention relates to a semiconductor arrangement, constructed from transistors, in the case of which the semiconductor path is composed of an organic semiconductor, and memory cells based on a ferroelectric effect perferably in a polymer, for use in RF-ID tags, for example.

Abstract: Disclosed is a land grid array module comprising: a substrate; a plurality of active and passive components mounted on both sides of the substrate; and a molding compound for encapsulating the both sides of the substrate with the active and passive components mounted thereon. The land grid array module mounts the passive and active components on both sides of the substrate, thereby improving the integration of the circuit device. Also, the use of a thin film printed circuit board or a flexible printed circuit board with high rigidity as the substrate reduces the overall thickness of the land grid array module.

Abstract: A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.

Abstract: Die pads 50, 51, an external connecting electrode 52 and a bridge are covered with an insulating resin after half-etching, formed into a single package without a coupling member such as a supporting lead or adhesive tape. In addition, since no supporting board is required, a low-profile semiconductor device with improved heat radiation can be provided.

Abstract: A semiconductor component package configuration includes a semiconductor chip mounted to a printed circuit board, and a substrate arranged between the semiconductor chip and the printed circuit board. The substrate is for routing the wiring terminals of the semiconductor chip to the printed circuit board. The substrate is connected to the printed circuit board by solder joints. A filler between the semiconductor chip and the substrate mechanically isolates the semiconductor chip and the solder joints. A metal layer, which is connected to solder joints, is applied to the substrate. At least one molded element of heat-dissipating material is applied to the metal layer and is connected in a heat-conducting manner to the metal layer. This provides the package configuration with an improved capability of conducting the lost power that is dissipated from the installed semiconductor chip, and the desired mechanical properties of the package arrangement are retained.