Abstract: A field-effect transistor includes a substrate, a source electrode, a drain electrode, a gate electrode, a gate-insulating film, and an active layer. The active layer contains an oxide having a transmittance of 70% or more in the wavelength range of 400 to 800 nm. A light-shielding member is provided as a light-shielding structure for the active layer, for example, on the bottom face of the substrate.

Abstract: An exemplary method for fabricating a thin film transistor (TFT) array substrate (200) includes: forming a transparent conductive layer (202) and a gate metal layer (203) on an insulating substrate (201); forming a photo-resist layer (231) on the gate metal layer; exposing the photo-resist layer using a photo-mask with a predetermined pattern; developing the photo-resist layer to form a photo-resist pattern; and etching the transparent conductive layer and the gate metal layer using the photo-resist pattern as a mask to form a plurality of gate electrodes (213) and a plurality of pixel electrodes (212). Compared to the conventional method, in the above-described exemplary method for fabricating the TFT array substrate, only one photo-mask process is used to form the gate electrodes and the pixel electrodes, thus saving one photo-mask process. Therefore, a simplified method at a reduced cost is provided.

Abstract: A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.

Abstract: The invention enhances a production yield of a display device (an electro-optical device). The invention provides a method of manufacturing an electro-optical device including a display region in which a plurality of basic pixels are arranged, each basic pixel including a plurality of color pixels. The method includes: forming on a first substrate lines to drive a plurality of electro-optical elements respectively constituting the color pixels, correspondingly to the arrangement of the basic pixels; forming on a second substrate, as a chip to be transferred to each basic pixel, a drive circuit to drive the plurality of electro-optical elements which constitutes the plurality of color pixels of the basic pixels to obtain a plurality of basic-pixel driving chips; and transferring step of transferring the respective basic-pixel driving chips from the second substrate onto the first substrate, and connecting the drive circuits to regions of the lines corresponding to the basic pixels.

Abstract: An object of the present invention is to provide an efficient method for manufacturing a p-type group III nitride semiconductor that has adequate carrier concentration and a surface with a low occurrence of crystal damage. The inventive method for manufacturing a p-type group III nitride semiconductor comprises: (a) growing a group III nitride semiconductor containing a p-type dopant at 1000° C. or higher in an atmosphere containing H2 gas and/or NH3 gas; and (b) after the growth of the group III nitride semiconductor, substituting the H2 gas and NH3 gas with an inert gas at a temperature higher than 800° C. while reducing the temperature.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: The invention relates to a photoactive component, especially a solar cell, comprising organic layers and formed by at least one stacked pi, ni, and/or pin diode. The diodes are characterised in that they comprise at least one p-doped or n-doped transport layer having a larger optical band gap than that of the photoactive layer. The individual diodes are characterised by a high internal quantum yield, but can be optically thin (peak absorption <80%). A high external quantum yield is obtained by either enlarging the optical path of the incident light in the diodes using light traps, or by stacking a plurality of the diodes. The transition between two diodes being facilitated by transition layers for the purposes of improved recombination and generation. Both forms of embodiment have a number of specific advantages using the doped transport layers with a large band gap.

Abstract: A light emitting diode including a substrate, a semiconductor stacking layer, a first electrode and a second electrode is provided. The semiconductor stacking layer including an n-type doped semiconductor layer, a p-type doped semiconductor layer and an active layer is disposed on the substrate. The n-type doped semiconductor layer has In dopant. The active layer is disposed between the n-type doped semiconductor layer and the p-type doped semiconductor layer. In addition, the first electrode is disposed on the n-type doped semiconductor layer while the second electrode is disposed on the p-type doped semiconductor layer. In the light emitting diode mentioned above, no crack, open or pin hole are found in the n-type doped semiconductor layer, thus the light emitting diode mentioned above has lower power consumption, higher manufacturing yield and better reliability.

Abstract: A III-nitride power device for controlling high currents as an interdigitated electrode pattern for increasing device rating while decreasing device dimensions. Fingers of the interdigitated electrode pattern have tips with smaller dimensions than the remainder of the fingers. The tapered finger design balances current flow in the electrode fingers to reduce device resistance while permitting a more compact construction.

Abstract: A flat lamp panel includes a top substrate and a bottom substrate. The bottom substrate includes at least an electrode pair, a dielectric layer, and a first phosphor layer covering the up surface of the bottom substrate. The top substrate is disposed above the bottom substrate in a parallel manner. A first magnesium oxide layer and a second phosphor layer with patterns are disposed on the down surface of the top substrate, in which the down surface of the top substrate faces the up surface of the bottom substrate. Preferably, the flat lamp panel further includes a discharged space formed between the top substrate and the bottom substrate and a gas filled within the discharged space.

Abstract: An LED-based illumination device can use an array of four LEDs to produce high intensity light over a broad color spectrum and a broad range of color temperature. A high quality white light can be produced by using two green LEDs with a single red and a single blue LED.

Abstract: It is an object of the present invention to provide a light-emitting element having, between a pair of electrodes, a layer containing a light-emitting material and a transparent conductive film, wherein the electric erosion of the transparent conductive film and reflective metal can be prevented and to provide a light-emitting device using the light-emitting element. According to the present invention, a first layer 102 containing a light-emitting material, a second layer 103 containing an N-type semiconductor, a third layer 104 including a transparent conductive film, and a fourth layer 105 containing a hole-transporting medium are provided between an anode 101 and a cathode 106, wherein the first layer 102, the second layer 103, the third layer 104, the fourth layer 105, and the cathode 106 are provided in order, and wherein the cathode has a layer containing reflective metal.

Abstract: A light emitting device includes a substrate and an adhesive layer on the substrate. At least two multi-layer epitaxial structures are on the substrate. Each structure sequentially includes an upper cladding layer, an active layer, a lower cladding layer, an ohmic contact epitaxial layer, and a first ohmic contact electrode adhered to the substrate by the adhesive layer. A second ohmic contact electrode is on the lower cladding layer. A channel divides the active layer into two portions. A first electrode is on the lower cladding layer corresponding to a first portion of the active layer. A second electrode is on the second ohmic contact electrode corresponding to a second portion of the active layer. A connection layer is formed in the structure so as to couple the first electrode with the first ohmic contact electrode. A dielectric layer is between these two structures. A conductive line couples the electrodes of these two structures.

Abstract: A nitride-based semiconductor LED which is flip-chip bonded on a lead pattern of a sub-mount through a bump ball comprises a substrate; a light-emitting structure formed on the substrate; an electrode formed on the light-emitting structure; a protective film formed on the resulting structure having the electrode formed therein, the protective film exposing the electrode surface corresponding to a portion which is connected to the lead pattern of the sub-mount through the bump ball; and a grid-shaped buffer film formed on the electrode surface exposed through the protective film.

Abstract: A light emitting device has a light emitting diode (LED), a reflector cup, and one or more adjustment mechanisms to control the intensity profile of light emitted from the light emitting device. The reflector cup has a base and a sidewall extending outward from the base. A base adjustment mechanism controls the total amount of light reflected from the base and into the beam of light emitted from the light emitting mechanism by controlling the aggregate reflectivity of the base. A sidewall adjustment mechanism controls the angle of the sidewall relative to the base. A vertical adjustment mechanism vertically raises or lowers the LED relative to the base.

Abstract: An image sensor structure with a connector includes a substrate having an upper surface, which is formed with a central region and first electrodes arranged at the periphery of central region, and a lower surface is formed with second electrodes corresponding to electrically connect the first electrodes. A frame layer is arranged at the upper surface of the substrate, so that a cavity is formed between with substrate and frame layer. A chip is mounted at the central region of the upper surface of the substrate and is located within the cavity. A plurality of bonding pads is formed at the periphery of the chip. A plurality of wires are electrically connected the bonding pads of the chip to the first electrodes of the substrate, so that the signal from the chip is transmitted to the second electrodes of the substrate through the first electrodes. The transparent layer is covered on the frame layer to encapsulate the chip.

Abstract: A semiconductor light emitting device comprises: a semiconductor light emitting element that emits first wavelength light; a first fluorescent material that absorbs the first wavelength light and emits second wavelength light having a longer wavelength than the first wavelength light; and a second fluorescent material that absorbs the first wavelength light and emits third wavelength light having a longer wavelength than the second wavelength light. The first fluorescent material and the second fluorescent material are represented by a common chemical composition formula. The first wavelength light, the second wavelength light, and the third wavelength light are combined into light emission of mixed color.

Abstract: A light emitting diode package is provided. A package body has a mounting part surrounded by side walls and lead electrodes on a bottom surface of the mounting part. A light emitting diode chip is mounted on the bottom surface of the mounting part and electrically connected to the lead electrodes. A resin encapsulant is filled in the mounting part to encapsulate the light emitting diode chip. At least one residual resin storage is formed on a top surface of a corresponding one of the side walls to guide and accommodate a residual resin for forming the encapsulant of a preset height. Further, a storing groove is formed on the top surface of the corresponding side wall and a guiding groove is formed to guide the residual resin to the storing groove. This produces the light emitting diode package with uniform color distribution regardless of a liquid resin amount injected.

Abstract: The light emitting device has a light emitting diode which is made of a nitride semiconductor and a phosphor which absorbs a part of lights emitted from the light emitting diode and emits different lights with wavelengths other than those of the absorbed lights. The phosphor is made of alkaline earth metal silicate fluorescent material activated with europium.

Abstract: A multiple layered buffer structure for nitride based semiconductor device is provided herein. The buffer structure contains a first layer of AlxInyGa1-x-yN grown under a high temperature, and a second layer of an un-doped or appropriately doped GaN based material grown under a low temperature The GaN based material of the second layer could be doped with Al, or In, or codoped with one of following sets of elements: Al/In, Si/In, Si/Al, Mg/In, Mg/Al, Si/Al/In, and Mg/Al/In. In another embodiment, the buffer structure contains a GaN seed layer, an AlInN thin layer, a GaN based main layer, and a GaN based thin layer. The GaN seed layer is grown under a high temperature while the other layers are grown under a low temperature.

Abstract: The present invention provides a semiconductor device in which a power line is not affected by noise due to a voltage drop caused by instantaneous high-current consumption in the buffer portion and that has no possibility that a logic portion malfunctions. In a case where the same potential is supplied to a logic portion and a buffer portion, by a method in which separate FPC terminals are used for the logic portion and the buffer portion, or by a method in which the FPC terminal is shared but a power line is branched for the logic portion and the buffer portion at a point close to the FPC terminal, a problem that the logic portion is affected by noise generated by a voltage drop of the power line due to instantaneous high-current consumption in the buffer portion can be prevented.

Abstract: The present invention replaces a standard size halogen tungsten lamp spotlight or floodlight with a much cooler LED lamp that also fits into existing housings. However, the LED's still need to be cooled. The Present Invention mounts up to three LED's into a special reflector with a plurality of specially designed heat sinking fins arranged in a star configuration. Peltier junctions may also be used to further direct heat to the fins.

Abstract: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare die electronic element is provided having a top conductive side and a bottom conductive side. Each bare die electronic element is disposed so that the top conductive side is in electrical communication with the top electrically conductive surface and so that the bottom conductive side is in electrical communication with the bottom electrically conductive surface.

Abstract: A light emitting diode including a substrate, a semiconductor layer, multiple electrodes, a passivation layer, multiple under bump metallurgy (UBM) layers and a reflective layer is provided. The semiconductor layer is disposed on the substrate. The electrodes and the passivation layer are disposed on the semiconductor layer. The passivation layer has multiple openings for exposing the electrodes. The UBM layers are disposed on the electrodes. The reflective layer is disposed on the passivation layer. The reflective layer is electrically isolated from the electrodes and the UBM layers. A method of fabricating the light emitting diode is also provided. The reflective layer and the UBM layers are fabricated simultaneously in one process. Therefore, the fabricating method is compatible with the existing process.

Abstract: A light emitting diode (LED) package unit, comprising a substrate having a concave, a LED chip, at least two electrodes, at least two wires, a gel and a first wavelength-converting material. The LED chip, disposed in the concave, comprising a top-face, a bottom-face for jointing with the substrate, and at least two chip-electrodes. The LED chip emits light of a first wavelength. The electrodes are disposed on the substrate. The wires are respectively connecting one of the chip-electrode with one of the electrode. The gel is disposed to seal the LED chip and the wires. The first wavelength-converting material comprising Sr—Si—O—N:Eu is doped within the gel. The first wavelength-converting material absorbs light of the first wavelength and emits light of a second wavelength longer than the first wavelength.

Abstract: A LED chip including a substrate, a first type doped semiconductor layer, a second type doped semiconductor layer, a light emitting layer, at least an Indium-doped AlxGa1-xN based material layer (0?x<1) and at least a tunneling junction layer is provided. The first type doped semiconductor layer is disposed on the substrate, and the light emitting layer is disposed between the first type doped semiconductor layer and the second type doped semiconductor layer. The Indium-doped AlxGa1-xN based material layer is disposed on at least one surface of the light emitting layer, and the tunneling junction layer is disposed between the Indium-doped AlxGa1-xN based material layer and the first type doped semiconductor layer and/or disposed between the Indium-doped AlxGa1-xN based material layer and the second type doped semiconductor layer, wherein the Indium-doped AlxGa1-xN based material layer and the tunneling junction layer are disposed on the same side of the light emitting layer.

Abstract: A light-emitting element, in particular a light-emitting diode, having at least one light-emitting chip crystal, in particular a semiconductor crystal, is described. At least free surfaces of the light-emitting chip crystal are covered with an inert material—liquid fluid—which is in direct contact with the light-emitting chip crystal.

Abstract: A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element. A first well region of a first conductivity type formed within a semiconductor body. A first region of the first conductivity type is formed within the first well region. A second region of a second conductivity type is formed with the first well region. A second well region having the second conductivity type is formed within the semiconductor body adjacent the first well region. A third region of the first conductivity type is formed within the second well region. A fourth region of the second conductivity type is formed within the second well region. The trigger element is connected to the first region and alters a base trigger voltage and a base holding voltage into an altered trigger voltage and an altered holding voltage. A first terminal or pad is connected to the second region. A second terminal is connected to the third region, the fourth region, and the trigger element.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory cell of a substrate that includes (1) a PFET with an orientation approximately planar to a surface of the substrate; and (2) an NFET coupled to the approximately planar PFET. An orientation of the NFET in the substrate is approximately perpendicular to the orientation of the PFET. Numerous other aspects are provided.

Abstract: This invention comprises photodiodes, optionally organized in the form of an array, including p+ deep diffused regions or p+ and n+ deep diffused regions. More specifically, the invention permits one to fabricate thin 4 inch and 6 inch wafer using the physical support provided by a n+ deep diffused layer and/or p+ deep diffused layer. Consequently, the present invention delivers high device performances, such as low crosstalk, low radiation damage, high speed, low leakage dark current, and high speed, using a thin active layer.

Abstract: A MIS transistor includes a gate electrode portion, insulating sidewalls formed on side surfaces of the gate electrode portion, source/drain regions and a stress film formed so as to cover the gate electrode portion and the source/drain regions. A height of an upper surface of the gate electrode portion is smaller than a height of an upper edge of each of the insulating sidewalls. A thickness of first part of the stress film located on the gate electrode portion is larger than a thickness of second part of the stress film located on the source/drain regions.

Abstract: A semiconductor substrate (1) of GaAs with a semiconductor layer sequence (2) applied on top. The semiconductor layer sequence (2) contains a plurality of semiconductor layers (3, 4, 5, 6, 7) of Al1?yGayAs1?xPx with 0?x?1 and 0?y?1, the phosphorus component x in a number of the semiconductor layers respectively being greater than in a neighboring semiconductor layer lying thereunder in the direction of growth. Such a semiconductor substrate may be advantageously used as a quasi-substrate substrate (8) for growing further semiconductor layers (28) which have a smaller lattice constant than GaAs.

Abstract: In a semiconductor photo-detecting element (an avalanche photodiode), a high-sensitivity element is obtained by incorporating a multiplication layer having high-performance multiplication characteristics. By using a structure which reduces an electric field applied to an etching stopper layer, it is possible to use a multiplication layer having higher-performance multiplication characteristics (a multiplication layer which performs multiplication with a high electric field). The first method to realize this is to use a conductivity type multiplication layer. The second method is to use a structure in which a field buffer layer of the second conductivity type is incorporated. As a result of the use of these methods, a structure which applies an electric field lower than the multiplier electrical field to the etching stopper layer is obtained.

Abstract: A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive plane. This combination of series inductances and shunt resonant vias lowers the cutoff frequency for the fundamental stopband. The series inductances and shunt capacitances may be implemented using surface mount component technology, or printed traces. Patches may also be interconnected by coplanar coupled transmission lines. The even and odd mode impedances of the coupled lines may be increased by forming slots in the second conductive plane disposed opposite to the transmission line, lowering the cutoff frequency and increasing the bandwidth of the fundamental stopband.

Abstract: The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bottom to top on a semi-insulating substrate. The high-resistivity structure comprises at least two layers. A first layer is on top of the HBT structure to provide the required high resistivity, while the second layer having a high purity is on top of the first layer to prevent the doped impurity in the first layer to affect the upper FET structure.

Abstract: A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor.

Abstract: Embodiments of the present invention provide an integrated circuit (IC) in which power to input output (IO) drivers may be distributed within unused areas over macro processing circuits. This IC includes a long distance power and ground distribution network, an input output (IO) power and ground distribution network, a number of macro processing circuits, and IO circuits. The long distance power and ground distribution network electrically couples to the IO power and ground distribution network. Both the power and ground distribution networks may be located within the upper level conductive layers. IO power and ground distribution network locally supplies power and ground to IO circuits. Macro processing circuits may be located beneath the power distribution network as some macro processing circuits do not require access to upper level conductive layers. By placing these macro processing circuits beneath these power distribution networks, die size may be reduced.

Abstract: Bond pad structures are presented. Some embodiments of the structure include a conductive conductor-insulator layer overlying a substrate. The conductive conductor-insulator layer includes a composite region having a conductor sub-region and insulator sub-region, which neighbor each other, and a single material region. The insulator is harder than the conductor.

Abstract: An array substrate includes a substrate, an electrode pad, an insulating layer and a transparent electrode. The substrate includes a display region and a peripheral region adjacent to the display region. The electrode pad is in the peripheral region. The electrode pad includes a first metal layer and a second metal layer. The second metal layer is on the first metal layer, and includes an opening through which the first metal layer is partially exposed. The insulating layer is on the electrode pad and covers a side surface of the second metal layer in the opening and a portion of the exposed the first metal layer. The transparent electrode is on the insulating layer, and is electrically connected to the first metal layer through a via hole in the insulating layer.

Abstract: A thin-film device is fabricated by forming a protective layer and a thin-film device layer one by one on a first substrate and bonding a second substrate on the thin-film device layer via a first adhesive layer or a coating layer and first adhesive layer, removing the first substrate at least in a part thereof by etching with a chemical solution, bonding the protective layer, which covers the thin-film device layer on a side of the first substrate, to a third substrate via a second adhesive layer, and removing the second substrate. The protective layer is formed of at least two layers having resistance to the chemical solution used upon removal of the first substrate.

Abstract: A method of forming a semiconductor structure comprises providing an insulator layer overlying a III-V compound substrate, the insulator layer having a surface charge layer, the surface charge layer having a deleterious performance effect on the underlying layer or layers of the III-V compound substrate. The method further comprises transforming the surface charge layer into a passivated surface layer, wherein the passivated surface layer reduces the deleterious performance effect on the underlying layer or layers.

Abstract: There is provided a field effect transistor (FET) including a source side semiconductor; a drain side semiconductor; and a gate. The source side semiconductor is made of a high mobility semiconductor material, and the drain side semiconductor is made of a low leakage semiconductor material. In one embodiment, the FET is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). There is also provided a method for manufacturing the FET.

Abstract: A thin film transistor array substrate and a manufacturing method thereof are provided. Wherein, scan lines and data lines are disposed on a substrate to define a plurality of pixel regions. Thin film transistors are disposed in the pixel regions correspondingly and driven by the scan lines and the data lines. Pixel electrodes are disposed in the pixel regions respectively and electrically connected to the corresponding thin film transistors. In addition, a gate insulating layer is disposed on the substrate to cover the scan lines and gates of the thin film transistors. A patterned leaning layer is disposed on the gate insulating layer and forms a plurality of non-continuous patterns under the data lines. The non-continuous patterns expose portions of the gate insulating layer under the data lines to which a portion of each data line can be directly attached.

Abstract: A field-effect transistor for a narrow-body, multiple-gate transistor such as a FinFET, tri-gate or ?-FET is described. The corners of the channel region disposed beneath the gate are rounded n, for instance, oxidation steps, to reduce the comer effect associated with conduction initiating in the corners of the channel region.

Abstract: The present invention relates to a semiconductor device comprising at least one gate located in each of a memory array area and a periphery circuit area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. The semiconductor device also comprises a barrier layer, which is located in the memory array area and the periphery circuit area, an undoped oxide barrier, which is located on the barrier layer in the periphery circuit area, and a boron-containing silicate glass, which is located on the barrier layer in the memory array area and on the undoped oxide barrier in the periphery circuit area.

Abstract: A thin film transistor array, an electrostatic discharge protective device thereof, and methods for fabricating the same are provided. The thin film transistor array comprises a plurality of scan lines, a plurality of data lines, a first shorting bar, and a second shorting bar. The electrostatic discharge protective device comprises a switching device and a resistance line in parallel. If static electricity accumulated on the TFT array is over a predetermined range, the accumulated static electricity will be conducted to the first or second shorting bar via the switching device. The resistance line can prevent signals applied to one of the scan lines or data lines from being conducted to other scan lines or data lines, to detect a defective pixel.

Abstract: A sensor chip includes a layer-shaped base body, which has a plurality of fine holes formed in one surface, and fine metal particles, each of which is loaded in one of the fine holes of the base body. At least a part of each of the fine metal particles is exposed to a side of the layer-shaped base body, which side is more outward than the one surface of the layer-shaped base body. The layer-shaped base body may be constituted of anodic oxidation alumina. The sensor chip constitutes a sensor utilizing localized plasmon resonance, with which a state of binding of a sensing medium with a specific substance is capable of being detected quickly and with a high sensitivity.

Abstract: Disclosed is a semiconductor device has a semiconductor substrate of a first conductivity type in which at least a first element-forming region and a second element-forming region are formed. Wells are formed in respective ones of the element-forming regions of the semiconductor substrate, and the well of at least one element-forming region is of the first conductivity type. A guard ring of a second conductivity type is formed between the wells of the first and second element-forming regions, and a region of the first conductivity type having an impurity concentration lower than that of the well of the one element-forming region is formed between the guard ring and the well of the one element-forming region.

Abstract: A nonvolatile ferroelectric memory device has a plurality of ferroelectric memory cells. The ferroelectric memory cells include a first double gate cell for storing a bit of datum, the first double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the floating channel layer corresponding to the bit of datum stored in the first double gate cell; and a second double gate cell selectively turned on by a potential on a selection line to supply a potential of a sense line to the first double gate cell to control read and write operations of the first double gate cell. The present invention also provides methods for operating the nonvolatile ferroelectric memory device.

Abstract: A semiconductor device includes a plurality of gate electrodes, source and drain regions, a plurality of source contacts, a plurality of drain contacts, substrate contacts, and a salicide block. The gate electrodes are arrayed in parallel on a semiconductor region on a semiconductor substrate. The source and drain regions are formed in the semiconductor region on both sides of each gate electrode. The source contacts are formed on the source region. The drain contacts are formed on the drain region. The substrate contacts are formed on the semiconductor substrate and electrically connect to the semiconductor substrate. The salicide block is formed between the gate electrode and the plurality of drain contacts. The salicide block prevents silicidation on the drain region. The length of the salicide block in a channel length direction increases as the distance from the substrate contact increases.